Hi Everyone,
I was performing some benchmarking today. On a Skylake Core-i5-6400
machine, and in the past (May 30, 2020), I would see these performance
numbers:
RDRAND: 67 MB/s, ~38 cpb
RDSEED: 24 MB/s, ~105 cpb
I ran the same benchmarks today (January 2 2020) and the benchmark
program repor
Hello,
syzbot found the following issue on:
HEAD commit:cb4d9b52 usb: dwc3: drd: Improve dwc3_get_extcon() style
git tree: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git
usb-testing
console output: https://syzkaller.appspot.com/x/log.txt?x=131bf58f50
kernel config:
On Fri, Dec 18, 2020 at 11:57:08AM +0100, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> We are calling the same code for enable and disable the block in various
> parts of the driver. Put that code into a new function to reduce code
> duplication.
>
> Signed-off-by: Matthias Brugge
On Sat, Dec 19, 2020 at 08:52:07AM +0100, Christophe JAILLET wrote:
> In case of error, we should call 'clk_disable_unprepare()' to undo a
> previous 'clk_prepare_enable()' call, as already done in the remove
> function.
>
> Fixes: 406346d22278 ("hwrng: ingenic - Add hardware TRNG for Ingenic X183
On Sat, Jan 02, 2021 at 02:59:09PM +0100, Ard Biesheuvel wrote:
> Pavel reports that commit 17858b140bf4 ("crypto: ecdh - avoid unaligned
> accesses in ecdh_set_secret()") fixes one problem but introduces another:
> the unconditional memcpy() introduced by that commit may overflow the
> target buff
On Wed, Dec 23, 2020 at 12:09:49AM -0800, Eric Biggers wrote:
> This patchset adds 32-bit ARM assembly language implementations of
> BLAKE2b and BLAKE2s.
>
> As a prerequisite to adding these without copy-and-pasting lots of code,
> this patchset also reworks the existing BLAKE2b and BLAKE2s code
On Fri, Dec 18, 2020 at 11:57:07AM +0100, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> When trying to disable the block we bitwise or the control
> register with value zero. This is confusing as using bitwise or with
> value zero doesn't have any effect at all. Drop this as we alre
On Thu, Dec 17, 2020 at 07:55:16PM +0100, Ard Biesheuvel wrote:
> Counter mode is a stream cipher chaining mode that is typically used
> with inputs that are of arbitrarily length, and so a tail block which
> is smaller than a full AES block is rule rather than exception.
>
> The current ctr(aes)
On Thu, Dec 17, 2020 at 07:55:15PM +0100, Ard Biesheuvel wrote:
> Commit 69b6f2e817e5b ("crypto: arm64/aes-neon - limit exposed routines if
> faster driver is enabled") intended to hide modes from the plain NEON
> driver that are also implemented by the faster bit sliced NEON one if
> both are enab
On Wed, Dec 16, 2020 at 11:46:34AM +, Daniele Alessandrelli wrote:
> The Intel Keem Bay SoC has an Offload Crypto Subsystem (OCS) featuring a
> Hashing Control Unit (HCU) for accelerating hashing operations.
>
> This driver adds support for such hardware thus enabling hardware-accelerated
> ha
On Mon, Dec 14, 2020 at 08:02:24PM +, Corentin Labbe wrote:
> Hello
>
> For help testing on "crypto: sun4i-ss - Fix sparse endianness markers",
> I have added "stats" support like other allwinner's crypto drivers.
> Seeing stats showed a clear problem, the ciphers function were not used
> at a
On Mon, Dec 14, 2020 at 07:44:40PM +0800, Tian Tao wrote:
> Remove dev_err() messages after platform_get_irq*() failures.
> drivers/crypto/inside-secure/safexcel.c: line 1161 is redundant
> because platform_get_irq() already prints an error
>
> Generated by: scripts/coccinelle/api/platform_get_irq
On Sun, Dec 13, 2020 at 03:39:29PM +0100, Ard Biesheuvel wrote:
> Commit 86cd97ec4b943af3 ("crypto: arm/chacha-neon - optimize for non-block
> size multiples") refactored the chacha block handling in the glue code in
> a way that may result in the counter increment to be omitted when calling
> chac
On Fri, Dec 11, 2020 at 01:27:13PM +0100, Ard Biesheuvel wrote:
> Patch #2 puts the cipher API (which should not be used outside of the
> crypto API implementation) into an internal header file and module
> namespace
>
> Patch #1 is a prerequisite for this, to avoid having to make the chelsio
> dr
On Fri, Dec 11, 2020 at 09:42:47AM +0800, Tian Tao wrote:
> Remove including that don't need it.
>
> Signed-off-by: Tian Tao
> ---
> drivers/crypto/ccree/cc_driver.h | 1 -
> 1 file changed, 1 deletion(-)
Patch applied. Thanks.
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~her
On Thu, Dec 10, 2020 at 02:03:14PM -0600, Rob Herring wrote:
> PicoXcell has had nothing but treewide cleanups for at least the last 8
> years and no signs of activity. The most recent activity is a yocto vendor
> kernel based on v3.0 in 2015.
>
> Cc: Jamie Iles
> Cc: Herbert Xu
> Cc: "David S.
On Tue, Dec 08, 2020 at 12:34:02AM +0100, Ard Biesheuvel wrote:
> Follow the same approach as the arm64 driver for implementing a version
> of AES-NI in CBC mode that supports ciphertext stealing. This results in
> a ~2x speed increase for relatively short inputs (less than 256 bytes),
> which is r
On Mon, Dec 07, 2020 at 05:55:20PM +0100, Krzysztof Kozlowski wrote:
> E-mails to Kamil Konieczny to his Samsung address bounce with 550 (User
> unknown). Kamil no longer takes care about Samsung S5P SSS driver so
> remove the invalid email address from:
> - mailmap,
> - bindings maintainer entr
On Wed, Dec 09, 2020 at 06:50:14PM -0300, Fabio Estevam wrote:
> Since 5.10-rc1 i.MX is a devicetree-only platform and the existing
> .id_table support in this driver was only useful for old non-devicetree
> platforms.
>
> Remove the unused .id_table support.
>
> Signed-off-by: Fabio Estevam
> -
On Tue, Dec 08, 2020 at 03:34:41PM +0100, Ard Biesheuvel wrote:
> The signed long type used for printing the number of bytes processed in
> tcrypt benchmarks limits the range to -/+ 2 GiB, which is not sufficient
> to cover the performance of common accelerated ciphers such as AES-NI
> when benchma
On Mon, Dec 07, 2020 at 03:58:42PM +0800, Vic Wu wrote:
> The crypto mediatek driver has been replaced by the inside-secure
> driver now. Remove this driver to avoid having duplicate drivers.
>
> Signed-off-by: Vic Wu
> Acked-by: Ryder Lee
> ---
> drivers/crypto/Kconfig | 15 -
This patch moves the extern algorithm declarations into a header
file so that a number of compiler warnings are silenced.
Signed-off-by: Herbert Xu
diff --git a/drivers/crypto/vmx/aesp8-ppc.h b/drivers/crypto/vmx/aesp8-ppc.h
index 01774a4d26a2..5764d4438388 100644
--- a/drivers/crypto/vmx/aesp8-
On Thu, Dec 24, 2020 at 02:08:25PM +0800, Meng Yu wrote:
> Move elliptic curves definition to 'include/crypto/ecc_curve_defs.h',
> so all can use it,
>
> Signed-off-by: Meng Yu
> Reviewed-by: Zaibo Xu
> ---
> crypto/ecc.c| 1 -
> crypto/ecc.h| 37 +--
On Fri, Dec 18, 2020 at 10:30:22PM -0500, Thara Gopinath wrote:
> Export and import interfaces save and restore partial transformation
> states. The partial states were being stored and restored in struct
> sha1_state for sha1/hmac(sha1) transformations and sha256_state for
> sha256/hmac(sha256) tr
On Wed, Dec 16, 2020 at 11:59:06AM +0100, Luca Dariz wrote:
>
> @@ -432,12 +433,15 @@ static int hwrng_fillfn(void *unused)
> {
> long rc;
>
> + complete(&hwrng_started);
> while (!kthread_should_stop()) {
> struct hwrng *rng;
>
> rng = get_current_r
On Tue, Dec 15, 2020 at 06:28:11PM +0800, Tony W Wang-oc wrote:
> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
> On platforms with Zhaoxin CPUs supporting this X86 feature, when
> crc32c-intel and crc32c-generic are both registered, system will
> use crc32c-intel because its .c
On Thu, Dec 10, 2020 at 07:10:01PM +0800, Longfang Liu wrote:
> Add support for new algorithms of SEC accelerator on Kunpeng930,
> the driver and test case needs to be updated
>
> Longfang Liu (5):
> crypto: hisilicon/sec - add new type of sqe for Kunpeng930
> crypto: hisilicon/sec - add new s
Pavel reports that commit 17858b140bf4 ("crypto: ecdh - avoid unaligned
accesses in ecdh_set_secret()") fixes one problem but introduces another:
the unconditional memcpy() introduced by that commit may overflow the
target buffer if the source data is invalid, which could be the result of
intention
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