AW: problem with testing a CTR block cipher mode which is partially working

> Von: linux-crypto-ow...@vger.kernel.org > [linux-crypto-ow...@vger.kernel.org]" im Auftrag von "Corentin > LABBE [clabbe.montj...@gmail.com] > Gesendet: Montag, 30. März 2015 19:59 > An: linux-crypto@vger.kernel.org > Cc: linux-su...@googlegroups.com > Betreff: problem with testing a CTR block

AW: [RFC PATCH 1/6] crypto: sha512: implement base layer for SHA-512

> Von: Ard Biesheuvel [ard.biesheu...@linaro.org] > Gesendet: Sonntag, 29. März 2015 12:38 > An: Markus Stockhausen > Cc: linux-arm-ker...@lists.infradead.org; linux-crypto@vger.kernel.org; > samitolva...@google.com; herb...@gondor.apana.org.au; jussi.kivili...@iki.fi > Betreff

AW: [RFC PATCH 1/6] crypto: sha512: implement base layer for SHA-512

> Von: linux-crypto-ow...@vger.kernel.org > [linux-crypto-ow...@vger.kernel.org]" im Auftrag von "Ard > Biesheuvel [ard.biesheu...@linaro.org] > Gesendet: Samstag, 28. März 2015 23:10 > An: linux-arm-ker...@lists.infradead.org; linux-crypto@vger.kernel.org; > samitolva...@google.com; herb...@gon

AW: [PATCH] crypto: powerpc - move files to fix build error

> Von: Kim Phillips [kim.phill...@freescale.com] > Gesendet: Samstag, 7. März 2015 01:46 > An: Herbert Xu; Benjamin Herrenschmidt; Paul Mackerras; Michael Ellerman > Cc: Markus Stockhausen; linux-crypto@vger.kernel.org; > linuxppc-...@lists.ozlabs.org; linux-ker...@vger.kerne

[PATCH v1 3/3] crypto: powerpc/md5 - kernel config

[PATCH v1 3/3] crypto: powerpc/md5 - kernel config Integrate the module into the kernel config tree. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile index d400bf9..c6b25cba 100644 --- a/arch/powerpc/crypto/Makefile +++ b/arch/powerpc

[PATCH v1 1/3] crypto: powerpc/md5 - assembler

Stockhausen diff --git a/arch/powerpc/crypto/md5-asm.S b/arch/powerpc/crypto/md5-asm.S new file mode 100644 index 000..10cdf5b --- /dev/null +++ b/arch/powerpc/crypto/md5-asm.S @@ -0,0 +1,243 @@ +/* + * Fast MD5 implementation for PPC + * + * Copyright (c) 2015 Markus Stockhausen + * + * This

[PATCH v1 2/3] crypto: powerpc/md5 - glue

ion. + * + * Copyright (c) 2015 Markus Stockhausen + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later vers

[PATCH v1 0/3] crypto: powerpc/md5

[PATCH v1 0/3] crypto: powerpc/md5 The following patches add support for optimized MD5 calculation on PPC processors. It completes the previous patches to provide a comprehensive IPsec algorithm support for low power routers without hardware crypto acceleration. The implementation is endian indep

AW: [PATCH v1 1/3] SHA1 for PPC/SPE - assembler

> Von: David Laight [david.lai...@aculab.com] > Gesendet: Mittwoch, 25. Februar 2015 13:01 > An: Markus Stockhausen; linux-crypto@vger.kernel.org > Cc: linuxppc-...@lists.ozlabs.org > Betreff: RE: [PATCH v1 1/3] SHA1 for PPC/SPE - assembler > > From: Markus Stockhausen > &

[PATCH v1 3/3] SHA1 for PPC/SPE - kernel config

[PATCH v1 3/3] SHA1 for PPC/SPE - kernel config Integrate the module into the kernel config tree. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile index 1698fb9..d400bf9 100644 --- a/arch/powerpc/crypto/Makefile +++ b/arch/powerpc

[PATCH v1 2/3] SHA1 for PPC/SPE - glue

data. Kick out early for input chunks < 64 bytes and replace memset for context cleanup with simple loop. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/sha1_spe_glue.c b/arch/powerpc/sha1_spe_glue.c new file mode 100644 index 000..3e1d222 --- /dev/null +++ b/arch/powe

[PATCH v1 0/3] SHA1 for PPC/SPE

[PATCH v1 0/3] SHA1 for PPC/SPE The following patches add support for SIMD accelerated SHA1 calculation on PPC processors with SPE instruction set. The implementation takes care of the following constraints: - independant of processor endianess - save SPE registers for interrupt context compatib

[PATCH v1 1/3] SHA1 for PPC/SPE - assembler

stack. Clear this area in the stack afterwards to avoid information leakage. The code is endian independant. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/sha1-spe-asm.S b/arch/powerpc/sha1-spe-asm.S new file mode 100644 index 000..fcb6cf0 --- /dev/null +++ b/arch/powerpc/sha1

[PATCH v2 6/7] AES for PPC/SPE - glue code

[PATCH v2 6/7] AES for PPC/SPE - glue code Integrate the assembler modules into the kernel crypto framework. Take care to avoid long intervals of disabled preemption. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes_spe_glue.c b/arch/powerpc/crypto/aes_spe_glue.c new

[PATCH v2 7/7] AES for PPC/SPE - kernel config

[PATCH v2 7/7] AES for PPC/SPE - kernel config Integrate the module into the kernel configuration v2 changes - better explanation of use case in help text Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile index a07e763..1698fb9 100644

[PATCH v2 5/7] AES for PPC/SPE - ECB/CBC/CTR/XTS modes

[PATCH v2 5/7] AES for PPC/SPE - ECB/CBC/CTR/XTS modes The assembler block cipher module that controls the core AES functions. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-modes.S b/arch/powerpc/crypto/aes-spe-modes.S new file mode 100644 index 000..ad48032

[PATCH v2 1/7] AES for PPC/SPE - register defines

[PATCH v2 1/7] AES for PPC/SPE - register defines Define some register aliases for better readability. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-regs.h b/arch/powerpc/crypto/aes-spe-regs.h new file mode 100644 index 000..30d217b --- /dev/null +++ b/arch

[PATCH v2 3/7] AES for PPC/SPE - assembler core

ast" call modules without any stack handling or register saving. The caller must take care of that part. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-core.S b/arch/powerpc/crypto/aes-spe-core.S new file mode 100644 index 000..5dc6bce --- /dev/null +++

[PATCH v2 4/7] AES for PPC/SPE - key handling

[PATCH v2 4/7] AES for PPC/SPE - key handling Key generation for big endian core routines. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-keys.S b/arch/powerpc/crypto/aes-spe-keys.S new file mode 100644 index 000..be8090f --- /dev/null +++ b/arch/powerpc/crypto

[PATCH v2 2/7] AES for PPC/SPE - aes tables

changes - comment source of tables - use macros for rotated value expansion Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-tab-4k.S b/arch/powerpc/crypto/aes-tab-4k.S new file mode 100644 index 000..e099e99 --- /dev/null +++ b/arch/powerpc/crypto/aes-tab-4k.S @@ -0,0

[PATCH v2 0/7] AES for PPC/SPE

[PATCH v2 0/7] AES for PPC/SPE The following patches add support for 64bit accelerated AES calculation on PPC processors with SPE instruction set. Besides the AES core module it implements ECB/CBC/CTR/XTS as block ciphers. The implementation takes care of the following constraints: - save SPE re

AW: [PATCH v1 2/7] AES for PPC/SPE - aes tables

> Von: linux-crypto-ow...@vger.kernel.org > [linux-crypto-ow...@vger.kernel.org]" im Auftrag von "Segher > Boessenkool [seg...@kernel.crashing.org] > Gesendet: Montag, 16. Februar 2015 15:37 > An: David Laight > Cc: Markus Stockhausen; linux-crypto@

[PATCH v1 3/7] AES for PPC/SPE - assembler core

ast" call modules without any stack handling or register saving. The caller must take care of that part. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-core.S b/arch/powerpc/crypto/aes-spe-core.S new file mode 100644 index 000..5dc6bce --- /dev/null +++

[PATCH v1 5/7] AES for PPC/SPE - ECB/CBC/CTR/XTS modes

[PATCH v1 5/7] AES for PPC/SPE - ECB/CBC/CTR/XTS modes The assembler block cipher module that controls the core AES functions. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-modes.S b/arch/powerpc/crypto/aes-spe-modes.S new file mode 100644 index 000..1141841

[PATCH v1 2/7] AES for PPC/SPE - aes tables

[PATCH v1 2/7] AES for PPC/SPE - aes tables 4K AES tables for big endian Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-tab-4k.S b/arch/powerpc/crypto/aes-tab-4k.S new file mode 100644 index 000..6bc1755 --- /dev/null +++ b/arch/powerpc/crypto/aes-tab-4k.S @@ -0,0

[PATCH v1 0/7] AES for PPC/SPE

[PATCH v1 0/7] AES for PPC/SPE The following patches add support for 64bit accelerated AES calculation on PPC processors with SPE instruction set. Besides the AES core module it implements ECB/CBC/CTR/XTS as block ciphers. The implementation takes care of the following constraints: - save SPE re

[PATCH v1 7/7] AES for PPC/SPE - kernel config

[PATCH v1 7/7] AES for PPC/SPE - kernel config Integrate the module into the kernel configuration Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile index a07e763..1698fb9 100644 --- a/arch/powerpc/crypto/Makefile +++ b/arch/powerpc

[PATCH v1 4/7] AES for PPC/SPE - key handling

[PATCH v1 4/7] AES for PPC/SPE - key handling Key generation for big endian core routines. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-keys.S b/arch/powerpc/crypto/aes-spe-keys.S new file mode 100644 index 000..55b258c --- /dev/null +++ b/arch/powerpc/crypto

[PATCH v1 1/7] AES for PPC/SPE - register defines

[PATCH v1 1/7] AES for PPC/SPE - register defines Define some register aliases for better readability. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes-spe-regs.h b/arch/powerpc/crypto/aes-spe-regs.h new file mode 100644 index 000..30d217b --- /dev/null +++ b/arch

[PATCH v1 6/7] AES for PPC/SPE - glue code

[PATCH v1 6/7] AES for PPC/SPE - glue code Integrate the assembler modules into the kernel crypto framework. Take care to avoid long intervals of disabled preemption. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/aes_spe_glue.c b/arch/powerpc/crypto/aes_spe_glue.c new

AW: AW: Best way to align key in AES context

> Von: linux-crypto-ow...@vger.kernel.org > [linux-crypto-ow...@vger.kernel.org]" im Auftrag von "Tadeusz Struk > [tadeusz.st...@intel.com] > Gesendet: Freitag, 13. Februar 2015 15:47 > An: Markus Stockhausen > Cc: linux-crypto@vger.kernel.org > Betreff: Re: A

AW: Best way to align key in AES context

Hi, I want to ensure that the key data in an AES ctx structure is 8 byte aligned to avoid aligment exceptions afterwards. Other fields don't need that restriction. At the moment I'm using the following (ugly) implementation. struct ppc_aes_ctx { u32 rounds; u32 *key_enc; u

[PATCH v2 2/3] SHA256 for PPC/SPE - glue

-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/sha256_spe_glue.c b/arch/powerpc/crypto/sha256_spe_glue.c new file mode 100644 index 000..f4a616f --- /dev/null +++ b/arch/powerpc/crypto/sha256_spe_glue.c @@ -0,0 +1,275 @@ +/* + * Glue code for SHA-256 implementation for SPE instructio

[PATCH v2 3/3] SHA256 for PPC/SPE - kernel config

[PATCH v2 3/3] SHA256 for PPC/SPE - kernel config Integrate the module into the kernel config tree. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile index 2926fb9..a07e763 100644 --- a/arch/powerpc/crypto/Makefile +++ b/arch/powerpc

[PATCH v2 1/3] SHA256 for PPC/SPE - assembler

registers Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/sha256-spe-asm.S b/arch/powerpc/crypto/sha256-spe-asm.S new file mode 100644 index 000..a334af7 --- /dev/null +++ b/arch/powerpc/crypto/sha256-spe-asm.S @@ -0,0 +1,323 @@ +/* + * Fast SHA-256 implementation for SPE

[PATCH v2 0/3] SHA256 for PPC/SPE

[PATCH v2 0/3] SHA256 for PPC/SPE The following patches add support for SIMD accelerated SHA256 calculation on PPC processors with SPE instruction set. The implementation takes care of the following constraints: - independant of processor endianess - save SPE registers for interrupt context com

AW: [PATCH v1 0/3] SHA256 for PPC/SPE

> Von: Conor O'Gorman [i...@conorogorman.net] > Gesendet: Freitag, 30. Januar 2015 13:02 > An: Markus Stockhausen; linux-crypto@vger.kernel.org > Cc: linuxppc-...@lists.ozlabs.org > Betreff: Re: [PATCH v1 0/3] SHA256 for PPC/SPE > > On 24/01/15 21:10, Markus Stockhause

Re: [PATCH v1 0/3] SHA256 for PPC/SPE

> Von: linux-crypto-ow...@vger.kernel.org > [linux-crypto-ow...@vger.kernel.org]" im Auftrag von "Herbert Xu > [herb...@gondor.apana.org.au] > Gesendet: Montag, 26. Januar 2015 01:18 > An: Markus Stockhausen > Cc: linux-crypto@vger.kernel.org; linuxppc-...@lists.ozla

[PATCH v1 2/3] SHA256 for PPC/SPE - glue

interrupt context fall back to generic implementation. Take a little care about small input data. Kick out early for input chunks < 64 bytes and replace memset for context cleanup with simple loop. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/sha256_spe_glue.c b/a

[PATCH v1 3/3] SHA256 for PPC/SPE - kernel config

[PATCH v1 3/3] SHA256 for PPC/SPE - kernel config Integrate the module into the kernel config tree. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/Makefile b/arch/powerpc/crypto/Makefile index 2926fb9..a07e763 100644 --- a/arch/powerpc/crypto/Makefile +++ b/arch/powerpc

[PATCH v1 1/3] SHA256 for PPC/SPE - assembler

. Signed-off-by: Markus Stockhausen diff --git a/arch/powerpc/crypto/sha256-spe-asm.S b/arch/powerpc/crypto/sha256-spe-asm.S new file mode 100644 index 000..fb385e1 --- /dev/null +++ b/arch/powerpc/crypto/sha256-spe-asm.S @@ -0,0 +1,312 @@ +/* + * Fast SHA-256 implementation for SPE

[PATCH v1 0/3] SHA256 for PPC/SPE

[PATCH v1 0/3] SHA256 for PPC/SPE The following patches add support for SIMD accelerated SHA256 calculation on PPC processors with SPE instruction set. The implementation takes care of the following constraints: - independant of processor endianess - fallback to generic code if called from inte

Getting vom synch to asynch algorithms

Hello, in the last weeks I programmed a small assembler optimized MIPS kernel module that provides basic IPsec algorithms CBC(AES), SHA1 and MD5. The OpenWrt driven router can now achieve higher throughputs than with standard modules. During my LAN direct-connect tests I noticed that the device w