On 03.10.2017 21:30, Krzysztof Kozlowski wrote:
> On Tue, Oct 03, 2017 at 04:57:43PM +0200, Kamil Konieczny wrote:
>
[...]
+static struct ahash_alg algs_sha256[] = {
+{
+ .init = s5p_hash_init,
+ .update = s5p_hash_update,
+ .final = s5p
On Tue, Oct 03, 2017 at 04:57:43PM +0200, Kamil Konieczny wrote:
> >> [...]
> >> +static struct ahash_alg algs_sha256[] = {
> >> +{
> >> + .init = s5p_hash_init,
> >> + .update = s5p_hash_update,
> >> + .final = s5p_hash_final,
> >> + .finup = s5p_hash_finu
On 30.09.2017 21:50, Krzysztof Kozlowski wrote:
> On Wed, Sep 27, 2017 at 02:25:50PM +0200, Kamil Konieczny wrote:
>> Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
>> It uses the crypto framework asynchronous hash api.
>> It is based on omap-sham.c driver.
>> S5P has some HW diff
On Wed, Sep 27, 2017 at 02:25:50PM +0200, Kamil Konieczny wrote:
> Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
> It uses the crypto framework asynchronous hash api.
> It is based on omap-sham.c driver.
> S5P has some HW differencies and is not implemented.
>
> Modifications in
Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
It uses the crypto framework asynchronous hash api.
It is based on omap-sham.c driver.
S5P has some HW differencies and is not implemented.
Modifications in s5p-sss:
- Add hash supporting structures and functions.
- Modify irq hand
