This patchset adds support for CoreSight STM IP block. It also makes
a little modification to the generic STM framework to cover the
CoreSight STM requirements. Full description follows the changelog.
Changes from v1:
- Added a definition of coresight_simple_func() in CS-STM driver to
avoid th
For some STM hardware (e.g. ARM CoreSight STM), the masterID associated
to a source is set at the hardware level and not user configurable.
Since the masterID information isn't available to SW, introducing
a new value of -1 to reflect this reality.
Signed-off-by: Chunyan Zhang
---
Documentation/
From: Pratik Patel
This driver adds support for the STM CoreSight IP block, allowing any
system compoment (HW or SW) to log and aggregate messages via a
single entity.
The CoreSight STM exposes an application defined number of channels
called stimulus port. Configuration is done using entries i
From: Mathieu Poirier
The System Trace Macrocell (STM) is an IP block falling under the
CoreSight umbrella. It's main purpose it so expose stimulus channels
to any system component for the purpose of information logging.
Bindings for this IP block adds a couple of items to the current
mandatory
There is already an interface of set_options, but no get_options yet.
Before setting any options, one would may want to see the current
status of that option by means of get_options interface. This
interface has been used in CoreSight STM driver.
Signed-off-by: Chunyan Zhang
---
drivers/hwtracin
From: Alexander Shishkin
By convention, the name of the stm policy directory in configfs consists of
the device name to which it applies and the actual policy name, separated
by a dot. Now, some devices already have dots in their names that separate
name of the actual device from its instance ide
From: Mathieu Poirier
Some architecture like ARM assign masterIDs statically at the HW design
phase, making masterID manipulation in the generic STM core irrelevant.
This patch adds a new 'mstatic' flag to struct stm_data that tells the
core that this specific STM device doesn't need explicit ma
Hi Guenter,
On 6 February 2016 at 07:54, Guenter Roeck wrote:
> On 02/05/2016 10:21 AM, Fu Wei wrote:
>>
>> On 5 February 2016 at 22:42, Guenter Roeck wrote:
>>>
>>> On 02/05/2016 01:51 AM, Fu Wei wrote:
Hi Guenter,
On 4 February 2016 at 13:17, Guenter Roeck wrote:
Fu Wei wrote:
if (action) {
wdd->min_timeout = 1;
wdd->max_timeout = U32_MAX / gwdt->clk;
} else {
wdd->min_timeout = 2;
wdd->max_timeout = U32_MAX / gwdt->clk * 2;
}
Why would the minimum timeout be 2? You can program WOR to timeout in
half a second, can't
On 02/06/2016 10:02 AM, Fu Wei wrote:
Hi Guenter,
On 6 February 2016 at 07:54, Guenter Roeck wrote:
On 02/05/2016 10:21 AM, Fu Wei wrote:
On 5 February 2016 at 22:42, Guenter Roeck wrote:
On 02/05/2016 01:51 AM, Fu Wei wrote:
Hi Guenter,
On 4 February 2016 at 13:17, Guenter Roeck wro
On Fri, 5 Feb 2016, Josh Cartwright wrote:
> Hey Alan-
>
> First off, thanks for all of your (and others') work on this.
>
> On Fri, Feb 05, 2016 at 03:29:58PM -0600, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > New bindings document for FPGA Region to support programming
> >
On 7 February 2016 at 02:55, Timur Tabi wrote:
> Fu Wei wrote:
>>
>> if (action) {
>> wdd->min_timeout = 1;
>> wdd->max_timeout = U32_MAX / gwdt->clk;
>> } else {
>> wdd->min_timeout = 2;
>> wdd->max_timeout = U32_MAX / gwdt->clk * 2;
>> }
>
>
> Why would the mi
On 7 February 2016 at 02:57, Guenter Roeck wrote:
> On 02/06/2016 10:02 AM, Fu Wei wrote:
>>
>> Hi Guenter,
>>
>> On 6 February 2016 at 07:54, Guenter Roeck wrote:
>>>
>>> On 02/05/2016 10:21 AM, Fu Wei wrote:
On 5 February 2016 at 22:42, Guenter Roeck wrote:
>
>
> On
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