Hello,
I am Mr. LAURENT EYADEMA from Republic of Togo.please read the attached
proposal.
Thanks in anticipation of your urgent response,
LAURENT EYADEMA
proposal.docx
Description: Binary data
Hello,
I am Mr. LAURENT EYADEMA from Republic of Togo.please read the attached
proposal.
Thanks in anticipation of your urgent response,
LAURENT EYADEMA
proposal.docx
Description: Binary data
On Wed, Feb 10, 2016 at 01:14:14PM -0700, Jonathan Corbet wrote:
> On Mon, 1 Feb 2016 13:32:56 +0200
> "Michael S. Tsirkin" wrote:
>
> > Looks like the HPET spec at intel.com got moved.
> > It isn't hard to find so drop the link, just mention
> > the revision assumed.
>
> Hmm...what I see sugges
Jonathan Corbet writes:
> [Adding Keith since you said you wanted to be a part of this - let us know
> when you've had enough!]
Thanks.
> - I would like to format directly to HTML if at all possible.
Agreed. asciidoc's docbook path seems to only increase the amount of
software involved.
>
Looks like the HPET spec at intel.com got moved.
It isn't hard to find so drop the link, just mention
the revision assumed.
Suggested-by: Thomas Gleixner
Signed-off-by: Michael S. Tsirkin
---
Changes from v1:
actually drop the links, just say "revision 1"
in case a new one ever
On Wed, 10 Feb 2016 16:03:38 +0200
Jani Nikula wrote:
> I'd like to clarify the end goal a bit more before deciding what to do
> next. In particular, is the aim to have asciidoc->HTML only or dual
> asciidoc->HTML and asciidoc->XML->whatever? Or independent
> asciidoc->HTML first, with the existi
Hi Fu Wei,
On 2/10/16 00:00, fu@linaro.org wrote:
From: Fu Wei
This can be a example of adding SBSA Generic Watchdog device node
into some dts files for the Soc which contains SBSA Generic Watchdog.
Acked-by: Arnd Bergmann
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Fu Wei
---
On Wed, 10 Feb 2016 09:07:22 +0100
Daniel Vetter wrote:
> I think for 4.6 it'd be best to go with the hybrid asciidoc->docbook
> toolchain, since that's less disruptive. And with that we can also
> fully concentrating on the frontend, and how it'll look and behave.
That can be fine, I'd just lik
On Sat, 30 Jan 2016 21:53:53 +0100
Peter Loeffler wrote:
> cor...@lwn.net told me that these regression postings haven't happened for
> several years. So i think we can remove it.
Applied to the docs tree, thanks.
jon
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On Mon, 1 Feb 2016 13:03:27 +0900
Masanari Iida wrote:
> This patch fix a typo witin HOWTO, which was translated in Japanese.
> Replace a word "kernlehacker" with "kernelhacker".
Wouldn't want to misspell Mr. Kernelhacker's name!
Applied, thanks.
jon
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On Mon, 1 Feb 2016 13:32:56 +0200
"Michael S. Tsirkin" wrote:
> Looks like the HPET spec at intel.com got moved.
> It isn't hard to find so drop the link, just mention
> the revision assumed.
Hmm...what I see suggests this patch doesn't do that...
> - * http://www.intel.com/hardwaredesign/hpets
On Tue, 2 Feb 2016 20:41:25 +0900
Masanari Iida wrote:
> This path fix spelling typos found in Documentation/i2c.
Applied to the docs tree, thanks.
jon
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On Mon, 8 Feb 2016 21:02:43 +0900
Masanari Iida wrote:
> This patch fix a spelling typo in device-drivers.tmpl.
Applied to the docs tree, thanks.
jon
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From: Thor Thayer
This patch enables the ECC for On-Chip RAM on machine startup. The ECC
has to be enabled before data is stored in memory otherwise the ECC will
fail on reads.
Signed-off-by: Thor Thayer
Acked-by: Dinh Nguyen
---
v10: No change
v9: Improve node release handling.
v8: Address
From: Thor Thayer
Adding the device tree entries and bindings needed to support
the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon
an earlier patch to declare and setup On-chip RAM properly.
http://www.spinics.net/lists/devicetree/msg51117.html
Signed-off-by: Thor Thayer
Acked-by:
From: Thor Thayer
This patch enables the ECC for L2 cache on machine startup. The ECC has to
be enabled before data is stored in memory otherwise the ECC will fail on
reads.
Signed-off-by: Thor Thayer
Acked-by: Dinh Nguyen
---
v10: No change
v9: Improve node put handling.
v8: Address communi
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
Each type of ECC is individually configurable.
Signed-off-by: Thor Thayer
---
v10: Changes noted by maintainer included: F
On 2016-02-10 17:53, Dan Williams wrote:
Yeah, I get that now. It's just that to me, something called
"AIRPLANE_MODE_CHANGE" seems like it should actually change airplane
mode on/off, which implies killing radios. I wouldn't have had the
problem if it was named AIRPLANE_MODE_INDICATOR_CHANGE, w
On 01/02/2016 20:59, Parav Pandit wrote:
> On Tue, Feb 2, 2016 at 12:10 AM, Tejun Heo wrote:
>> So, I'm really not gonna go for individual drivers defining resources
>> on their own. That's a trainwreck waiting to happen. There needs to
>> be a lot more scrutiny than that.
>>
> Not every low lev
On Wed, 2016-02-10 at 17:07 +0100, Johannes Berg wrote:
> On Mon, 2016-02-08 at 10:11 -0600, Dan Williams wrote:
> > I'd like to clarify a bit, so tell me if I'm correct or not. Using
> > RFKILL_OP_AIRPLANE_MODE_CHANGE does not actually change any device
> > state. It's just an indicator with no r
On Wed, 10 Feb 2016, Jani Nikula wrote:
>> On Wed, Feb 10, 2016 at 1:09 AM, Jonathan Corbet wrote:
>>> - I'm not sold on the new inclusion mechanism. Creating thousands of
>>>little files and tracking them for dependencies and such doesn't seem
>>>like a simplification or a path toward
On Mon, 2016-02-08 at 10:11 -0600, Dan Williams wrote:
> I'd like to clarify a bit, so tell me if I'm correct or not. Using
> RFKILL_OP_AIRPLANE_MODE_CHANGE does not actually change any device
> state. It's just an indicator with no relationship to any of the
> registered rfkill switches, right?
On Wed 2016-02-03 20:11:07, Jessica Yu wrote:
> diff --git a/kernel/module.c b/kernel/module.c
> index 71c77ed..9c16eb2 100644
> --- a/kernel/module.c
> +++ b/kernel/module.c
> @@ -2676,6 +2764,23 @@ static int copy_module_from_user(const void __user
> *umod, unsigned long len,
> return 0;
>
On 9 February 2016 at 10:00, wrote:
> From: Fu Wei
>
> According to Server Base System Architecture (SBSA) specification,
> the SBSA Generic Watchdog has two stage timeouts: the first signal (WS0)
> is for alerting the system by interrupt, the second one (WS1) is a real
> hardware reset.
> More
[Sorry this turned out a long email, I didn't have the time to write a
short one.]
On Wed, 10 Feb 2016, Daniel Vetter wrote:
> On Wed, Feb 10, 2016 at 1:09 AM, Jonathan Corbet wrote:
>> On Tue, 26 Jan 2016 14:08:45 +0200
>> Jani Nikula wrote:
>>
>>> I'm afraid we've done some overlapping work
On Wed, Feb 10, 2016 at 1:09 AM, Jonathan Corbet wrote:
> On Tue, 26 Jan 2016 14:08:45 +0200
> Jani Nikula wrote:
>
>> I'm afraid we've done some overlapping work in the mean time, but I'm
>> happy we've both looked at the tool chain, and can have a more
>> meaningful conversation now.
>
> [Addin
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