Re: [RESEND PATCH v2 4/4] PCI: Add support for enforcing all MMIO BARs to be page aligned

2016-06-20 Thread Yongji Xie
On 2016/6/21 10:26, Bjorn Helgaas wrote: On Thu, Jun 02, 2016 at 01:46:51PM +0800, Yongji Xie wrote: When vfio passthrough a PCI device of which MMIO BARs are smaller than PAGE_SIZE, guest will not handle the mmio accesses to the BARs which leads to mmio emulations in host. This is because vfi

Re: [RESEND PATCH v2 1/4] PCI: Ignore resource_alignment if PCI_PROBE_ONLY was set\\

2016-06-20 Thread Yongji Xie
On 2016/6/21 9:43, Bjorn Helgaas wrote: On Thu, Jun 02, 2016 at 01:46:48PM +0800, Yongji Xie wrote: The resource_alignment will releases memory resources allocated by firmware so that kernel can reassign new resources later on. But this will cause the problem that no resources can be allocated

Re: [RESEND PATCH v2 3/4] PCI: Add a new option for resource_alignment to reassign alignment

2016-06-20 Thread Yongji Xie
On 2016/6/21 9:57, Bjorn Helgaas wrote: On Thu, Jun 02, 2016 at 01:46:50PM +0800, Yongji Xie wrote: When using resource_alignment kernel parameter, the current implement reassigns the alignment by changing resources' size which can potentially break some drivers. For example, the driver uses th

Re: [RESEND PATCH v2 2/4] PCI: Do not Use IORESOURCE_STARTALIGN to identify bridge resources

2016-06-20 Thread Yongji Xie
On 2016/6/21 9:50, Bjorn Helgaas wrote: On Thu, Jun 02, 2016 at 01:46:49PM +0800, Yongji Xie wrote: Now we use the IORESOURCE_STARTALIGN to identify bridge resources in __assign_resources_sorted(). That's quite fragile. We can't make sure that the PCI devices' resources will not use IORESOURCE_

Re: [RESEND PATCH v2 4/4] PCI: Add support for enforcing all MMIO BARs to be page aligned

2016-06-20 Thread Bjorn Helgaas
On Thu, Jun 02, 2016 at 01:46:51PM +0800, Yongji Xie wrote: > When vfio passthrough a PCI device of which MMIO BARs are > smaller than PAGE_SIZE, guest will not handle the mmio > accesses to the BARs which leads to mmio emulations in host. > > This is because vfio will not allow to passthrough one

Re: [RESEND PATCH v2 2/4] PCI: Do not Use IORESOURCE_STARTALIGN to identify bridge resources

2016-06-20 Thread Bjorn Helgaas
On Thu, Jun 02, 2016 at 01:46:49PM +0800, Yongji Xie wrote: > Now we use the IORESOURCE_STARTALIGN to identify bridge resources > in __assign_resources_sorted(). That's quite fragile. We can't > make sure that the PCI devices' resources will not use > IORESOURCE_STARTALIGN any more. Can you explai

Re: [RESEND PATCH v2 3/4] PCI: Add a new option for resource_alignment to reassign alignment

2016-06-20 Thread Bjorn Helgaas
On Thu, Jun 02, 2016 at 01:46:50PM +0800, Yongji Xie wrote: > When using resource_alignment kernel parameter, the current > implement reassigns the alignment by changing resources' size > which can potentially break some drivers. For example, the driver > uses the size to locate some register whose

Re: [RESEND PATCH v2 1/4] PCI: Ignore resource_alignment if PCI_PROBE_ONLY was set\\

2016-06-20 Thread Bjorn Helgaas
On Thu, Jun 02, 2016 at 01:46:48PM +0800, Yongji Xie wrote: > The resource_alignment will releases memory resources allocated > by firmware so that kernel can reassign new resources later on. > But this will cause the problem that no resources can be > allocated by kernel if PCI_PROBE_ONLY was set,

Re: [PATCH] rcutorture: Remove outdated config option description

2016-06-20 Thread Paul E. McKenney
On Mon, Jun 20, 2016 at 07:51:22AM +0900, SeongJae Park wrote: > CONFIG_RCU_TORTURE_TEST_RUNNABLE has removed by commit 4e9a073f60367 > ("torture: Remove CONFIG_RCU_TORTURE_TEST_RUNNABLE, simplify code") > entirely but the document has not updated. This commit updates the > document to remove the

[PATCH 3/6] MAINTAINERS: add Documentation/gpu and Documentation/gpu/i915.rst

2016-06-20 Thread Jani Nikula
We'll want to keep an eye on what's going on in these files. Signed-off-by: Jani Nikula --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cb88f724e07c..ce9c23dd02c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3857,6 +3857,7 @@ F:driv

[PATCH 4/6] Documentation/gpu: use recommended order of heading markers

2016-06-20 Thread Jani Nikula
While splitting the document up, the headings "shifted" from what pandoc generated. Use the following order for headings for consistency: == Document title == First = Second -- Third ~ Leave the lower level headings as they are; I think those are less import

[PATCH 0/6] Documentation: convert DocBook gpu.tmpl to reStructuredText

2016-06-20 Thread Jani Nikula
Hi all, this series converts the DocBook gpu.tmpl to reStructuredText, now that we have Sphinx support merged to docs-next and drm-next. I haven't really touched the content, this is just a fairly mechanical conversion and split up of the document. I'm sure there are small issues here and there, b

[PATCHv4 4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding

2016-06-20 Thread tthayer
From: Thor Thayer Add the device tree bindings needed to support the Altera Ethernet FIFO buffers on the Arria10 chip. Signed-off-by: Thor Thayer --- v2 No Change v3 Change to common compatible string based on maintainer comments Add local IRQ values. v4 Add compatible string for parent

Re: [PATCH 18/19] arm64:ilp32: add vdso-ilp32 and use for signal return

2016-06-20 Thread Andreas Schwab
Yury Norov writes: > diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c > index 2a0de6f..e48ea34 100644 > --- a/arch/arm64/kernel/vdso.c > +++ b/arch/arm64/kernel/vdso.c > @@ -40,6 +40,12 @@ extern char vdso_start, vdso_end; > static unsigned long vdso_pages; > static struct page

[PATCHv4 2/7] EDAC, altera: Make all private data structures static const.

2016-06-20 Thread tthayer
From: Thor Thayer The device private data structures should be converted from const struct edac_device_prv_data to static const struct edac_device_prv_data. Signed-off-by: Thor Thayer --- v4 New patch added for conversion. --- drivers/edac/altera_edac.c | 16 1 file changed

[PATCHv4 3/7] EDAC, altera: Share Arria10 check_deps & IRQ functions

2016-06-20 Thread tthayer
From: Thor Thayer In preparation for additional memory module ECCs, the IRQ and check_deps() functions are being made available to all the memory buffers. Move them outside of the OCRAM only area. Signed-off-by: Thor Thayer --- v2 New patch. Move shared functions outside OCRAM only area. v3 C

[PATCHv4 0/7] Add Ethernet EDAC & peripheral init functions

2016-06-20 Thread tthayer
From: Thor Thayer This patch set adds the Ethernet EDAC and memory initialization functions for Altera's Arria10 peripherals. The ECC memory init functions are common to all the peripheral memory buffers (to follow in later patches). Thor Thayer (7): EDAC, altera: Add panic flag check to A10 I

[PATCHv4 1/7] EDAC, altera: Add panic flag check to A10 IRQ

2016-06-20 Thread tthayer
From: Thor Thayer In preparation for additional memory module ECCs, the IRQ function will check a panic flag before doing a kernel panic on double bit errors. OCRAM uncorrectable errors cause a panic because sleep/resume functions and FPGA contents during sleep are stored in OCRAM. ECCs on peri

[PATCHv4 5/7] EDAC, altera: Add Arria10 ECC memory init functions

2016-06-20 Thread tthayer
From: Thor Thayer In preparation for additional memory module ECCs, add the memory initialization functions and helper functions used for memory initialization. Signed-off-by: Thor Thayer --- v2: Specify INTMODE selection -> IRQ on each ECC error. Insert functions above memory-specific func

[PATCHv4 6/7] EDAC, altera: Add Arria10 Ethernet EDAC support

2016-06-20 Thread tthayer
From: Thor Thayer Add Altera Arria10 Ethernet FIFO memory EDAC support. Update to support a common compatibility string for all ethernet FIFOs in the DT. Signed-off-by: Thor Thayer --- v2 Remove (void *) cast from altr_edac_device_of_match[] Addition of panic flag to ethernet private data.

[PATCHv4 7/7] ARM: dts: Add Arria10 Ethernet EDAC devicetree entry

2016-06-20 Thread tthayer
From: Thor Thayer Add the device tree entries needed to support the Altera Ethernet FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer --- v2 No change v3 Add interrupts for SBERR and DBERR. v4 No change --- arch/arm/boot/dts/socfpga_arria10.dtsi | 16 1 fil

Re: [PATCH 14/19] arm64: ilp32: add sys_ilp32.c and a separate table (in entry.S) to use it

2016-06-20 Thread Yury Norov
On Sat, Jun 18, 2016 at 02:54:23AM +0300, Yury Norov wrote: > From: Andrew Pinski > > Add a separate syscall-table for ILP32, which dispatches either to native > LP64 system call implementation or to compat-syscalls, as appropriate. > > Signed-off-by: Andrew Pinski > Signed-off-by: Yury Norov