Re: [PATCH v4 0/4] Application Data Integrity feature introduced by SPARC M7

On 01/12/2017 05:22 PM, Khalid Aziz wrote: On 01/12/2017 10:53 AM, Dave Hansen wrote: On 01/12/2017 08:50 AM, Khalid Aziz wrote: 2. Any shared page that has ADI protection enabled on it, must stay ADI protected across all processes sharing it. Is that true? What happens if a page with ADI

Re: [PATCH v2 7/7] uapi: export all headers under uapi directories

On Thu, Jan 12, 2017 at 05:32:09PM +0100, Nicolas Dichtel wrote: > What I was trying to say is that I export those directories like other are. > Removing those files is not related to that series. Perhaps the correct solution is to only copy files matching "*.h" to reduce the risk of copying

Re: [PATCH v4 0/4] Application Data Integrity feature introduced by SPARC M7

On 01/12/2017 10:53 AM, Dave Hansen wrote: On 01/12/2017 08:50 AM, Khalid Aziz wrote: 2. Any shared page that has ADI protection enabled on it, must stay ADI protected across all processes sharing it. Is that true? What happens if a page with ADI tags set is accessed via a PTE without the

[PATCH] Documentation: cpuset: Fix 'cpuset.tasks' -> 'tasks'

This looks like it was accidentally caught up in e21a05cb (doc: cpuset: Update the cpuset flag file, 2010-02-24). While I'm touching the line, also fix the posessive "cpusets" -> "cpuset's". Signed-off-by: W. Trevor King --- Documentation/cgroup-v1/cpusets.txt | 2 +- 1 file

Re: [linux-sunxi] Re: [PATCH 2/5] clk: sunxi-ng: add support for V3s CCU

Hi, On Wed, Jan 11, 2017 at 11:55:16AM +0800, Icenowy Zheng wrote: > > 2017年1月11日 02:10于 Maxime Ripard 写道： > > > > On Tue, Jan 03, 2017 at 11:16:26PM +0800, Icenowy Zheng wrote: > > > V3s has a similar but cut-down CCU to H3. > > > > > > Add support for it.

Re: [PATCH v4 0/4] Application Data Integrity feature introduced by SPARC M7

On 01/12/2017 08:50 AM, Khalid Aziz wrote: > 2. Any shared page that has ADI protection enabled on it, must stay ADI > protected across all processes sharing it. Is that true? What happens if a page with ADI tags set is accessed via a PTE without the ADI enablement bit set? > COW creates an

Re: [PATCH 2/5] clk: sunxi-ng: add support for V3s CCU

On Thu, Jan 12, 2017 at 03:44:53AM +0800, Icenowy Zheng wrote: > > > 12.01.2017, 03:40, "Icenowy Zheng" : > > 11.01.2017, 02:10, "Maxime Ripard" : > >>  On Tue, Jan 03, 2017 at 11:16:26PM +0800, Icenowy Zheng wrote: > >>>   V3s has a similar

Re: [PATCH v2 7/7] uapi: export all headers under uapi directories

Le 12/01/2017 à 17:28, Jan Engelhardt a écrit : > On Thursday 2017-01-12 16:52, Nicolas Dichtel wrote: > >> Le 09/01/2017 à 13:56, Christoph Hellwig a écrit : >>> On Fri, Jan 06, 2017 at 10:43:59AM +0100, Nicolas Dichtel wrote: Regularly, when a new header is created in include/uapi/, the

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Thu, Jan 12, 2017 at 03:55:58PM +, Catalin Marinas wrote: > On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > > On 11/01/17 18:06, Catalin Marinas wrote: > > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > > >> diff --git a/arch/arm64/mm/proc.S

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > On 11/01/17 18:06, Catalin Marinas wrote: > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > >> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > >> index 32682be..9ee46df 100644 > >> ---

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:40:52PM +, Mark Rutland wrote: > On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > > On 11/01/17 18:06, Catalin Marinas wrote: > > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > > >> diff --git a/arch/arm64/mm/proc.S

[PATCH 03/37] PCI: dwc: dra7xx: Populate cpu_addr_fixup ops

Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding cpu address. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/dwc/pci-dra7xx.c

[PATCH 10/37] PCI: dwc: designware: Fix style errors in pcie-designware.c

No functional change. Fix all checkpatch warnings and check errors in pcie-designware.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.c | 42 ++--- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git

[PATCH 11/37] PCI: dwc: Split pcie-designware.c into host and core files

Split pcie-designware.c into pcie-designware-host.c that contains the host specific parts of the driver and pcie-designware.c that contains the parts used by both host driver and endpoint driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/Makefile |

[PATCH 14/37] PCI: endpoint: Add EP core layer to enable EP controller and EP functions

Introduce a new EP core layer in order to support endpoint functions in linux kernel. This comprises of EPC library (Endpoint Controller Library) and EPF library (Endpoint Function Library). EPC library implements functions that is specific to an endpoint controller and EPF library implements

[PATCH 13/37] PCI: dwc: Remove dependency of designware to CONFIG_PCI

CONFIG_PCI is used to enable the host mode PCI. In preparation for adding endpoint mode support to designware driver, remove the dependency of designware to CONFIG_PCI and make only the host specific part depend on CONFIG_PCI. Signed-off-by: Kishon Vijay Abraham I ---

[PATCH 16/37] PCI: endpoint: Introduce configfs entry for configuring EP functions

Introduce a new configfs entry to configure the EP function (like configuring the standard configuration header entries) and to bind the EP function with EP controller. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/Kconfig |4 +-

[PATCH 15/37] Documentation: PCI: Guide to use PCI Endpoint Core Layer

Add Documentation to help users use endpoint library to enable endpoint mode in the PCI controller and add new PCI endpoint functions. Signed-off-by: Kishon Vijay Abraham I --- Documentation/PCI/00-INDEX |2 + Documentation/PCI/endpoint/pci-endpoint.txt |

[PATCH 02/37] PCI: dwc: designware: Add new *ops* for cpu addr fixup

Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for host mode where the

[PATCH 19/37] PCI: endpoint: functions: Add an EP function to test PCI

This adds a new endpoint function driver (to program the virtual test device) making use of the EP-core library. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/Kconfig |2 + drivers/pci/endpoint/Makefile |3 +-

[PATCH 24/37] PCI: dwc: designware: Add EP mode support

Add endpoint mode support to designware driver. This uses the EP Core layer introduced recently to add endpoint mode support. *Any* function driver can now use this designware device in order to achieve the EP functionality. Signed-off-by: Kishon Vijay Abraham I ---

[PATCH 23/37] PCI: dwc: Add *ops* to start and stop pcie link

Add start_link and stop_link ops in dw_pcie_ops to start or stop the link. This will be used by endpoint functions to start the link once the setup has been done. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pcie-designware.h |2 ++ 1 file changed, 2

[PATCH 26/37] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently

No functional change. Split dra7xx_pcie_enable_interrupts into dra7xx_pcie_enable_wrapper_interrupts and dra7xx_pcie_enable_msi_interrupts so that wrapper interrupts and msi interrupts can be enabled independently. This is in preparation for adding EP mode support to dra7xx driver since EP mode

[PATCH 27/37] PCI: dwc: dra7xx: Add EP mode support

The PCIe controller integrated in dra7xx SoCs is capable of operating in endpoint mode. Add endpoint mode support to dra7xx driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/Kconfig | 31 +- drivers/pci/dwc/Makefile |4 +-

[PATCH 07/37] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init

No functional change. Get device pointer at the beginning of dw_pcie_host_init instead of getting it all over dw_pcie_host_init. This is in preparation for splitting struct pcie_port into host and core structures (Once split pcie_port will not have device pointer). Signed-off-by: Kishon Vijay

[PATCH 28/37] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode

Add device tree binding documentation for pci dra7xx EP mode. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/ti-pci.txt | 37 ++ 1 file changed, 30 insertions(+), 7 deletions(-) diff --git

[PATCH 33/37] tools: PCI: Add a userspace tool to test PCI endpoint

Add a userspace tool to invoke the ioctls exposed by the PCI endpoint test driver to perform various PCI tests. Signed-off-by: Kishon Vijay Abraham I --- tools/pci/pcitest.c | 186 +++ 1 file changed, 186 insertions(+) create mode

[PATCH 30/37] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode

Update device tree binding documentation of TI's dra7xx PCI controller to include property for enabling legacy mode. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/ti-pci.txt |4 1 file changed, 4 insertions(+) diff --git

[PATCH 17/37] Documentation: PCI: Guide to use pci endpoint configfs

Add Documentation to help users use pci endpoint to configure pci endpoint function and to bind the endpoint function with endpoint controller. Signed-off-by: Kishon Vijay Abraham I --- Documentation/PCI/00-INDEX |2 +

[PATCH 36/37] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP

The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO in RC mode. However in EP mode, the host system is not able to access the MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it. Signed-off-by: Kishon

[PATCH 32/37] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver

Add Documentation for pci-endpoint-test driver. Signed-off-by: Kishon Vijay Abraham I --- Documentation/misc-devices/pci-endpoint-test.txt | 35 ++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt diff

[PATCH 35/37] MAINTAINERS: add PCI EP maintainer

Add maintainer for the newly introduced PCI EP framework. Signed-off-by: Kishon Vijay Abraham I --- MAINTAINERS |9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8672f18..021f676 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9407,6

[PATCH 21/37] PCI: dwc: Modify dbi accessors to take dbi_base as argument

dwc has 2 dbi address space labelled dbics and dbics2. The existing helper to access dbi address space can access only dbics. However dbics2 has to be accessed for programming the BAR registers in the case of EP mode. This is in preparation for adding EP mode support to dwc driver. Signed-off-by:

[PATCH 34/37] tools: PCI: Add sample test script to invoke pcitest

Add a simple test script that invokes the pcitest userspace tool to perform all the PCI endpoint tests (BAR tests, interrupt tests, read tests, write tests and copy tests). Signed-off-by: Kishon Vijay Abraham I --- tools/pci/pcitest.sh | 56

[PATCH 31/37] misc: Add host side pci driver for pci test function device

Add PCI endpoint test driver that can verify base address register, legacy interrupt/MSI interrupt and read/write/copy buffers between host and device. The corresponding pci-epf-test function driver should be used on the EP side. Signed-off-by: Kishon Vijay Abraham I ---

[PATCH 29/37] PCI: dwc: dra7xx: Workaround for errata id i870

According to errata i870, access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Accessing non 32-bit aligned data causes incorrect data in the target buffer if memcpy is used. Implement the workaround for this errata

[PATCH 25/37] dt-bindings: PCI: Add dt bindings for pci designware EP mode

Add device tree binding documentation for pci designware EP mode. Signed-off-by: Kishon Vijay Abraham I --- .../devicetree/bindings/pci/designware-pcie.txt| 26 ++-- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git

[PATCH 22/37] PCI: dwc: Modify dbi accessors to access data of 4/2/1 bytes

Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding

[PATCH 09/37] PCI: dwc: designware: Parse *num-lanes* property in dw_pcie_setup_rc

*num-lanes* dt property is parsed in dw_pcie_host_init. However *num-lanes* property is applicable to both root complex mode and endpoint mode. As a first step, move the parsing of this property outside dw_pcie_host_init. This is in preparation for splitting pcie-designware.c to pcie-designware.c

[PATCH 01/37] PCI: dwc: dra7xx: Group all host related setup in add_pcie_port

commit 150645b94348 ("PCI: dra7xx: Move struct pcie_port setup to probe function") moved host related setup to the probe function. However instead of cluttering the probe function with host related setup, group all host related setup in add_pcie_port function. This way when endpoint support is

[PATCH 04/37] PCI: dwc: designware: Move the register defines to designware header file

No functional change. Move the register defines and other macros from pcie-designware.c to pcie-designware.h. This is in preparation to split the pcie-designware.c file into designware core file and host specific file. While at that also fix a checkpatch warning. Signed-off-by: Kishon Vijay

[PATCH 06/37] PCI: dwc: Rename cfg_read/cfg_write to read/write

No functional change. dw_pcie_cfg_read/dw_pcie_cfg_write doesn't do anything specific to access configuration space. It can be just renamed to dw_pcie_read/dw_pcie_write and used to read/write data to dbi space. This is in preparation for added endpoint support to linux kernel. Cc: Jingoo Han

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On Wed, Jan 11, 2017 at 06:37:39PM +, Mark Rutland wrote: > On Wed, Jan 11, 2017 at 12:35:55PM -0600, Timur Tabi wrote: > > On 01/11/2017 12:33 PM, Mark Rutland wrote: > > >It'll need to affect all lines since the kconfig column needs to expand > > >by at least one character to fit

Re: [PATCH linux v2 0/6] drivers: hwmon: Add On-Chip Controller driver

> This patchset adds a hwmon driver to support the OCC (On-Chip Controller) > on the IBM POWER8 and POWER9 processors, from a BMC (Baseboard Management > Controller). The OCC is an embedded processor that provides real time > power and thermal monitoring. Please don't cc the I2C list for I2C