On Thu, 2017-06-08 at 05:37 -0700, Guenter Roeck wrote:
> On 06/08/2017 12:53 AM, Andrew Jeffery wrote:
> > On Wed, 2017-06-07 at 08:55 -0700, Guenter Roeck wrote:
> > > On Tue, Jun 06, 2017 at 04:32:30PM +0930, Andrew Jeffery wrote:
> > > > Add a basic driver for the MAX31785, focusing on the fan
On Thu, Jun 08, 2017 at 04:24:34PM +0100, Catalin Marinas wrote:
> On Sun, Jun 04, 2017 at 03:00:08PM +0300, Yury Norov wrote:
> > From: Philipp Tomsich
> >
> > ILP32 VDSO exports following symbols:
> > __kernel_rt_sigreturn;
> > __kernel_gettimeofday;
> > __kernel_clock_gettime;
> > __kernel
On 6/8/2017 2:58 AM, Christoph Hellwig wrote:
On Wed, Jun 07, 2017 at 02:17:32PM -0500, Tom Lendacky wrote:
Add warnings to let the user know when bounce buffers are being used for
DMA when SME is active. Since the bounce buffers are not in encrypted
memory, these notifications are to allow the
Hi Catalin, thanks for review.
On Thu, Jun 08, 2017 at 03:09:12PM +0100, Catalin Marinas wrote:
> On Sun, Jun 04, 2017 at 02:59:54PM +0300, Yury Norov wrote:
> > --- a/arch/arm64/Kconfig
> > +++ b/arch/arm64/Kconfig
> > @@ -402,7 +402,7 @@ config ARM64_ERRATUM_834220
> >
> > config ARM64_ERRATU
On 6/8/2017 1:05 AM, Andy Lutomirski wrote:
On Wed, Jun 7, 2017 at 12:14 PM, Tom Lendacky wrote:
The cr3 register entry can contain the SME encryption bit that indicates
the PGD is encrypted. The encryption bit should not be used when creating
a virtual address for the PGD table.
Create a new
On 08/06/2017 22:17, Boris Ostrovsky wrote:
> On 06/08/2017 05:02 PM, Tom Lendacky wrote:
>> On 6/8/2017 3:51 PM, Boris Ostrovsky wrote:
> What may be needed is making sure X86_FEATURE_SME is not set for PV
> guests.
And that may be something that Xen will need to control through eithe
On 06/08/2017 05:02 PM, Tom Lendacky wrote:
> On 6/8/2017 3:51 PM, Boris Ostrovsky wrote:
>>
>>>
What may be needed is making sure X86_FEATURE_SME is not set for PV
guests.
>>>
>>> And that may be something that Xen will need to control through either
>>> CPUID or MSR support for the PV g
://github.com/0day-ci/linux/commits/Tom-Lendacky/x86-Secure-Memory-Encryption-AMD/20170608-104147
config: sparc-defconfig (attached as .config)
compiler: sparc-linux-gcc (GCC) 6.2.0
reproduce:
wget
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
On 6/8/2017 3:51 PM, Boris Ostrovsky wrote:
What may be needed is making sure X86_FEATURE_SME is not set for PV
guests.
And that may be something that Xen will need to control through either
CPUID or MSR support for the PV guests.
Only on newer versions of Xen. On earlier versions (2-3 y
>
>> What may be needed is making sure X86_FEATURE_SME is not set for PV
>> guests.
>
> And that may be something that Xen will need to control through either
> CPUID or MSR support for the PV guests.
Only on newer versions of Xen. On earlier versions (2-3 years old) leaf
0x8007 is passed to
On 6/7/2017 9:40 PM, Nick Sarnie wrote:
On Wed, Jun 7, 2017 at 3:13 PM, Tom Lendacky wrote:
This patch series provides support for AMD's new Secure Memory Encryption (SME)
feature.
SME can be used to mark individual pages of memory as encrypted through the
page tables. A page of memory that is
On Tue, Jun 06, 2017 at 01:42:29PM -0700, David Rientjes wrote:
> On Tue, 6 Jun 2017, Roman Gushchin wrote:
>
> > Hi David!
> >
> > Thank you for sharing this!
> >
> > It's very interesting, and it looks like,
> > it's not that far from what I've suggested.
> >
> > So we definitily need to come
On Sun, Jun 04, 2017 at 03:00:08PM +0300, Yury Norov wrote:
> From: Philipp Tomsich
>
> ILP32 VDSO exports following symbols:
> __kernel_rt_sigreturn;
> __kernel_gettimeofday;
> __kernel_clock_gettime;
> __kernel_clock_getres.
>
> What shared object to use, kernel selects depending on result
On Sun, Jun 04, 2017 at 02:59:51PM +0300, Yury Norov wrote:
> All new 32-bit architectures should have 64-bit off_t type, but existing
> architectures has 32-bit ones.
>
> To handle it, new config option is added to arch/Kconfig that defaults
> ARCH_32BIT_OFF_T to be disabled for non-64 bit archit
Hi Yury,
On 04/06/17 13:00, Yury Norov wrote:
> From: Andrew Pinski
>
> Add a separate syscall-table for ILP32, which dispatches either to native
> LP64 system call implementation or to compat-syscalls, as appropriate.
(I'm still reading through this series trying to understand it, but spotted
On Thu, Jun 8, 2017 at 4:10 PM, Catalin Marinas wrote:
> On Sun, Jun 04, 2017 at 03:00:02PM +0300, Yury Norov wrote:
>> off_t is passed in register pair just like in aarch32.
>> In this patch corresponding aarch32 handlers are shared to
>> ilp32 code.
>
> Is the comment here relevant? IOW, do we
On 6/7/2017 9:38 PM, Nick Sarnie wrote:
On Wed, Jun 7, 2017 at 3:17 PM, Tom Lendacky wrote:
The IOMMU is programmed with physical addresses for the various tables
and buffers that are used to communicate between the device and the
driver. When the driver allocates this memory it is encrypted. I
On Sun, Jun 04, 2017 at 03:00:02PM +0300, Yury Norov wrote:
> off_t is passed in register pair just like in aarch32.
> In this patch corresponding aarch32 handlers are shared to
> ilp32 code.
Is the comment here relevant? IOW, do we have any AArch64/ILP32 syscall
where off_t is used as an argumen
On Sun, Jun 04, 2017 at 02:59:54PM +0300, Yury Norov wrote:
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -402,7 +402,7 @@ config ARM64_ERRATUM_834220
>
> config ARM64_ERRATUM_845719
> bool "Cortex-A53: 845719: a load might read incorrect data"
> - depends on COMPAT
> +
On 6/7/2017 5:06 PM, Boris Ostrovsky wrote:
On 06/07/2017 03:14 PM, Tom Lendacky wrote:
The cr3 register entry can contain the SME encryption bit that indicates
the PGD is encrypted. The encryption bit should not be used when creating
a virtual address for the PGD table.
Create a new function,
On Tue, 2017-06-06 at 17:19 +0800, Eryu Guan wrote:
> On Wed, May 31, 2017 at 09:08:20AM -0400, Jeff Layton wrote:
> > With btrfs, we can't really put the log on a separate device. What we
> > can do however is mirror the metadata across two devices and make the
> > data striped across all devices.
On 06/08/2017 12:53 AM, Andrew Jeffery wrote:
On Wed, 2017-06-07 at 08:55 -0700, Guenter Roeck wrote:
On Tue, Jun 06, 2017 at 04:32:30PM +0930, Andrew Jeffery wrote:
Add a basic driver for the MAX31785, focusing on the fan control
features but ignoring the temperature and voltage monitoring
fea
On Wed, Jun 07, 2017 at 02:17:32PM -0500, Tom Lendacky wrote:
> Add warnings to let the user know when bounce buffers are being used for
> DMA when SME is active. Since the bounce buffers are not in encrypted
> memory, these notifications are to allow the user to determine some
> appropriate actio
On Wed, 2017-06-07 at 08:55 -0700, Guenter Roeck wrote:
> On Tue, Jun 06, 2017 at 04:32:30PM +0930, Andrew Jeffery wrote:
> > Add a basic driver for the MAX31785, focusing on the fan control
> > features but ignoring the temperature and voltage monitoring
> > features of the device.
> >
> > This d
On Tue, 06 Jun 2017, Konstantin Ryabitsev
wrote:
> This is probably the lamest patch ever, but then again "Welcome to The
> Linux Kernel's documentation" is nearly equally lame. Really, we don't
> need to "Welcome" people to the documentation, just tell them what the
> site is about.
The origina
-Secure-Memory-Encryption-AMD/20170608-104147
config: um-x86_64_defconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=um SUBARCH=x86_64
All errors (new ones prefixed by >>):
I
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