On Mon, Jun 26, 2017 at 01:38:31PM +0200, Petr Mladek wrote:
> On Fri 2017-06-23 12:20:11, Luis R. Rodriguez wrote:
> > If we reach the limit of modprobe_limit threads running the next
> > request_module() call will fail. The original reason for adding
> > a kill was to do away with possible issues
When servicing mmap() reads from file holes the current DAX code allocates
a page cache page of all zeroes and places the struct page pointer in the
mapping->page_tree radix tree. This has three major drawbacks:
1) It consumes memory unnecessarily. For every 4k page that is read via a
DAX mmap()
dax_load_hole() will soon need to call dax_insert_mapping_entry(), so it
needs to be moved lower in dax.c so the definition exists.
dax_wake_mapping_entry_waiter() will soon be removed from dax.h and be made
static to dax.c, so we need to move its definition above all its callers.
Signed-off-by:
Now that we no longer insert struct page pointers in DAX radix trees we can
remove the special casing for DAX in page_cache_tree_insert(). This also
allows us to make dax_wake_mapping_entry_waiter() local to fs/dax.c,
removing it from dax.h.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
--
To be able to use the common 4k zero page in DAX we need to have our PTE
fault path look more like our PMD fault path where a PTE entry can be
marked as dirty and writeable as it is first inserted, rather than waiting
for a follow-up dax_pfn_mkwrite() => finish_mkwrite_fault() call.
Right now we c
When servicing mmap() reads from file holes the current DAX code allocates
a page cache page of all zeroes and places the struct page pointer in the
mapping->page_tree radix tree. This has three major drawbacks:
1) It consumes memory unnecessarily. For every 4k page that is read via a
DAX mmap()
Now that we no longer insert struct page pointers in DAX radix trees the
page cache code no longer needs to know anything about DAX exceptional
entries. Move all the DAX exceptional entry definitions from dax.h to
fs/dax.c.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
---
fs/dax.c
On 06/28/2017 03:26 AM, Viresh Kumar wrote:
> Users must be given an option to discard any constraints set by
> bootloaders. For example, consider that a constraint is set for the LCD
> controller's supply and the LCD driver isn't loaded by the kernel. If
> the user doesn't need to use the LCD devi
On 6/28/2017 4:36 AM, Joerg Roedel wrote:
Hi Tom,
Hi Joerg,
On Tue, Jun 27, 2017 at 10:12:30AM -0500, Tom Lendacky wrote:
---
drivers/iommu/amd_iommu.c | 30 --
drivers/iommu/amd_iommu_init.c | 34 --
drivers/iommu/a
a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Shaokun-Zhang/Add-HiSilicon-SoC-uncore-Performance-Monitoring-Unit-driver/20170628-070841
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save
drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c:274:1-3: WARNING: PTR_ERR_OR_ZERO
can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Fixes: 2dd3bcc1c8a7 ("drivers: perf: hisi: Add support for HiSilicon SoC DDRC
PMU driver")
:
https://github.com/0day-ci/linux/commits/Shaokun-Zhang/Add-HiSilicon-SoC-uncore-Performance-Monitoring-Unit-driver/20170628-070841
coccinelle warnings: (new ones prefixed by >>)
>> drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c:274:1-3: WARNING:
>> PTR_ERR_OR_ZERO can be used
Users must be given an option to discard any constraints set by
bootloaders. For example, consider that a constraint is set for the LCD
controller's supply and the LCD driver isn't loaded by the kernel. If
the user doesn't need to use the LCD device, then he shouldn't be forced
to honour the constr
:
https://github.com/0day-ci/linux/commits/Shaokun-Zhang/Add-HiSilicon-SoC-uncore-Performance-Monitoring-Unit-driver/20170628-070841
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
drivers/perf/hisilicon/hisi_uncore_hha_pmu.c:272:1-3: WARNING: PTR_ERR_OR_ZERO
can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Fixes: 2b8a651927f4 ("drivers: perf: hisi: Add support for HiSilicon SoC HHA
PMU driver")
CC
Hi Tom,
On Tue, Jun 27, 2017 at 10:12:30AM -0500, Tom Lendacky wrote:
> ---
> drivers/iommu/amd_iommu.c | 30 --
> drivers/iommu/amd_iommu_init.c | 34 --
> drivers/iommu/amd_iommu_proto.h | 10 ++
> drivers/iommu/am
:
https://github.com/0day-ci/linux/commits/Shaokun-Zhang/Add-HiSilicon-SoC-uncore-Performance-Monitoring-Unit-driver/20170628-070841
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c:348:1-3: WARNING: PTR_ERR_OR_ZERO
can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
Fixes: 05958712d8d4 ("drivers: perf: hisi: Add support for HiSilicon SoC L3C
PMU driver")
CC
This patch adds support HiSilicon SoC uncore PMU driver framework and
interfaces.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
drivers/perf/Kconfig | 7 +
drivers/perf/Makefile| 1 +
drivers/perf/hisilicon/Makefile | 1 +
driver
Add support HiSilicon SoC uncore PMU driver.
Signed-off-by: Shaokun Zhang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c0348bc..fbd664b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6072,6 +6072,13 @@ S: Maintained
F: driv
L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
SoC. This patch adds support for HHA PMU driver, Each HHA has own
control, counter and interrupt registers and is an separate PMU. For
each HHA PMU, it has 16-programable counters and supports 0x50 events,
event code is 8-bits
This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
DDRC has own control, counter and interrupt registers and is an separate
PMU. For each DDRC PMU, it has 8-fixed-purpose counters which have been
mapped to 8-events by hardware, it assumes that counter index is equal
to event co
This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
L3C has own control, counter and interrupt registers and is an separate
PMU. For each L3C PMU, it has 8-programable counters and supports 0x60
events, each event code is 8-bits and every counter is free-running.
Interrupt is sup
This patchset adds support for HiSilicon SoC uncore PMUs driver. It
include L3C, Hydra Home Agent (HHA) and DDRC.
Changes in v2:
* fix kbuild test robot error
* make hisi_uncore_ops static
Shaokun Zhang (6):
Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
drivers: perf:
This patch adds documentation for the uncore PMUs on HiSilicon SoC.
Signed-off-by: Shaokun Zhang
Signed-off-by: Anurup M
---
Documentation/perf/hisi-pmu.txt | 51 +
1 file changed, 51 insertions(+)
create mode 100644 Documentation/perf/hisi-pmu.txt
diff
On Wed, Dec 14, 2016 at 12:43 AM, Jonathan Corbet wrote:
> On Tue, 13 Dec 2016 16:20:59 +0100
> Dmitry Vyukov wrote:
>
>> Now that we have gcc plugins and in particular sancov plugin,
>> KCOV can be used with gcc 4.5+. Note this in the docs.
>
> Makes sense. Applied to docs-next, thanks.
Hi Jo
On Tue, Jun 27, 2017 at 08:54:07PM +0530, Aneesh Kumar K.V wrote:
>
>
> On Tuesday 27 June 2017 03:41 PM, Ram Pai wrote:
> >Pass the correct protection key value to the hash functions on
> >page fault.
> >
> >Signed-off-by: Ram Pai
> >---
> > arch/powerpc/include/asm/pkeys.h | 11 +++
>
27 matches
Mail list logo
