Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

2018-05-01 Thread Will Deacon
Hi Kim, On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote: > On Fri, 27 Apr 2018 17:09:14 +0100 > Will Deacon <will.dea...@arm.com> wrote: > > On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote: > > > On Fri, 27 Apr 2018 15:37:20 +0100 > > &

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

2018-04-27 Thread Will Deacon
Kim, [Ganapat: please don't let this discussion disrupt your PMU driver development. You can safely ignore it for now :)] On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote: > On Fri, 27 Apr 2018 15:37:20 +0100 > Will Deacon <will.dea...@arm.com> wrote: > > >

Re: [PATCH v4 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

2018-04-27 Thread Will Deacon
On Fri, Apr 27, 2018 at 08:15:25AM -0500, Kim Phillips wrote: > On Fri, 27 Apr 2018 10:30:27 +0100 > Mark Rutland wrote: > > On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote: > > > On Wed, 25 Apr 2018 14:30:47 +0530 > > > Ganapatrao Kulkarni

[PATCH] docs/memory-barriers.txt: Fix broken DMA vs MMIO ordering example

2018-03-27 Thread Will Deacon
t <cor...@lwn.net> Reported-by: Sinan Kaya <ok...@codeaurora.org> Signed-off-by: Will Deacon <will.dea...@arm.com> --- Documentation/memory-barriers.txt | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/Documentation/memory-barriers.txt b/Documenta

Re: [PATCH v2 1/2] acpi, spcr: Make SPCR avialable to other architectures

2017-12-13 Thread Will Deacon
a...@vger.kernel.org > > Cc: linux-ser...@vger.kernel.org > > Cc: Bhupesh Sharma <bhsha...@redhat.com> > > Cc: Lv Zheng <lv.zh...@intel.com> > > Cc: Thomas Gleixner <t...@linutronix.de> > > Cc: Ingo Molnar <mi...@redhat.com> > > Cc: "H. Pe

Re: [PATCH v6 0/6] Add HiSilicon SoC uncore Performance Monitoring Unit driver

2017-10-19 Thread Will Deacon
On Thu, Oct 19, 2017 at 01:29:18PM +0100, Mark Rutland wrote: > Will, are you happy to queue this? > > There's a minor fixup [1] needed in patch 2, but otherwise this looks > good to me, and builds cleanly. > > I've pushed out a branch [2] with that fix folded in, in case that's > easier for

Re: [PATCH] arm64: fix documentation on kernel pages mappings to HYP VA

2017-09-27 Thread Will Deacon
Wed Sep 13 21:08:30 2017 +0300 arm64: fix documentation on kernel pages mappings to HYP VA The Documentation/arm64/memory.txt says: When using KVM, the hypervisor maps kernel pages in EL2, at a fixed offset from the kernel VA (top 24bits of the kernel VA set to zero):

Re: [PATCH v3 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver

2017-07-20 Thread Will Deacon
On Thu, Jul 20, 2017 at 02:08:47PM +0100, Will Deacon wrote: > On Thu, Jul 20, 2017 at 08:54:36PM +0800, Zhangshaokun wrote: > > On 2017/7/19 17:17, Jonathan Cameron wrote: > > >> +Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has two > > >> HHAs

Re: [PATCH v3 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver

2017-07-20 Thread Will Deacon
On Thu, Jul 20, 2017 at 08:54:36PM +0800, Zhangshaokun wrote: > On 2017/7/19 17:17, Jonathan Cameron wrote: > >> +Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has two HHAs > >> +(0 - 1) and four DDRCs (0 - 3), respectively. > >> + > >> +HiSilicon SoC uncore PMU driver > >>

Re: [PATCH 1/1] doc: Update control-dependencies section of memory-barriers.txt

2017-04-07 Thread Will Deacon
, 1); > + WRITE_ONCE(b, 2); > do_something_else(); > > Signed-off-by: pierre Kuo <vichy@gmail.com> > --- > Documentation/memory-barriers.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Yup, looks like a typo since the do_something_else(

Re: [PATCH 03/20] asm-generic: Drop getrlimit and setrlimit syscalls from default list

2017-03-10 Thread Will Deacon
no in-tree architectures > are affected. > > Cc: Arnd Bergmann <a...@arndb.de> > Cc: James Hogan <james.ho...@imgtec.com> > Cc: linux-a...@vger.kernel.org > Cc: linux-snps-...@lists.infradead.org > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Will Deaco

Re: [PATCH] Documentation: Note QDF2400 SoC Erratum 44

2017-02-17 Thread Will Deacon
On Wed, Feb 15, 2017 at 04:54:07PM -0500, Christopher Covington wrote: > The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a > custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the > BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1 >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Will Deacon
On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > >

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Will Deacon
On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > > &

Re: [PATCH v4 2/4] arm64: Work around Falkor erratum 1003

2017-02-01 Thread Will Deacon
On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote: > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote: > > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote: > > > On 01/31/2017 12:56 PM, Marc Zyngier wrote: > > > > Given t

Re: [RFC] tty: pl011: Work around stuck BUSY bit on QDF2400

2017-01-31 Thread Will Deacon
On Mon, Jan 30, 2017 at 06:44:17PM -0500, Christopher Covington wrote: > N.B. I'm not confident that this patch is ready to be included as-is. > Rather I'm hoping for guidance from reviewers and maintainers on > broad implementation choices--whether A) the bitmask of flags to invert > makes sense

Re: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009

2017-01-31 Thread Will Deacon
On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote: > diff --git a/arch/arm64/include/asm/tlbflush.h > b/arch/arm64/include/asm/tlbflush.h > index deab52374119..fc434f421c7b 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -36,9

Re: [PATCH v5 2/2] arm64: Work around Falkor erratum 1009

2017-01-31 Thread Will Deacon
On Tue, Jan 31, 2017 at 12:42:23PM +, Mark Rutland wrote: > On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote: > > During a TLB invalidate sequence targeting the inner shareable domain, > > Falkor may prematurely complete the DSB before all loads and stores using > > the

Re: [PATCH v4 4/4] arm64: Work around Falkor erratum 1009

2017-01-27 Thread Will Deacon
On Wed, Jan 25, 2017 at 10:52:32AM -0500, Christopher Covington wrote: > During a TLB invalidate sequence targeting the inner shareable domain, > Falkor may prematurely complete the DSB before all loads and stores using > the old translation are observed. Instruction fetches are not subject to >

Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

2017-01-12 Thread Will Deacon
On Thu, Jan 12, 2017 at 03:55:58PM +, Catalin Marinas wrote: > On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote: > > On 11/01/17 18:06, Catalin Marinas wrote: > > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote: > > >> diff --git a/arch/arm64/mm/proc.S

Re: [RESEND PATCH v5 0/1] ARM64: ACPI: Update documentation for latest specification version

2016-06-14 Thread Will Deacon
On Tue, Jun 14, 2016 at 10:13:31AM +0100, Will Deacon wrote: > On Mon, Jun 13, 2016 at 03:41:54PM -0600, Al Stone wrote: > > This is a resend only: Ping? Last ping was 26 May; there has been zero > > response since then. Already have one ACK from Lorenzo; another from an >

Re: [PATCH] Documentation:Update Documentation/zh_CN/arm64/booting.txt

2016-04-21 Thread Will Deacon
/Documentation/zh_CN/arm64/booting.txt > index 1145bf8..c1dd968 100644 > --- a/Documentation/zh_CN/arm64/booting.txt > +++ b/Documentation/zh_CN/arm64/booting.txt > @@ -8,7 +8,7 @@ or if there is a problem with the translation. > > M: Will Deacon <will.dea...@arm.com>

Re: [PATCH] arm64: erratum: Workaround for Kryo reserved system register read

2016-04-11 Thread Will Deacon
On Mon, Apr 11, 2016 at 07:49:20AM +0100, James Morse wrote: > On 08/04/16 11:24, Marc Zyngier wrote: > > On 08/04/16 10:58, Suzuki K Poulose wrote: > >> On 07/04/16 18:31, Marc Zyngier wrote: > >> > +All system register encodings above use the form > + > +Op0, Op1,

Re: [PATCH v3] ARM64: ACPI: Update documentation for latest specification version

2016-04-08 Thread Will Deacon
id) > >-- Clarification on _CCA usage (Harb Abdulhamid) > >-- IORT moved to required from recommended (Hanjun Guo) > >-- Clarify IORT description (Hanjun Guo) > > > > Signed-off-by: Al Stone <al.st...@linaro.org> > > Cc: Catalin Marinas <