Hi Kim,
On Fri, Apr 27, 2018 at 11:56:25AM -0500, Kim Phillips wrote:
> On Fri, 27 Apr 2018 17:09:14 +0100
> Will Deacon <will.dea...@arm.com> wrote:
> > On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote:
> > > On Fri, 27 Apr 2018 15:37:20 +0100
> > &
Kim,
[Ganapat: please don't let this discussion disrupt your PMU driver
development. You can safely ignore it for now :)]
On Fri, Apr 27, 2018 at 10:46:29AM -0500, Kim Phillips wrote:
> On Fri, 27 Apr 2018 15:37:20 +0100
> Will Deacon <will.dea...@arm.com> wrote:
>
> >
On Fri, Apr 27, 2018 at 08:15:25AM -0500, Kim Phillips wrote:
> On Fri, 27 Apr 2018 10:30:27 +0100
> Mark Rutland wrote:
> > On Thu, Apr 26, 2018 at 05:06:24PM -0500, Kim Phillips wrote:
> > > On Wed, 25 Apr 2018 14:30:47 +0530
> > > Ganapatrao Kulkarni
t <cor...@lwn.net>
Reported-by: Sinan Kaya <ok...@codeaurora.org>
Signed-off-by: Will Deacon <will.dea...@arm.com>
---
Documentation/memory-barriers.txt | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/Documentation/memory-barriers.txt
b/Documenta
a...@vger.kernel.org
> > Cc: linux-ser...@vger.kernel.org
> > Cc: Bhupesh Sharma <bhsha...@redhat.com>
> > Cc: Lv Zheng <lv.zh...@intel.com>
> > Cc: Thomas Gleixner <t...@linutronix.de>
> > Cc: Ingo Molnar <mi...@redhat.com>
> > Cc: "H. Pe
On Thu, Oct 19, 2017 at 01:29:18PM +0100, Mark Rutland wrote:
> Will, are you happy to queue this?
>
> There's a minor fixup [1] needed in patch 2, but otherwise this looks
> good to me, and builds cleanly.
>
> I've pushed out a branch [2] with that fix folded in, in case that's
> easier for
Wed Sep 13 21:08:30 2017 +0300
arm64: fix documentation on kernel pages mappings to HYP VA
The Documentation/arm64/memory.txt says:
When using KVM, the hypervisor maps kernel pages in EL2, at a fixed
offset from the kernel VA (top 24bits of the kernel VA set to zero):
On Thu, Jul 20, 2017 at 02:08:47PM +0100, Will Deacon wrote:
> On Thu, Jul 20, 2017 at 08:54:36PM +0800, Zhangshaokun wrote:
> > On 2017/7/19 17:17, Jonathan Cameron wrote:
> > >> +Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has two
> > >> HHAs
On Thu, Jul 20, 2017 at 08:54:36PM +0800, Zhangshaokun wrote:
> On 2017/7/19 17:17, Jonathan Cameron wrote:
> >> +Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has two HHAs
> >> +(0 - 1) and four DDRCs (0 - 3), respectively.
> >> +
> >> +HiSilicon SoC uncore PMU driver
> >>
, 1);
> + WRITE_ONCE(b, 2);
> do_something_else();
>
> Signed-off-by: pierre Kuo <vichy@gmail.com>
> ---
> Documentation/memory-barriers.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Yup, looks like a typo since the do_something_else(
no in-tree architectures
> are affected.
>
> Cc: Arnd Bergmann <a...@arndb.de>
> Cc: James Hogan <james.ho...@imgtec.com>
> Cc: linux-a...@vger.kernel.org
> Cc: linux-snps-...@lists.infradead.org
> Cc: Catalin Marinas <catalin.mari...@arm.com>
> Cc: Will Deaco
On Wed, Feb 15, 2017 at 04:54:07PM -0500, Christopher Covington wrote:
> The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a
> custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the
> BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1
>
On Wed, Feb 01, 2017 at 06:22:44PM +, Catalin Marinas wrote:
> On Wed, Feb 01, 2017 at 05:59:48PM +, Will Deacon wrote:
> > On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote:
> > > On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote:
> > >
On Wed, Feb 01, 2017 at 05:49:34PM +, Catalin Marinas wrote:
> On Wed, Feb 01, 2017 at 05:41:05PM +, Will Deacon wrote:
> > On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote:
> > > On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote:
> > > &
On Wed, Feb 01, 2017 at 05:36:09PM +, Catalin Marinas wrote:
> On Wed, Feb 01, 2017 at 04:33:58PM +, Will Deacon wrote:
> > On Wed, Feb 01, 2017 at 11:29:22AM -0500, Christopher Covington wrote:
> > > On 01/31/2017 12:56 PM, Marc Zyngier wrote:
> > > > Given t
On Mon, Jan 30, 2017 at 06:44:17PM -0500, Christopher Covington wrote:
> N.B. I'm not confident that this patch is ready to be included as-is.
> Rather I'm hoping for guidance from reviewers and maintainers on
> broad implementation choices--whether A) the bitmask of flags to invert
> makes sense
On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h
> b/arch/arm64/include/asm/tlbflush.h
> index deab52374119..fc434f421c7b 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -36,9
On Tue, Jan 31, 2017 at 12:42:23PM +, Mark Rutland wrote:
> On Mon, Jan 30, 2017 at 06:08:17PM -0500, Christopher Covington wrote:
> > During a TLB invalidate sequence targeting the inner shareable domain,
> > Falkor may prematurely complete the DSB before all loads and stores using
> > the
On Wed, Jan 25, 2017 at 10:52:32AM -0500, Christopher Covington wrote:
> During a TLB invalidate sequence targeting the inner shareable domain,
> Falkor may prematurely complete the DSB before all loads and stores using
> the old translation are observed. Instruction fetches are not subject to
>
On Thu, Jan 12, 2017 at 03:55:58PM +, Catalin Marinas wrote:
> On Wed, Jan 11, 2017 at 06:22:08PM +, Marc Zyngier wrote:
> > On 11/01/17 18:06, Catalin Marinas wrote:
> > > On Wed, Jan 11, 2017 at 09:41:15AM -0500, Christopher Covington wrote:
> > >> diff --git a/arch/arm64/mm/proc.S
On Tue, Jun 14, 2016 at 10:13:31AM +0100, Will Deacon wrote:
> On Mon, Jun 13, 2016 at 03:41:54PM -0600, Al Stone wrote:
> > This is a resend only: Ping? Last ping was 26 May; there has been zero
> > response since then. Already have one ACK from Lorenzo; another from an
>
/Documentation/zh_CN/arm64/booting.txt
> index 1145bf8..c1dd968 100644
> --- a/Documentation/zh_CN/arm64/booting.txt
> +++ b/Documentation/zh_CN/arm64/booting.txt
> @@ -8,7 +8,7 @@ or if there is a problem with the translation.
>
> M: Will Deacon <will.dea...@arm.com>
On Mon, Apr 11, 2016 at 07:49:20AM +0100, James Morse wrote:
> On 08/04/16 11:24, Marc Zyngier wrote:
> > On 08/04/16 10:58, Suzuki K Poulose wrote:
> >> On 07/04/16 18:31, Marc Zyngier wrote:
> >>
> +All system register encodings above use the form
> +
> +Op0, Op1,
id)
> >-- Clarification on _CCA usage (Harb Abdulhamid)
> >-- IORT moved to required from recommended (Hanjun Guo)
> >-- Clarify IORT description (Hanjun Guo)
> >
> > Signed-off-by: Al Stone <al.st...@linaro.org>
> > Cc: Catalin Marinas <
24 matches
Mail list logo