Re: [PATCH] docs/memory-barriers.txt: Fix broken DMA vs MMIO ordering example

On Wed, Mar 28, 2018 at 10:57:11AM -0700, Tony Luck wrote: > On Wed, Mar 28, 2018 at 6:02 AM, Sinan Kaya wrote: > > +linux-ia64 > > Does IA64 follow this requirement? If not, is implementation planned? > > > > "no wmb() before writel()" > > > > Linus asked us to get rid of

Re: [PATCH] docs/memory-barriers.txt: Fix broken DMA vs MMIO ordering example

+linux-ia64 On 3/27/2018 11:02 AM, Paul E. McKenney wrote: > On Tue, Mar 27, 2018 at 02:11:27PM +0100, Will Deacon wrote: >> The section of memory-barriers.txt that describes the dma_Xmb() barriers >> has an incorrect example claiming that a wmb() is required after writing >> to coherent memory

Re: [PATCH] docs/memory-barriers.txt: Fix broken DMA vs MMIO ordering example

On Tue, Mar 27, 2018 at 02:11:27PM +0100, Will Deacon wrote: > The section of memory-barriers.txt that describes the dma_Xmb() barriers > has an incorrect example claiming that a wmb() is required after writing > to coherent memory in order for those writes to be visible to a device > before a

[PATCH] docs/memory-barriers.txt: Fix broken DMA vs MMIO ordering example

The section of memory-barriers.txt that describes the dma_Xmb() barriers has an incorrect example claiming that a wmb() is required after writing to coherent memory in order for those writes to be visible to a device before a subsequent MMIO access using writel() can reach the device. In fact,