Alan,
I merged SBI emulation for perf counters and config:
https://github.com/riscv/riscv-pk/pull/98
You should be able to write these CSRs.
Thanks,
Alex
On Mon, Apr 9, 2018 at 12:07 AM, Alan Kao wrote:
> On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote:
>> On Mon, 26 Mar 2018 00
On Mon, 09 Apr 2018 00:07:11 PDT (-0700), alan...@andestech.com wrote:
On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote:
On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote:
>This patch provide a basic PMU, riscv_base_pmu, which supports two
>general hardware even
On Thu, Apr 05, 2018 at 09:47:50AM -0700, Palmer Dabbelt wrote:
> On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote:
> >This patch provide a basic PMU, riscv_base_pmu, which supports two
> >general hardware event, instructions and cycles. Furthermore, this
> >PMU serves as a re
On Mon, 26 Mar 2018 00:57:54 PDT (-0700), alan...@andestech.com wrote:
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pm
Hi Alex,
On Mon, Apr 02, 2018 at 03:36:12PM +0800, Alan Kao wrote:
> On Sat, Mar 31, 2018 at 03:47:10PM -0700, Alex Solomatnikov wrote:
>
> The original guess was that maybe, an counter value on a hart is picked
> as the minusend, and an old counter value on another hart was recorded
> as the s
On Sat, Mar 31, 2018 at 03:47:10PM -0700, Alex Solomatnikov wrote:
The original guess was that maybe, an counter value on a hart is picked
as the minusend, and an old counter value on another hart was recorded
as the subtrahend but numerically larger. Then, the overflow causes
by that subtractio
You can add a skew between cores in qemu, something like this:
case CSR_INSTRET:
core_id()*return cpu_get_host_ticks()/10;
break;
case CSR_CYCLE:
return cpu_get_host_ticks();
break;
Alex
On Wed, Mar 28, 2018 at 7:30 PM, Alan Kao wrote:
> Hi Alex,
>
> I'm appreciated for
Hi Alex,
I'm appreciated for your reply and tests.
On Wed, Mar 28, 2018 at 03:58:41PM -0700, Alex Solomatnikov wrote:
> Did you test this code?
I did test this patch on QEMU's virt model with multi-hart, which is the only
RISC-V machine I have for now. But as I mentioned in
https://github.com/
On Wed, 28 Mar 2018 15:31:30 PDT (-0700), s...@sifive.com wrote:
Also, core IDs and socket IDs are wrong in perf report:
It looks like for this we need the stuff in topology.h. I've cobbled something
together quickly for Alex to use for now to see if that fixes other problems,
I'll submit a
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-S
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