On Thu, Mar 30, 2017 at 04:56:52PM +0100, Sudeep Holla wrote:
[...]
> > +static struct pm_qos_request debug_qos_req;
> > +static int idle_constraint = PM_QOS_DEFAULT_VALUE;
> > +module_param(idle_constraint, int, 0600);
> > +MODULE_PARM_DESC(idle_constraint, "Latency requirement in microseconds f
On 30/03/17 16:46, Mathieu Poirier wrote:
> On 29 March 2017 at 19:59, Leo Yan wrote:
>> On Wed, Mar 29, 2017 at 10:55:35AM -0600, Mathieu Poirier wrote:
>>
>> [...]
>>
So this is why add "idle_constraint" as a central place to control
power domain for CPU debug purpose and I also thin
On 25/03/17 18:23, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based Profiling Extension"
On 29/03/17 15:56, Mike Leach wrote:
[...]
>
> No - EDPRCR_COREPURQ and EDPRCR_CORENPDRQ have different semantics and
> purposes
>
> EDPRCR_COREPURQ is in the debug power domain an is tied to an external
> debug request that should be an input to the external (to the PE)
> system power contro
On 29 March 2017 at 19:59, Leo Yan wrote:
> On Wed, Mar 29, 2017 at 10:55:35AM -0600, Mathieu Poirier wrote:
>
> [...]
>
>> > So this is why add "idle_constraint" as a central place to control
>> > power domain for CPU debug purpose and I also think this is more
>> > friendly for hardware design,
On Thu, Mar 30, 2017 at 10:00:30AM +0100, Suzuki K Poulose wrote:
[...]
> Leo,
>
> Also, it would be good to restore the PRCR register back to the original state
> after we read the registers (if we changed them). I am exploring ways to make
> use of this feature on demand (e.g, tie it to sysrq-
On 30/03/17 02:03, Leo Yan wrote:
On Wed, Mar 29, 2017 at 03:56:23PM +0100, Mike Leach wrote:
[...]
+ /*
+* Unfortunately the CPU cannot be powered up, so return
+* back and later has no permission to access other
+* registers. For this case, should set 'idle_constraint'
+* t
On Wed, Mar 29, 2017 at 10:55:35AM -0600, Mathieu Poirier wrote:
[...]
> > So this is why add "idle_constraint" as a central place to control
> > power domain for CPU debug purpose and I also think this is more
> > friendly for hardware design, e.g. some platforms can enable partial
> > low power
On Wed, Mar 29, 2017 at 04:17:19PM +0100, Mike Leach wrote:
[...]
> >> >+out_powered_up:
> >> >+debug_os_unlock(drvdata);
> >>
> >> Question: Do we need a matching debug_os_lock() once we are done ?
> >
> > I have checked ARM ARMv8, but there have no detailed description for
> > this. I refer
On Wed, Mar 29, 2017 at 03:56:23PM +0100, Mike Leach wrote:
[...]
> >> > + /*
> >> > +* Unfortunately the CPU cannot be powered up, so return
> >> > +* back and later has no permission to access other
> >> > +* registers. For this case, should set 'idle_constraint'
> >> > +* to
On Wed, Mar 29, 2017 at 09:54:23AM +0800, Leo Yan wrote:
> Hi Mathieu,
>
> On Tue, Mar 28, 2017 at 10:50:10AM -0600, Mathieu Poirier wrote:
> > On Sun, Mar 26, 2017 at 02:23:14AM +0800, Leo Yan wrote:
>
> [...]
>
> > > +static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
> > >
On 29/03/17 11:37, Leo Yan wrote:
On Wed, Mar 29, 2017 at 11:31:03AM +0100, Suzuki K Poulose wrote:
On 29/03/17 11:27, Leo Yan wrote:
On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
[...]
+ if (mode == EDDEVID_IMPL_NONE) {
+ drvdata->edpcsr_present = fa
On Wed, Mar 29, 2017 at 11:07:35AM +0800, Leo Yan wrote:
> Hi Suzuki,
>
> On Mon, Mar 27, 2017 at 05:34:57PM +0100, Suzuki K Poulose wrote:
> > On 25/03/17 18:23, Leo Yan wrote:
>
> [...]
>
> > Leo,
> >
> > Thanks a lot for the quick rework. I don't fully understand (yet!) why we
> > need the
On 29 March 2017 at 04:07, Leo Yan wrote:
> Hi Suzuki,
>
> On Mon, Mar 27, 2017 at 05:34:57PM +0100, Suzuki K Poulose wrote:
>> On 25/03/17 18:23, Leo Yan wrote:
>
> [...]
>
>> Leo,
>>
>> Thanks a lot for the quick rework. I don't fully understand (yet!) why we
>> need the
>> idle_constraint. I w
Hi Leo
On 29 March 2017 at 02:54, Leo Yan wrote:
> Hi Mathieu,
>
> On Tue, Mar 28, 2017 at 10:50:10AM -0600, Mathieu Poirier wrote:
>> On Sun, Mar 26, 2017 at 02:23:14AM +0800, Leo Yan wrote:
>
> [...]
>
>> > +static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
>> > +{
>> > +
On Wed, Mar 29, 2017 at 11:31:03AM +0100, Suzuki K Poulose wrote:
> On 29/03/17 11:27, Leo Yan wrote:
> >On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
> >
> >[...]
> >
> >+if (mode == EDDEVID_IMPL_NONE) {
> >+drvdata->edpcsr_present = false;
> >>
On 29/03/17 11:27, Leo Yan wrote:
On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
[...]
+ if (mode == EDDEVID_IMPL_NONE) {
+ drvdata->edpcsr_present = false;
+ drvdata->edcidsr_present = false;
+ drvdata->edvidsr_present = fals
On Wed, Mar 29, 2017 at 10:07:07AM +0100, Suzuki K Poulose wrote:
[...]
> >>>+ if (mode == EDDEVID_IMPL_NONE) {
> >>>+ drvdata->edpcsr_present = false;
> >>>+ drvdata->edcidsr_present = false;
> >>>+ drvdata->edvidsr_present = false;
> >>>+ } else if (mode == EDDEVID
On 29/03/17 04:07, Leo Yan wrote:
Hi Suzuki,
On Mon, Mar 27, 2017 at 05:34:57PM +0100, Suzuki K Poulose wrote:
On 25/03/17 18:23, Leo Yan wrote:
[...]
Leo,
Thanks a lot for the quick rework. I don't fully understand (yet!) why we need
the
idle_constraint. I will leave it for Sudeep to com
Hi Suzuki,
On Mon, Mar 27, 2017 at 05:34:57PM +0100, Suzuki K Poulose wrote:
> On 25/03/17 18:23, Leo Yan wrote:
[...]
> Leo,
>
> Thanks a lot for the quick rework. I don't fully understand (yet!) why we
> need the
> idle_constraint. I will leave it for Sudeep to comment on it, as he is the
>
Hi Mathieu,
On Tue, Mar 28, 2017 at 10:50:10AM -0600, Mathieu Poirier wrote:
> On Sun, Mar 26, 2017 at 02:23:14AM +0800, Leo Yan wrote:
[...]
> > +static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
> > +{
> > + int timeout = DEBUG_WAIT_TIMEOUT;
> > +
> > + drvdata->edprsr
Hi Leo,
On Sun, Mar 26, 2017 at 02:23:14AM +0800, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Samp
On 25/03/17 18:23, Leo Yan wrote:
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension" introduces
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension" introduces several
sampling registers, e.g. we
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