On Mon, Apr 7, 2014 at 3:56 AM, Michael Heimpold wrote:
> Hi,
>
> I have a question regarding user-space gpio support with sysfs.
>
> Documentation/gpio/sysfs.txt states
>> GPIO signals have paths like /sys/class/gpio/gpio42/ (for GPIO #42)
>> and have the following read/write attributes:
>>
>>
On Wed, Mar 19, 2014 at 6:09 PM, Tien Hock Loh wrote:
> On Fri, Mar 7, 2014 at 11:14 PM, Josh Cartwright wrote:
>> On Mon, Mar 03, 2014 at 06:27:43PM +0800, [email protected] wrote:
>>> From: Tien Hock Loh
>>>
>>> Add driver support for Altera GPIO soft IP, including interrupts and I/O.
>>> Teste
On 03/25/2014 10:36 PM, Sebastian Hesselbarth wrote:
>> @@ -242,17 +244,28 @@ static void dwapb_configure_irqs(struct dwapb_gpio
>> *gpio,
>> irq_gc->reg_base = gpio->regs;
>> irq_gc->private = gpio;
>>
>> -ct = irq_gc->chip_types;
>> -ct->chip.irq_ack = irq_gc_ack_set_bit;
>>
Hi,
my queue, updated with latest comments I recevied.
#1 fixes a list corruption bug
#4 enabled mixed edge/level user
the dts changes are not part of the series as I believe that they have
been already picked up by the maintainer(s).
Sebastian
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According to irq_linear_revmap() comment, it is slightly faster compared
to irq_find_mapping() since we don't use a radix tree but a linear
mapping.
Signed-off-by: Sebastian Andrzej Siewior
---
drivers/gpio/gpio-dwapb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
The generic irq chip uses irq_gc_lock() for locking so the
enable/startup and type callbacks should use the same lock. None of
those registers (polarity, mask, enable) are used by the gpio part.
Signed-off-by: Sebastian Andrzej Siewior
---
drivers/gpio/gpio-dwapb.c | 20 +++-
1 f
The driver calls irq_alloc_domain_generic_chips() which creates a gc and
adds it to gc_list. The driver later then calls irq_setup_generic_chip()
which also initializes the gc and adds it to the gc_list() and this
corrupts the list. Enable LIST_DEBUG and you see the kernel complain.
This isn't requ
Right new have one irq chip running always in level mode. It would nicer
to have two irq chips where one is handling level type interrupts and
the other one is doing edge interrupts. So we can have at runtime two users
where one is using edge and the other level.
Signed-off-by: Sebastian Andrzej S
d->mask contains exact the same information as BIT(bit) so we could save
a few cycles here.
Signed-off-by: Sebastian Andrzej Siewior
---
drivers/gpio/gpio-dwapb.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/
Hello Linus,
On Thursday 27 March 2014 10:22:40, Linus Walleij wrote:
> On Tue, Mar 25, 2014 at 10:32 AM, Alexander Stein
> wrote:
>
> > From: Daniel Krueger
> >
> > This ensures that the output signal does not toggle if set to high.
> >
> > Signed-off-by: Daniel Krueger
> > Signed-off-by: Ale
From: Daniel Krueger
According to the datasheet, writing to the level register has no effect
when GPIO is programmed as input. Actually the the level register is
read-only when configured as input. Thus presetting the output level
before switching to output is _NOT_ possible. Any writes are lost!
On Mon, 2014-04-07 at 12:13 +0200, Sebastian Andrzej Siewior wrote:
>
> d->mask contains exact the same information as BIT(bit) so we could save
> a few cycles here.
ISTR that the benefit of saving cycles was questioned in previous
review comments. On ARM, the shift "comes for free".
I'm not sa
On Wed, Apr 2, 2014 at 6:01 PM, Maxime Ripard
wrote:
> On Wed, Apr 02, 2014 at 12:06:03PM +0200, Yegor Yefremov wrote:
>> On Tue, Mar 18, 2014 at 4:02 PM, Yegor Yefremov
>> wrote:
>> > I've an am335x-based board with tca6416. The interrupt output of the
>> > tca is connected to GPIO0_20 on my SoC
Hi,
IIRC I tested that and input and output are independant of each other.
If you set a pin as output and write a 1 into the output register, but you
connect the pin to ground physically output is "1" and input "0".
Which behaviour is the correct one for gpio_get?
Bye,
Fabian
Am Montag, 7. Apri
On Mon, Apr 07, 2014 at 04:00:43PM +0800, Tien Hock Loh wrote:
> On Wed, Mar 19, 2014 at 6:09 PM, Tien Hock Loh wrote:
> > On Fri, Mar 7, 2014 at 11:14 PM, Josh Cartwright
> > wrote:
> >> On Mon, Mar 03, 2014 at 06:27:43PM +0800, [email protected] wrote:
> >>> From: Tien Hock Loh
[..]
> >>> +
On 04/07/2014 02:26 PM, Gerhard Sittig wrote:
> On Mon, 2014-04-07 at 12:13 +0200, Sebastian Andrzej Siewior wrote:
>>
>> d->mask contains exact the same information as BIT(bit) so we could save
>> a few cycles here.
>
> ISTR that the benefit of saving cycles was questioned in previous
> review co
[ ignore this if you are busy :) ]
On Mon, 2014-04-07 at 20:26 +0200, Sebastian Andrzej Siewior wrote:
>
> On 04/07/2014 02:26 PM, Gerhard Sittig wrote:
> > On Mon, 2014-04-07 at 12:13 +0200, Sebastian Andrzej Siewior wrote:
> >>
> >> d->mask contains exact the same information as BIT(bit) so we
On Mon, 2014-03-31 at 11:23AM +0200, Ulf Hansson wrote:
> On 27 March 2014 16:25, Harini Katakam wrote:
[...]
> > +static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
> > +{
> > + struct platform_device *pdev = to_platform_device(dev);
> > + struct zynq_gpio *gpio =
On Mon, 2014-04-07 at 17:17 +0200, Fabian Vogt wrote:
>
> Hi,
>
> IIRC I tested that and input and output are independant of each other.
> If you set a pin as output and write a 1 into the output register, but you
> connect the pin to ground physically output is "1" and input "0".
> Which behavi
Hi,
Am Montag, 7. April 2014, 16:58:22 schrieb Alexandre Courbot:
> On Mon, Apr 7, 2014 at 3:56 AM, Michael Heimpold wrote:
> > Hi,
> >
> > I have a question regarding user-space gpio support with sysfs.
> >
> > Documentation/gpio/sysfs.txt states
> >> GPIO signals have paths like /sys/class/gpio
>> > @@ -81,9 +81,15 @@ static inline void zevio_gpio_port_set(struct
>> > zevio_gpio *c, unsigned pin,
>> > static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
>> > {
>> > struct zevio_gpio *controller = to_zevio_gpio(chip);
>> > + u32 val, dir;
>> >
>> > - /* Only reading a
Read gpio output value from ZEVIO_GPIO_OUTPUT.
The spin_lock is required to ensure the direction is not changed before reading
input/ouput value.
Signed-off-by: Axel Lin
---
drivers/gpio/gpio-zevio.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio
On Fri, Apr 04, 2014 at 09:25:50AM -0700, Guenter Roeck wrote:
> Is there a clean way to use any of those to implement interrupt support
> for this driver ? I thought about hijacking the SCI interrupt by registering
> an interrupt handler with acpi_install_sci_handler(), but that would restrict
>
On 04/07/2014 07:48 PM, Matthew Garrett wrote:
On Fri, Apr 04, 2014 at 09:25:50AM -0700, Guenter Roeck wrote:
Is there a clean way to use any of those to implement interrupt support
for this driver ? I thought about hijacking the SCI interrupt by registering
an interrupt handler with acpi_insta
On Mon, Apr 07, 2014 at 08:21:00PM -0700, Guenter Roeck wrote:
> On 04/07/2014 07:48 PM, Matthew Garrett wrote:
> >You shouldn't need to install an SCI handler - the way the hardware will
> >generate an SCI is to raise a GPE. If you know which GPE the device
> >raises (my recollection is that for m
This is a DT-only driver and it will be built only when CONFIG_OF is set.
So it's pointless to use of_match_ptr.
Signed-off-by: Axel Lin
---
drivers/gpio/gpio-zevio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-zevio.c b/drivers/gpio/gpio-zevio.c
index 2
On 04/07/2014 08:31 PM, Matthew Garrett wrote:
On Mon, Apr 07, 2014 at 08:21:00PM -0700, Guenter Roeck wrote:
On 04/07/2014 07:48 PM, Matthew Garrett wrote:
You shouldn't need to install an SCI handler - the way the hardware will
generate an SCI is to raise a GPE. If you know which GPE the devi
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