Hi,
On Tue, Jul 16, 2013 at 04:19:35PM +0800, Hein Tibosch wrote:
Hi Vikram,
On a OMAP4460, i2c-bus-3:
A driver (lm75) is causing many 'timeout waiting for bus ready' errors.
SDA remains high (as it should), but SCL remains low after a NACK.
The bus becomes _unusable for other clients_.
On 7/16/2013 5:03 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 16, 2013 at 04:19:35PM +0800, Hein Tibosch wrote:
Hi Vikram,
On a OMAP4460, i2c-bus-3:
A driver (lm75) is causing many 'timeout waiting for bus ready' errors.
SDA remains high (as it should), but SCL remains low after a NACK.
The
Hi Hein, Felipe
On 07/16/2013 12:42 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 16, 2013 at 05:33:47PM +0800, Hein Tibosch wrote:
On 7/16/2013 5:03 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 16, 2013 at 04:19:35PM +0800, Hein Tibosch wrote:
Hi Vikram,
On a OMAP4460, i2c-bus-3:
A driver (lm75)
On Sat, Jul 13, 2013 at 02:36:43PM +0900, Shinya Kuribayashi wrote:
Hi,
Now I've had a look at the whole discussion.
Basically, DW I2C core provides a good enough (and quite direct) way
to control tHIGH and tLOW timing specs, *HCNT and *LCNT registers.
But from my experience (with a
Hi,
On Tue, Jul 16, 2013 at 02:01:11PM +0300, Grygorii Strashko wrote:
On a OMAP4460, i2c-bus-3:
A driver (lm75) is causing many 'timeout waiting for bus ready' errors.
SDA remains high (as it should), but SCL remains low after a NACK.
The bus becomes _unusable for other clients_.
While
Hi Felipe,
On 07/16/2013 02:27 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 16, 2013 at 02:01:11PM +0300, Grygorii Strashko wrote:
On a OMAP4460, i2c-bus-3:
A driver (lm75) is causing many 'timeout waiting for bus ready' errors.
SDA remains high (as it should), but SCL remains low after a NACK.
Hi,
(when replying, can you add some blank lines around your reply and the
previous mail, it's quite difficult to find your replies with so many
quote marks () around)
On Tue, Jul 16, 2013 at 03:08:04PM +0300, Grygorii Strashko wrote:
Hi Felipe,
On 07/16/2013 02:27 PM, Felipe Balbi wrote:
Hi,
Hi Grygorii, Filipe,
On 7/16/2013 9:00 PM, Felipe Balbi wrote:
On Tue, Jul 16, 2013 at 03:08:04PM +0300, Grygorii Strashko wrote:
Hi Felipe,
On 07/16/2013 02:27 PM, Felipe Balbi wrote:
Hi,
On Tue, Jul 16, 2013 at 02:01:11PM +0300, Grygorii Strashko wrote:
On a OMAP4460, i2c-bus-3:
A
Intel's LGA2011 chips (Core i7 Extreme and Xeon E5) have two SMBUS
controllers per package, addressing up to 16 DIMM slots per package.
This is a driver for those SMBUS channels.
The first patch is a minor change to the i2c core to make it work
better with extremely limited hardware like this.
The Intel iMC SMBUS controller can't READ_BYTE. (This seems odd to me
-- it supports WRITE_BYTE.) SPD EEPROMs are safe to probe with
READ_BYTE_DATA, so fall back to that.
While I'm in here, also show the address that had no probing method for
easier debugging.
Signed-off-by: Andy Lutomirski
Sandy Bridge Xeon and Extreme chips have integrated memory controllers
with (rather limited) onboard SMBUS masters. This driver gives access
to the bus.
Signed-off-by: Andy Lutomirski l...@amacapital.net
---
drivers/i2c/busses/Kconfig | 14 ++
drivers/i2c/busses/Makefile | 1 +
I'm rather confused here. In SMBUS, the read word operation returns
two bytes. Just to be confusing, the SMBUS spec calls the first byte
Data Byte Low and the second byte Data Byte High. But they really
are the first and second bytes -- Read Word will return whatever Read
Byte would have as its
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