Hi,
compiling this driver gives me:
drivers/i2c/busses/i2c-sun6i-p2wi.c: In function 'p2wi_probe':
drivers/i2c/busses/i2c-sun6i-p2wi.c:272:2: error: implicit declaration of
function 'devm_reset_control_get' [-Werror=implicit-function-declaration]
drivers/i2c/busses/i2c-sun6i-p2wi.c:272:13: warni
Hi,
On Sat, Jun 07, 2014 at 07:36:19PM +0200, Max Schwarz wrote:
> Driver for the native I2C adapter found in Rockchip RK3xxx SoCs.
>
> Configuration is only possible through devicetree. The driver is
> interrupt driven and supports the I2C_M_IGNORE_NAK mangling bit.
>
> Signed-off-by: Max Schwa
On 06/10/2014 02:24 AM, Mika Westerberg wrote:
On Thu, Apr 10, 2014 at 09:15:16PM -0700, Srinivas Pandruvada wrote:
ACPI specification allows multiple i2c addresses defined under one
ACPI device object. These addresses are defined using _CRS method.
The current implementation will pickup the las
On Tuesday 10 June 2014 16:36:04 Maxime Ripard wrote:
> On Tue, Jun 10, 2014 at 03:54:56PM +0200, Arnd Bergmann wrote:
> > On Tuesday 10 June 2014 15:47:16 Boris BREZILLON wrote:
> > >
> > > +config I2C_SUN6I_P2WI
> > > + tristate "Allwinner sun6i internal P2WI controller"
> > > + depe
Hi Arnd,
On Tue, Jun 10, 2014 at 03:54:56PM +0200, Arnd Bergmann wrote:
> On Tuesday 10 June 2014 15:47:16 Boris BREZILLON wrote:
> >
> > +config I2C_SUN6I_P2WI
> > + tristate "Allwinner sun6i internal P2WI controller"
> > + depends on ARCH_SUNXI
> > + help
> > + If you
On Tuesday 10 June 2014 15:47:16 Boris BREZILLON wrote:
>
> +config I2C_SUN6I_P2WI
> + tristate "Allwinner sun6i internal P2WI controller"
> + depends on ARCH_SUNXI
> + help
> + If you say yes to this option, support will be included for the
> + P2WI (Push/Pull 2
Hello Paul,
On 10/06/2014 10:56, Paul Carpenter wrote:
> Wolfram Sang wrote:
>> On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
>>> The P2WI looks like an SMBus controller which only supports byte data
>>> transfers. But, it differs from standard SMBus protocol on several
>>> aspe
P2WI (Push/Pull 2 Wire Interface) is an SMBus like bus used to communicate
with some PMICs (like the AXP221).
Document P2WI DT bindings which are pretty much the same as the one defined
for the marvell's mv64xxx controller.
Signed-off-by: Boris BREZILLON
---
.../devicetree/bindings/i2c/i2c-sunx
The P2WI controller looks like an SMBus controller which only supports byte
data transfers. But, it differs from standard SMBus protocol on several
aspects:
- it supports only one slave device, and thus drop the address field
- it adds a parity bit every 8bits of data
- only one read access is requ
Hello,
This series adds support for the P2WI block used by some Allwinner boards
to interface with the AXP221 PMIC.
Best Regards,
Boris
Changes since v4:
- add P2WI protocol description in driver header comment
- remove unneeded i2c address check
- remove unneeded irq field from p2wi struct
Ch
Hi Pankaj,
On 10.05.2014 09:20, Pankaj Dubey wrote:
> Let's handle i2c interrupt re-configuration in i2c driver. This will
> help us in removing some soc specific checks from machine files.
> Since only Exynos5250, and Exynos5420 need to do this, added syscon
> based phandle to i2c device nodes of
Wolfram Sang wrote:
On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
The P2WI looks like an SMBus controller which only supports byte data
transfers. But, it differs from standard SMBus protocol on several
aspects:
- it supports only one slave device, and thus drop the address fi
On Thu, Apr 10, 2014 at 09:15:16PM -0700, Srinivas Pandruvada wrote:
> ACPI specification allows multiple i2c addresses defined under one
> ACPI device object. These addresses are defined using _CRS method.
> The current implementation will pickup the last entry in _CRS, and
> create an i2C device,
On 10/06/2014 10:54, Boris BREZILLON wrote:
> Hello Wolfram,
>
> On 10/06/2014 10:38, Wolfram Sang wrote:
>> On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
>>> The P2WI looks like an SMBus controller which only supports byte data
>>> transfers. But, it differs from standard SMBus
Hello Wolfram,
On 10/06/2014 10:38, Wolfram Sang wrote:
> On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
>> The P2WI looks like an SMBus controller which only supports byte data
>> transfers. But, it differs from standard SMBus protocol on several
>> aspects:
>> - it supports onl
On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
> The P2WI looks like an SMBus controller which only supports byte data
> transfers. But, it differs from standard SMBus protocol on several
> aspects:
> - it supports only one slave device, and thus drop the address field
> - it adds
> > > + /* Synchronization & notification */
> > > + spinlock_t lock;
> >
> > Why the lock? The core has per-adapter locks anyhow.
>
> I'm using it to lock the rk3x_i2c struct during interrupts. It's needed there
> because an operation can timeout, which means the interrupt can occur at any
>
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