On Saturday, September 20, 2014 02:23:19 PM Wolfram Sang wrote:
>
> --bAmEntskrkuBymla
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> On Fri, Sep 19, 2014 at 08:27:39PM +0200, Ulf Hansson wrote:
> > Previously only the
On 09/20/2014 06:49 PM, Wolfram Sang wrote:
On Fri, Sep 05, 2014 at 04:02:19PM +0200, Jean-Michel Hautbois wrote:
Some I2C devices have multiple addresses assigned, for example each address
corresponding to a different internal register map page of the device.
So far drivers which need support f
On Fri, Sep 05, 2014 at 04:02:19PM +0200, Jean-Michel Hautbois wrote:
> Some I2C devices have multiple addresses assigned, for example each address
> corresponding to a different internal register map page of the device.
> So far drivers which need support for this have handled this with a driver
>
On Saturday, September 20, 2014 at 02:49:36 PM, Wolfram Sang wrote:
> On Tue, Sep 09, 2014 at 06:19:31PM +0200, Janusz Uzycki wrote:
> > i2cdetect scanned i2c bus very slow if address was not occupied by any
> > device.
> >
> > Signed-off-by: Janusz Uzycki
>
> I would apply this patch and produc
On Saturday, September 20, 2014 at 02:39:53 PM, Wolfram Sang wrote:
> On Tue, Sep 09, 2014 at 06:19:30PM +0200, Janusz Uzycki wrote:
> > If I2C_M_RD flag is set SELECT command is sent
> > and afterward READ command.
> > The patch fixes READ command to return READ failure error message
> > instead o
On Tue, Sep 16, 2014 at 05:21:04PM +0800, Fan Du wrote:
> In block write mode, when encapsulating dma_buffer, first element is
> 'command', the rest is data buffer, so only copy actual data buffer
> starting from block[1] with the size indicating by block[0].
>
> Signed-off-by: Fan Du
Applied to
On Tue, Sep 16, 2014 at 05:21:03PM +0800, Fan Du wrote:
> Software is allowed to allocate number of descriptor size from 2 to 256,
> this i2c controller could process more descriptor, but for i2c core soft
> ware layer, only one i2c transaction is allowed each time.
>
> So here switch to minimum 2
On Tue, Sep 09, 2014 at 06:19:31PM +0200, Janusz Uzycki wrote:
> i2cdetect scanned i2c bus very slow if address was not occupied by any device.
>
> Signed-off-by: Janusz Uzycki
I would apply this patch and produce a fitting commit message out of the
text you already sent, so you get an idea what
On Tue, Sep 09, 2014 at 06:19:30PM +0200, Janusz Uzycki wrote:
> If I2C_M_RD flag is set SELECT command is sent
> and afterward READ command.
> The patch fixes READ command to return READ failure error message
> instead of SELECT failure error message.
>
> Signed-off-by: Janusz Uzycki
Applied to
On Wed, Sep 03, 2014 at 01:52:07PM +0800, Haibo Chen wrote:
> According to the i.mx spec, for multimaster mode, if I2C is
> enabled when the bus is busy and asserts start, hardware inhibits
> the transmission, clears MSTA without signaling a stop, generate
> an interrupt, and set I2C_I2SR[IAL] to i
On Fri, Sep 19, 2014 at 08:27:39PM +0200, Ulf Hansson wrote:
> Previously only the ACPI PM domain was supported by the i2c bus.
>
> Let's convert to the common attach/detach functions for PM domains,
> which currently means we are extending the support to include the
> generic PM domain as well.
>
On Mon, Sep 08, 2014 at 11:38:25AM +0800, Addy Ke wrote:
> I2C_CLKDIV register descripted in the previous version of
> RK3x chip manual is incorrect. Plus 1 is required.
>
> The correct formula:
> - T(SCL_HIGH) = T(PCLK) * (CLKDIVH + 1) * 8
> - T(SCL_LOW) = T(PCLK) * (CLKDIVL + 1) * 8
> - (SCL Div
On Fri, Aug 22, 2014 at 10:43:44AM -0700, Doug Anderson wrote:
> Having a transfer more than 32 bits is not all that unlikely. Remove
> the annotation.
>
> The unlikely in the IRQ handler can't gain us much. It's not in a
> loop, so at most it would save 1 instruction per IRQ, which isn't
> much
Hi,
thanks for the submission.
On Mon, Aug 25, 2014 at 01:51:22PM +0200, Anders Berg wrote:
> Add I2C bus driver for the controller found in the LSI Axxia family SoCs. The
> driver implements 10-bit addressing and SMBus transfer modes via emulation
> (including SMBus block data read).
>
> Signed
From: Wolfram Sang
gcc rightfully says:
drivers/i2c/busses/i2c-rcar.c:198:10: warning: comparison between signed and
unsigned integer expressions [-Wsign-compare]
Signed-off-by: Wolfram Sang
---
drivers/i2c/busses/i2c-rcar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
On Mon, Sep 15, 2014 at 12:20:19AM +0400, Sergei Shtylyov wrote:
> Check if the ICMSR register (masked with the ICMIER register) evaluates to 0
> in
> the driver's interrupt handler and return IRQ_NONE in that case, like many
> other
> drivers do.
>
> Signed-off-by: Sergei Shtylyov
>
Applied
On Sat, Sep 06, 2014 at 03:34:32AM +0400, Sergei Shtylyov wrote:
> Bits 8-31 of all registers reflect the value of bits 0-7 on reads and should
> be
> 0 on writes, according to the manuals. RCAR_IRQ_ACK_{RECV|SEND} macros have
> all
> 1's in bits 8-31, thus going against the manuals, so fix them.
On Mon, Sep 15, 2014 at 12:17:34AM +0400, Sergei Shtylyov wrote:
> rcar_i2c_irq_recv() always returns 0, so we can make this function return
> *void* and also remove rcar_i2c_flags_set() invocation in rcar_i2c_irq().
>
> Signed-off-by: Sergei Shtylyov
I prefer to skip this patch to have more sim
On Mon, Sep 15, 2014 at 12:15:46AM +0400, Sergei Shtylyov wrote:
> rcar_i2c_prepare_msg() always returns 0, so we can make this function return
> *void* and thus remove the result check in rcar_i2c_master_xfer().
>
> Signed-off-by: Sergei Shtylyov
>
Applied to for-next, thanks!
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On Mon, Sep 15, 2014 at 12:14:14AM +0400, Sergei Shtylyov wrote:
> rcar_i2c_master_xfer() needlessly compares the message pointers (using
> indirect
> addressing) in order to detect the last I2C message, while it's enough to only
> compare the message indexes.
>
> Signed-off-by: Sergei Shtylyov
On Thu, Sep 18, 2014 at 12:26:07PM +0300, Mika Westerberg wrote:
> From: Carl Peng
>
> Add support for AMD version of the DW I2C host controller. The device is
> enumerated from ACPI namespace with ACPI ID AMD0010. Because the core
> driver needs an input source clock, and this is not an Intel LP
On Thu, Sep 18, 2014 at 12:26:06PM +0300, Mika Westerberg wrote:
> In order to be able to create missing clock for AMD (and in future possibly
> others) we move getting clock for the device a bit later. Also make ACPI/DT
> configuration in the same place depending on from where the device was
> enu
On Wed, Sep 03, 2014 at 10:41:38AM +0800, Raymond Tan wrote:
> From: "Tan, Raymond"
>
> Use the platform data to set the clk_freq when there is no DT configuration
> available. The clk_freq in turn will determine the I2C speed mode.
>
> In Quark, there is currently no other configuration mechani
On Wed, Aug 20, 2014 at 04:29:08PM +0200, Romain Baeriswyl wrote:
> From: Romain Baeriswyl
>
> Some legacy devices support ony I2C standard mode at 100kHz.
> This patch allows to select the standard mode through the DTS
> with the use of the existing clock-frequency parameter.
>
> When clock-fre
On Fri, Sep 05, 2014 at 12:28:18PM +0300, Mikko Perttunen wrote:
> From: Mikko Perttunen
>
> Currently the i2c-tegra bus driver prepares, enables
> and set_rates its clocks separately for each transfer.
> This causes locking problems when doing I2C transfers
> from clock notifiers; see
> http://l
On Wed, Aug 13, 2014 at 01:56:51PM +0200, Michal Simek wrote:
> There is no need to init .owner field.
>
> Based on the patch from Peter Griffin
> "mmc: remove .owner field for drivers using module_platform_driver"
>
> This patch removes the superflous .owner field for drivers which
It says dri
On Fri, Sep 19, 2014 at 11:53:28AM +0300, Mika Westerberg wrote:
> On Fri, Sep 19, 2014 at 04:28:02PM +0800, Lan Tianyu wrote:
> > How about including i2c-acpi.c in the i2c-core.c directly if ACPI is
> > selected?
>
> I would rather see it merged there.
+1
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