On Mon, Nov 9, 2015 at 1:43 PM, Liguo Zhang wrote:
> For platform with auto restart support, when doing i2c multi transfer
> in high speed, for example, doing write-then-read transfer, the master
> code will occupy the first transfer, and the second transfer will be
> the read transfer, the write
On Mon, Nov 9, 2015 at 10:25 PM, Andy Shevchenko
wrote:
> On Mon, Nov 9, 2015 at 7:43 AM, Liguo Zhang wrote:
>> For platform with auto restart support, between every transfer,
>> i2c controller will trigger an interrupt and SW need to handle
>> it to start new transfer. When doing write-then-read
Hi Wolfram,
On Tue, Aug 11, 2015 at 10:55 PM, Wolfram Sang wrote:
> On Thu, Aug 06, 2015 at 03:22:11PM +0800, Eddie Huang wrote:
>> When occur i2c ack error, i2c controller generate two interrupts,
>> first is the ack error interrupt, then the complete interrupt.
>> i2c interrupt handler should k
the complete interrupt.
>
> Signed-off-by: Liguo Zhang
> Signed-off-by: Eddie Huang
Reviewed-by: Daniel Kurtz
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/dri
On Thu, Aug 6, 2015 at 3:22 PM, Eddie Huang wrote:
> Reset DMA in hardware init function to avoid unknown hardware state
> before do any I2C operation.
>
> Signed-off-by: Liguo Zhang
> Signed-off-by: Eddie Huang
Reviewed-by: Daniel Kurtz
> ---
> drivers/i2c/busse
On Thu, May 21, 2015 at 4:53 PM, Eddie Huang wrote:
> This series is for Mediatek SoCs I2C controller common bus driver.
>
> Earlier MTK SoC (for example, MT6589, MT8135) I2C HW has some limitations.
> New generation SoC like MT8173 fix following limitations:
>
> 1. Only support one i2c_msg number
Hi guys,
On Fri, Apr 24, 2015 at 6:08 PM, Jean Delvare wrote:
> Hi Ellen,
>
> On Mon, 20 Apr 2015 15:52:47 -0700, Ellen Wang wrote:
>> This leads to a related question: If the driver is serialized, then the
>> (status = priv->status) inside wait_event_timeout() isn't strictly
>> necessary, corre
On Fri, May 17, 2013 at 4:36 PM, Jean Delvare wrote:
> Hi Robert,
>
> On Thu, 16 May 2013 13:44:55 +1000, Robert Norris wrote:
>> On Wed, May 15, 2013 at 09:49:23PM +0200, Jean Delvare wrote:
>> > > Interrupt: pin B routed to IRQ 0
>> >
>> > Hmm, this "IRQ 0" is quite odd. I'm wondering if thi
Signed-off-by: Jean Delvare
> Cc: Daniel Kurtz
> ---
> I was able to test on Patsburg IDF channels and although I couldn't
> test all transaction types, interrupts seem to work the same as on the
> main SMBus channel so let's enable interrupts there too.
I can confirm th
ty of I2C transfers on
>> the SoCs where the busy wait is effective.
>>
>> Signed-off-by: Mark Brown
>
> Acked-by: Olof Johansson
Reviewed-by: Daniel Kurtz
>
> -Olof
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On Tue, Nov 20, 2012 at 1:57 PM, Mark Brown
wrote:
> The changes in "i2c-s3c2410: use exponential back off while polling for
> bus idle" remove the initial busy wait for I2C transfers to complete and
> replace it with usleep_range() calls which will schedule.
>
> Since for older SoCs I2C transfers
Hi Mark,
On Tue, Nov 20, 2012 at 12:49 PM, Mark Brown
wrote:
>
> On Thu, Nov 15, 2012 at 05:43:32PM +0530, Naveen Krishna Chatradhi wrote:
>
> > + iicstat = readl(i2c->regs + S3C2410_IICSTAT);
> > + delay = 1;
> > + while ((iicstat & S3C2410_IICSTAT_START) &&
> > +ktime_us
On Thu, Jul 5, 2012 at 4:10 PM, Jean Delvare wrote:
> Hi Daniel,
>
> On Thu, 5 Jul 2012 12:31:11 +0800, Daniel Kurtz wrote:
>> On Thu, Jul 5, 2012 at 4:16 AM, Jean Delvare wrote:
>> > You should be able to reproduce this bug by loading i2c-i801 with
>> > option
Hi Jean,
On Thu, Jul 5, 2012 at 4:16 AM, Jean Delvare wrote:
> Hi again Daniel,
>
> On Wed, 27 Jun 2012 21:54:14 +0800, Daniel Kurtz wrote:
>> Add a new 'feature' to i2c-i801 to enable using i801 interrupts.
>> When the feature is enabled, then an isr is instal
On Wed, Jul 4, 2012 at 3:49 PM, Jean Delvare wrote:
> Hi Daniel,
>
> Thanks again for the continued feedback.
>
> On Wed, 4 Jul 2012 14:12:26 +0800, Daniel Kurtz wrote:
>> On Tue, Jul 3, 2012 at 9:39 PM, Jean Delvare wrote:
>> > On Tue, 3 Jul 2012 17:50:13 +0800,
On Tue, Jul 3, 2012 at 9:39 PM, Jean Delvare wrote:
>
> Hi Daniel,
>
> Thanks for the feedback.
>
> On Tue, 3 Jul 2012 17:50:13 +0800, Daniel Kurtz wrote:
> > On Tue, Jul 3, 2012 at 4:19 PM, Jean Delvare wrote:
> > >
> > > Come up with a consistent, d
both BUSY being cleared and INTR or any error flag being set.
> This avoids having to wait twice for the same event.
>
> Signed-off-by: Jean Delvare
> Cc: Daniel Kurtz
> ---
> Daniel, this is what I had in mind. This applies on top of your first 6
> patches (i.e. all the
On Mon, Jul 2, 2012 at 5:20 AM, Jean Delvare wrote:
> Hi again Daniel,
>
> On Wed, 27 Jun 2012 18:07:24 +0200, Jean Delvare wrote:
>> On Wed, 27 Jun 2012 21:54:10 +0800, Daniel Kurtz wrote:
>> > Per ICH10 datasheet [1] pg. 711, after completing a block transaction,
>
of which this is the only instance.
Signed-off-by: Daniel Kurtz
Reported-by: Jean Delvare
---
drivers/i2c/busses/i2c-i801.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index ae2945a..7443990 100644
--- a/dr
On Thu, Jun 28, 2012 at 12:07 AM, Jean Delvare wrote:
> On Wed, 27 Jun 2012 21:54:10 +0800, Daniel Kurtz wrote:
>> Per ICH10 datasheet [1] pg. 711, after completing a block transaction,
>> INTR should be checked & cleared separately, only after BYTE_DONE is
>> first clear
On Thu, Jun 28, 2012 at 12:51 AM, Jean Delvare wrote:
> On Wed, 27 Jun 2012 21:54:11 +0800, Daniel Kurtz wrote:
>> If an error is detected in the polling loop, abort the transaction and
>> return an error code.
>>
>> * DEV_ERR is set if the device does not respond with
Hi Jean
On Wed, Jun 27, 2012 at 5:24 PM, Jean Delvare wrote:
> Hi again Daniel,
>
> On Fri, 6 Jan 2012 18:58:19 +0800, Daniel Kurtz wrote:
>> This is a second version of a set of patches enables the Intel PCH SMBus
>> controller interrupt. It refactors the second two pa
the SMBus controller tries to generate a START condition, but
detects that the SMBDATA is being held low, usually by another SMBus/I2C
master.
* FAILED is only set if a the transaction is set by software (using the
SMBHSTCNT KILL bit).
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c-i801
appreciated.
Daniel Kurtz (8):
i2c: i801: refactor use of LAST_BYTE
i801_block_transaction_byte_by_byte
i2c: i801: optimize waiting for HWPEC to finish
i2c: i801: check INTR after every transaction
i2c: i801: check and return errors during byte-by-byte transfers
i2c: i801: rename some
Later patches enable interrupts. This preliminary patch removes the older
unsupported ENABLE_INT9 flag.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c-i801.c |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c
is patch checks and clears INTR at the very end of every successful
transaction, regardless of whether the PEC is used.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c-i801.c | 46
1 files changed, 23 insertions(+), 23 deletions(-)
diff --git a
might be occurring.
The end result is faster I2C block read and write transactions.
Note: This patch has only been tested and verified by doing I2C read and
write block transfers on Cougar Point 6 Series PCH.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c-i801.c | 78
As a slight optimization, pull some logic out of the polling loop during
byte-by-byte transactions by just setting the I801_LAST_BYTE bit, as
defined in the i801 (PCH) datasheet, when reading the last byte of a
byte-by-byte I2C_SMBUS_READ.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c
pt feature has only been enabled for COUGARPOINT hardware.
In addition, it is disabled if SMBus is using the SMI# interrupt.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c-i801.c | 93 ++---
1 files changed, 87 insertions(+), 6 deletions(-)
diff --git
When a transaction has finished (including the PEC), the SMBus controller
sets the INTR bit.
Slightly optimize the polling loop by reading status before the first
sleep.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c-i801.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions
Rename the SMBHSTCNT register bit access constants to match the style of
other register bits.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c-i801.c | 21 +++--
1 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c
On Wed, Jun 20, 2012 at 4:58 PM, Jean Delvare wrote:
> On Tue, 19 Jun 2012 20:47:04 +0200, Jean Delvare wrote:
>> On Fri, 6 Jan 2012 18:58:21 +0800, Daniel Kurtz wrote:
>> > @@ -879,8 +953,24 @@ static int __devinit i801_probe(struct pci_dev *dev,
>> > i801
Jean? Anyone? ping?
On Mon, Feb 20, 2012 at 7:23 PM, Daniel Kurtz wrote:
> On Fri, Jan 6, 2012 at 7:35 PM, Jean Delvare wrote:
>> Hi Daniel,
>>
>> On Fri, 6 Jan 2012 18:58:19 +0800, Daniel Kurtz wrote:
>>> This is a second version of a set of patches enables the
On Fri, Jan 6, 2012 at 7:35 PM, Jean Delvare wrote:
> Hi Daniel,
>
> On Fri, 6 Jan 2012 18:58:19 +0800, Daniel Kurtz wrote:
>> This is a second version of a set of patches enables the Intel PCH SMBus
>> controller interrupt. It refactors the second two patches a little
loop, abort the transaction and return
-ENXIO to the caller. DEV_ERR is set if the device does not respond with
an acknowledge, and the SMBus controller times out (minimum 25ms).
[1]
http://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf
Signed-off-by: Daniel
ons for a single
adapter are always serialized.
For this patch, the INTREN bit is set only for smbus block, byte and word
transactions, but not for emulated i2c reads or writes. The use of the
DS (BYTE_DONE) interrupt with byte-by-byte i2c transactions is
implemented in a subsequent patch.
Sig
might be occurring.
The end result is a dramatic speed up in emulated i2c-over smbus block
read and write transactions.
Note: This patch has only been tested and verified by doing i2c read and
write block transfers on Cougar Point 6 Series PCH.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c
led on the Cougar Point,
and even here, it can be completely disabled with the "Interrupt" feature like
other advanced features of the driver.
Daniel Kurtz (3):
i2c: i801: refactor i801_block_transaction_byte_by_byte
i2c: i801: enable irq for i801 smbus transactions
i2c: i801: enable
might be occurring.
The end result is a dramatic speed up in emulated i2c-over smbus block
read and write transactions.
Note: This patch has only been tested and verified by doing i2c read and
write block transfers on Cougar Point 6 Series PCH.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2c
or is only enabled on the Cougar Point,
and even here, it can be completely disabled with the "Interrupt" feature like
other advanced features of the driver.
Daniel Kurtz (3):
i2c: i801: refactor i801_block_transaction_byte_by_byte
i2c: i801: enable irq for i801 smbus transactions
i2c:
loop, abort the transaction and return
-ENXIO to the caller. DEV_ERR is set if the device does not respond with
an acknowledge, and the SMBus controller times out (minimum 25ms).
[1]
http://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf
Signed-off-by: Daniel
the INTREN bit is set only for smbus block, byte and word
transactions, but not for emulated i2c reads or writes.
The use of the DS (BYTE_DONE) interrupt with byte-by-byte i2c
transactions is implemented in a subsequent patch.
Signed-off-by: Daniel Kurtz
---
drivers/i2c/busses/i2
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