On 05/29/2013 08:22 PM, Kevin Hilman wrote:
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
Starting from the OMAP chips with version2 registers scheme there are
2 registers (I2C_IRQENABLE_SET and I2C_IRQENABLE_CLR) to manage
interrupts instead of the older OMAP chips with old scheme
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
On 05/29/2013 08:22 PM, Kevin Hilman wrote:
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
Starting from the OMAP chips with version2 registers scheme there are
2 registers (I2C_IRQENABLE_SET and I2C_IRQENABLE_CLR) to manage
On 05/30/2013 05:18 PM, Kevin Hilman wrote:
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
On 05/29/2013 08:22 PM, Kevin Hilman wrote:
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
Starting from the OMAP chips with version2 registers scheme there are
2 registers
Starting from the OMAP chips with version2 registers scheme there
are 2 registers (I2C_IRQENABLE_SET and I2C_IRQENABLE_CLR) to manage
interrupts instead of the older OMAP chips with old scheme which have
only one register (I2C_IE). Now we should use I2C_IRQENABLE_SET
register for enabling
Oleksandr Dmytryshyn oleksandr.dmytrys...@ti.com writes:
Starting from the OMAP chips with version2 registers scheme there are
2 registers (I2C_IRQENABLE_SET and I2C_IRQENABLE_CLR) to manage
interrupts instead of the older OMAP chips with old scheme which have
only one register (I2C_IE). Now
