On Wed, Jun 17, 2015 at 03:18:42PM +0200, Wolfram Sang wrote:
>
> > > Having said that, I am still not convinced that the driver should be in
> > > the kernel
> > > to start with. Browsing through Intel's datasheets, the registers are
> > > supported
> > > in E5-2600 v1, v2, and v3. However, in
> > Having said that, I am still not convinced that the driver should be in the
> > kernel
> > to start with. Browsing through Intel's datasheets, the registers are
> > supported
> > in E5-2600 v1, v2, and v3. However, in v3 Intel added a note saying that
> > the registers
> > should not be acc
On Mar 13, 2015 9:15 PM, "Guenter Roeck" wrote:
>
> On 03/09/2015 01:55 PM, Andy Lutomirski wrote:
>>
>> Sandy Bridge Xeon and Extreme chips have integrated memory
>> controllers with (rather limited) onboard SMBUS masters. This
>> driver gives access to the bus.
>>
>> There are various groups wo
On 03/09/2015 01:55 PM, Andy Lutomirski wrote:
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the bus.
There are various groups working on standardizing a way to arbitrate
access to the bus between
Sandy Bridge Xeon and Extreme chips have integrated memory
controllers with (rather limited) onboard SMBUS masters. This
driver gives access to the bus.
There are various groups working on standardizing a way to arbitrate
access to the bus between the OS, SMM firmware, a BMC, hardware
thermal con
