Hi Tony,
Luck, Tony wrote:
> Getting close now. New (I think it's new, I didn't notice it last time, but
> I may have
> missed it in the other build noise) concern while compiling this version was
> the warning:
>
> arch/ia64/kernel/iosapic.c:597: warning: 'iosapic_free_rte' defined but not
On Tue, 2007-07-17 at 18:31 -0400, Bob Picco wrote:
> Hi:
> Thanks for the review.
> Hidetoshi Seto wrote: [Tue Jul 17 2007, 06:55:47AM EDT]
> > Bob Picco wrote:
> > >@@ -214,61 +209,56 @@ ENTRY(fsys_gettimeofday)
> > :
> > > movl r27 = xtime
> > :
> > > .time_redo:
> > >- .pred.rel.mutex p8,p
Hi:
Thanks for the review.
Hidetoshi Seto wrote: [Tue Jul 17 2007, 06:55:47AM EDT]
> Bob Picco wrote:
> >@@ -214,61 +209,56 @@ ENTRY(fsys_gettimeofday)
> :
> > movl r27 = xtime
> :
> > .time_redo:
> >-.pred.rel.mutex p8,p9,p10
> >-ld4.acq r28 = [r29] // xtime_lock.sequence. Must
Yasuaki Ishimatsu <[EMAIL PROTECTED]> writes:
> - define NR_IRQS as follow:
>
> Vector domain can provide the number of irqs being proportional to the
> number of CPUs theoretically. However, the relation between them is
> actually not linear, especially in large system. To avoid the memory
Getting close now. New (I think it's new, I didn't notice it last time, but I
may have
missed it in the other build noise) concern while compiling this version was
the warning:
arch/ia64/kernel/iosapic.c:597: warning: 'iosapic_free_rte' defined but not
used
This isn't spurious, the only ca
Hi Linus,
please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git release
This will update the files shown below.
Thanks!
-Tony
arch/ia64/hp/common/sba_iommu.c | 20 ++--
arch/ia64/hp/sim/boot/fw-emu.c |5 -
arch/ia64/hp/s
Add support for IRQ migration across vector domain.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/iosapic.c | 20 +---
arch/ia64/kernel/irq_ia64.c | 42 +++---
arch
Add fundamental support for multiple vector domain. There still exists
only one vector domain even with this patch. IRQ migration across
domain is not supported yet by this patch.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/ke
Add per-CPU vector domain support for IA64_DIG. It is enabled by
adding the "vector=percpu" boot option.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/irq_ia64.c |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Add per-CPU vector domain support for IA64_GENERIC. It is enabled by
adding the "vector=percpu" boot option.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
Documentation/kernel-parameters.txt |3 +++
arch/ia64/kernel/irq_ia64.c
Add mapping tables between irqs and vectors, and its management code.
This is necessary for supporting multiple vector domain because 1:1
mapping between irq and vector will be changed to n:1.
The irq == vector relationship between irqs and vectors is explicitly
remained for percpu interrupts, pla
Need to check if irq is sharable amoung handlers when searching
sharable IOSAPIC irq.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/iosapic.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
Index: linux-2.
Use create_irq()/destroy_irq() for iosapic interrupts.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/iosapic.c | 39 +++
1 files changed, 15 insertions(+), 24 deletions(-)
Index: lin
Many of IOSAPIC codes depends on the flollowing assumptions, but these
would become invalid when multiple vector domain will be supported in
the future.
- 1:1 mapping between IRQ and vector
- IRQ == vector
To fix those invalid assumptions, this patch changes iosapic_intr_info[]
to be indexed
Use per-iosapic lock for indirect iosapic register access. It reduces
lock contention.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/iosapic.c | 57 ++---
include/asm-ia64/iosapic
Hi,
Here is a series of patches for ia64 vector domain. By these patches, we can
use more than NR_VECTORS(256) irqs. This is based on existing x86-64 vector
domain code. I tested it on my ia64 box.
Changes from previous patchset:
- rebase to 2.6.22
- remove unnecessary whitespaces
- do the bui
Cleanup order of irq_desc.lock and iosapic_lock in
iosapic_register_intr() and iosapic_unregister_intr().
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/iosapic.c | 50 ++---
1 fil
Remove duplicated members in iosapic_rte_info in iosapic.c. This patch
has no functional changes.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/iosapic.c | 60 ++---
1 files chang
Remove unnecessary indent between spin_lock() and spin_unlock() in
iosapic.c. This has no functional changes.
Signed-off-by: Kenji Kaneshige <[EMAIL PROTECTED]>
Signed-off-by: Yasuaki Ishimatsu <[EMAIL PROTECTED]>
arch/ia64/kernel/iosapic.c | 303 -
1
Bob Picco wrote:
@@ -214,61 +209,56 @@ ENTRY(fsys_gettimeofday)
:
movl r27 = xtime
:
.time_redo:
- .pred.rel.mutex p8,p9,p10
- ld4.acq r28 = [r29] // xtime_lock.sequence. Must come first for
locking purposes
+ ld4.acq r28 = [r20] // gtod_lock.sequence, Mu
20 matches
Mail list logo
