Hi,
I'm ignorant when it comes to IO access, so I hope this isn't rubbish (if
it is, I would appreciate being corrected).
It took me more than a glance to see what the difference is supposed to be
between wmb() and mmiowb(). I think especially because mmiowb isn't really
like a write barrier.
wm
This is updated version.
Andrew, could you repleace ?
-Kame
==
Fixing 2 small issues pointed by Tony Luck.
Changelog v1 -> v2
* add pte_present_exec_user()
* remove pte_user
* fixed comments.
v1.
* removing redundant BUG_ON in __ia64_sync_icache_dcache().
* check pte_present() first.
Signed-o
On Tue, 2007-08-21 at 17:34 -0700, [EMAIL PROTECTED] wrote:
> On Tue, Aug 21, 2007 at 03:55:29PM -0500, James Bottomley wrote:
>
> > .
> > Almost every platform supports posted DMA ... its a property of most PCI
> > bridge chips.
> >
>
> The term "posted DMA" is used to describe this behavio
On Tue, Aug 21, 2007 at 03:55:29PM -0500, James Bottomley wrote:
> .
> Almost every platform supports posted DMA ... its a property of most PCI
> bridge chips.
>
The term "posted DMA" is used to describe this behavior in the Altix
Device Driver Writer's Guide, but it may be confusing things
On Tue, 21 Aug 2007 14:12:02 -0700
"Luck, Tony" <[EMAIL PROTECTED]> wrote:
> > + if (pte_present(pteval) &&// swap out ?
> > + pte_exec(pteval) &&// flush only new executable page.
> > pte_user(pteval) &&// ignore kernel page
> > (!pte_present(*ptep) ||// do_no_page
[patch] Fix Altix BTE error return status
The Altix shub2 BTE error detail bits are in a different location
than on shub1. The current code does not take this into account
resulting in all shub2 BTE failures mapping to "unknown".
This patch reads the error detail bits from the proper location,
s
On Tue, Aug 21, 2007 at 02:16:32PM -0600, Matthew Wilcox wrote:
>
> So, let me try to understand ... your hardware allows writes from the
> device to pass other writes from the device? Doesn't that violate the
> PCI spec? I'm thinking about this (page 43 of PCI 2.3):
>
I should have stated
> + if (pte_present(pteval) &&// swap out ?
> + pte_exec(pteval) &&// flush only new executable page.
> pte_user(pteval) &&// ignore kernel page
> (!pte_present(*ptep) ||// do_no_page or swap in, migration,
> pte_pfn(*ptep) != pte_pfn(pteval)))
On Tue, 2007-08-21 at 13:05 -0700, Randy Dunlap wrote:
> > diff --git a/Documentation/DMA-API.txt b/Documentation/DMA-API.txt
> > index cc7a8c3..e117b72 100644
> > --- a/Documentation/DMA-API.txt
> > +++ b/Documentation/DMA-API.txt
> > @@ -392,6 +392,28 @@ Notes: You must do this:
> >
> > See a
On Tue, Aug 21, 2007 at 12:35:22PM -0700, [EMAIL PROTECTED] wrote:
> +int
> +dma_flags_set_dmaflush(int dir)
> +
> +Amend dir (one of the enum dma_data_direction values), with a platform-
> +specific "dmaflush" attribute. Unless the platform supports "posted DMA"
> +this is a no-op.
> +
> +On pla
On Tue, 21 Aug 2007 12:35:22 -0700 [EMAIL PROTECTED] wrote:
>
> > I'm a little concerned about changing the API for the dma_ foo
> > functions, which are defined cross platform. If you want to change
> > that, I think it will require updating the documentation explaining
> > it.
>
> What do
> I'm a little concerned about changing the API for the dma_ foo
> functions, which are defined cross platform. If you want to change
> that, I think it will require updating the documentation explaining
> it.
What do you think of the following? (And is there anyone else
I should be cc-ing f
Fixing 2 small issues pointed by Tony Luck.
* removing redundant BUG_ON in __ia64_sync_icache_dcache().
* check pte_present() first.
Signed-off-by: KAMEZAWA Hiroyuki <[EMAIL PROTECTED]>
---
arch/ia64/mm/init.c|2 --
include/asm-ia64/pgtable.h |4 ++--
2 files changed, 2 insertio
Hello All,
I have found the source of the problem for the tree not showing
up at http://git.kernel.org. The tree top dir needs to have the
.git suffix. I fixed that now and you can now browse the code online.
I am sorry about the inconvenience but I was not aware of the
restriction.
Anyway, to g
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