Hi Jeff:
Do you have any suggestion on my plan to withdraw Tejun's forcing 32 bit
DMA patch?
As well as further validation to the 64 bit DMA capacity of SB600 SATA
controller?
Thanks
Best Regards
Shane
> -Original Message-
> From: Shane Huang
> Sent: Wednesday, January 23, 2008 3:44 PM
Thomas Evans wrote:
> Um, I can, but it's not all that different than the others - is there
> something I am missing that would collect more info in the logs?
Well, at times, small differences can tell us more information. The
best we can do here is to gather as much information as possible. Eve
Um, I can, but it's not all that different than the others - is there
something I am missing that would collect more info in the logs?
Thanks,
...tom
On Jan 23, 2008 9:32 PM, Tejun Heo <[EMAIL PROTECTED]> wrote:
>
> Thomas Evans wrote:
> > I hadn't tried that until just now - I have 2 3124 cards
Robert worte.
>
> Kuan, does this patch (using the notifiers to see if the command is
> really done) still work if one port on the controller has
> ADMA disabled
> because it's in ATAPI mode? I seem to recall Allen Martin mentioning
> that notifiers wouldn't work in this case.
>
I just tried
Thomas Evans wrote:
> I hadn't tried that until just now - I have 2 3124 cards, 1 without
> internal connections.
> Just tried the 1 with internal sata ports - it fails in the same way on
> a single drive.
There are cable which have SATA connector on one side and e-SATA on the
other. You can conn
Jeff Garzik wrote:
Robert Hancock wrote:
Jeff Garzik wrote:
Ping... sata_nv status is still a bit open for 2.6.24, and I would
like to move us forward a bit.
* Kuan's patch... it has been confirmed (and is needed), correct?
can someone work up a good patch for 2.6.24? The only one I ever
Thomas Evans wrote:
> Hi All -
>>> If I forget and get the "Plug and Play" error, disconnecting the
>>> drives and resetting isn't enough, nor is power cycling *or*
>>> unplugging the machine. I have to physically remove the card and
>>> restart without it, power down and then re-insert it. I cou
Robert Hancock wrote:
Jeff Garzik wrote:
Ping... sata_nv status is still a bit open for 2.6.24, and I would
like to move us forward a bit.
* Kuan's patch... it has been confirmed (and is needed), correct?
can someone work up a good patch for 2.6.24? The only one I ever
received was badly
Kuan Luo wrote:
First thank davide to help to send the attachment.
Robert,
The patch is to solve the error message "ata1: CPB flags CMD err,
flags=0x11" when testing HDS7250SASUN500G in rhel4u5.
I tested this hd in 2.6.24-rc7 which needed to remove the mask in
blacklist to run the ncq and the s
Hi All -
> > If I forget and get the "Plug and Play" error, disconnecting the
> > drives and resetting isn't enough, nor is power cycling *or*
> > unplugging the machine. I have to physically remove the card and
> > restart without it, power down and then re-insert it. I could only
> > plug the c
Now that hardreset is the preferred method of resetting, there's no
need for ATA_LFLAG_HRST_TO_RESUME flag. Kill it.
Signed-off-by: Tejun Heo <[EMAIL PROTECTED]>
---
drivers/ata/ahci.c |2 +-
drivers/ata/libata-pmp.c | 16
drivers/ata/sata_nv.c|5 -
drive
When both soft and hard resets are available, libata preferred
softreset till now. The logic behind it was to be softer to devices;
however, this doesn't really help much. Rationales for the change:
* BIOS may freeze lock certain things during boot and softreset can't
unlock those. This by it
ata_ehi_schedule_probe() was created to hide details of link-resuming
reset magic. Now that all the softreset workarounds are gone,
scheduling probe is very simple - set probe_mask and request RESET.
Kill ata_ehi_schedule_probe() and open code it. This also increases
consistency as ata_ehi_schedu
ATA_EHI_RESUME_LINK has two functions - promote reset to hardreset if
ATA_LFLAG_HRST_TO_RESUME is set and preventing EH from shortcutting
reset action when probing is requested. The former is gone now and
the latter can easily be achieved by making EH to perform at least one
reset if reset is requ
Some controllers can't reliably record the initial D2H FIS after SATA
link is brought online for whatever reason. Advanced controllers
which don't have traditional TF register based interface often have
this problem as they don't really have the TF registers to update
while the controller and link
Hello, all.
This is the first take of prefer-hardreset patchset. I've been
meaning to do this for quite some time now. Preferring softreset over
hardreset seemed okay at the beginning but libata has been and
continue accumulating more and more quirks to promote reset to
COMRESET to avoid SRST fa
On Wed, 23 Jan 2008 16:38:06 +0300
Sergei Shtylyov <[EMAIL PROTECTED]> wrote:
> Hello.
>
> Alan Cox wrote:
>
> >>Why you chose to use ioread32() and iowrite32() if your device is
> >> strictly
> >>memory mapped? Those functions add some overhead, and boil down to readl()
> >>and
>
> > T
Jeff Garzik wrote:
Ping... sata_nv status is still a bit open for 2.6.24, and I would like
to move us forward a bit.
* Kuan's patch... it has been confirmed (and is needed), correct? can
someone work up a good patch for 2.6.24? The only one I ever received
was badly word-wrapped, and at t
Anton Salnikov wrote:
This is Palmchip BK3710 IDE controller support for kernel version 2.6.24-rc8.
The IDE controller logic supports PIO, multiword DMA and ultra-DMA modes.
Supports interface to compact Flash (CF) configured in True-IDE mode.
Use ide_setup_dma() since BLK_DEV_PALMCHIP_BK3710
Hello.
Alan Cox wrote:
Why you chose to use ioread32() and iowrite32() if your device is strictly
memory mapped? Those functions add some overhead, and boil down to readl() and
There are distinct portability advantages but you shouldn't mix
ioread32/iowrite32 with ioremap as that isn't g
On Wednesday 23 January 2008, Benjamin Herrenschmidt wrote:
>
> On Wed, 2008-01-23 at 01:58 +0100, Bartlomiej Zolnierkiewicz wrote:
> > I'm more worried about breaking automatic build checking (make randconfig)
> > than a few extra bytes so if you remove all #ifdefs you'll have to either
> > make
those errors apears only when I use the harddrives with
the sii controller and only when I make operation between
the onboard sata and the sii sata controller, operations between
ide and drives that are on sii works perfectly...
On Tue, 22 Jan 2008, Jeff Garzik wrote:
> Dan Nica wrote:
> > hello
Tejun Heo wrote:
Factor out ata_pci_activate_sff_host() from ata_pci_one(). This does
about the same thing as ata_host_activate() but needs to be separate
because SFF controllers use different and multiple IRQs in legacy
mode.
This will be used to make SFF LLD initialization more flexible.
Sig
Robert Hancock wrote:
Kuan Luo wrote:
Robert hancock wrote:
What problem does this resolve? I tested it against the cache
flush/NCQ write switching problem we've been trying to solve, and it
doesn't look like it fixes that one - if I apply this patch and then
remove the udelay(20) in sata_nv.
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