Sergei Shtylyov wrote:
The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
including mode 5 used to check for the necessity of 66 MHz clocking -- this
caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
While fixing this, also remove PLL mode from
Hello.
Bartlomiej Zolnierkiewicz wrote:
Index: linux-2.6/drivers/ata/pata_hpt37x.c
===
--- linux-2.6.orig/drivers/ata/pata_hpt37x.c
+++ linux-2.6/drivers/ata/pata_hpt37x.c
@@ -8,12 +8,10 @@
this driver is lacking
Bartlomiej Zolnierkiewicz wrote:
* This driver is heavily based upon:
*
* linux/drivers/ide/pci/hpt366.c Version 0.36April 25, 2003
*
reference to hpt366 version should also be updated (or removed)
Disagree - its not based on the newer hpt366 driver. Its based on the old
Hello.
Alan Cox wrote:
one. Actually by now it bears almost no resemblence any of them
Indeed, unfortunately...
Oh I think its very fortunate. The original IDE one is 3 semi-related
drivers in one file all falling over one another. At least we can now
break them individually 8)
I'm
one. Actually by now it bears almost no resemblence any of them
Indeed, unfortunately...
Oh I think its very fortunate. The original IDE one is 3 semi-related
drivers in one file all falling over one another. At least we can now
break them individually 8)
Alan
-
To unsubscribe from this
While at it:
On Sunday 05 August 2007, Sergei Shtylyov wrote:
Index: linux-2.6/drivers/ata/pata_hpt37x.c
===
--- linux-2.6.orig/drivers/ata/pata_hpt37x.c
+++ linux-2.6/drivers/ata/pata_hpt37x.c
@@ -8,12 +8,10 @@
this driver
* This driver is heavily based upon:
*
* linux/drivers/ide/pci/hpt366.c Version 0.36April 25, 2003
*
reference to hpt366 version should also be updated (or removed)
Disagree - its not based on the newer hpt366 driver. Its based on the old
one. Actually by now it bears
Alan Cox wrote:
/* Compute DPLL */
- dpll = 2;
- if (port-udma_mask 0xE0)
- dpll = 3;
+ dpll = (port-udma_mask 0xC0) ? 3 : 2;
Gak, I'd much rather people kept to the nice easy to read if() but fine
On Tue, 07 Aug 2007 20:49:34 -0400
Jeff Garzik [EMAIL PROTECTED] wrote:
Alan Cox wrote:
/* Compute DPLL */
- dpll = 2;
- if (port-udma_mask 0xE0)
- dpll = 3;
+ dpll = (port-udma_mask 0xC0) ? 3 : 2;
Gak, I'd much rather
Alan Cox wrote:
On Tue, 07 Aug 2007 20:49:34 -0400
Jeff Garzik [EMAIL PROTECTED] wrote:
Alan Cox wrote:
/* Compute DPLL */
- dpll = 2;
- if (port-udma_mask 0xE0)
- dpll = 3;
+ dpll = (port-udma_mask 0xC0) ? 3 :
Its a real fix for a real bug. The 374 needs a bit more stuff which is
sitting in my tree and I'll push for Sergei to comment tomorrow
OK, thanks. Do you also ACK
[PATCH 2/2] pata_hpt{37x|3x2n}: fix clock reporting
Yep
-
To unsubscribe from this list: send the line unsubscribe
On Sun, 2007-08-05 at 22:45 +0400, Sergei Shtylyov wrote:
The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
including mode 5 used to check for the necessity of 66 MHz clocking -- This
caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
While
Bob Ham wrote:
The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
including mode 5 used to check for the necessity of 66 MHz clocking -- This
caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
While fixing this, also remove PLL mode from the TODO
The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask
including mode 5 used to check for the necessity of 66 MHz clocking -- This
caused 66 MHz clock to be used for HPT374 chip that does not tolerate it.
While fixing this, also remove PLL mode from the TODO list -- I don't
/* Compute DPLL */
- dpll = 2;
- if (port-udma_mask 0xE0)
- dpll = 3;
+ dpll = (port-udma_mask 0xC0) ? 3 : 2;
Gak, I'd much rather people kept to the nice easy to read if() but fine
is_author_p()?Signed-off-by:Acked-by
15 matches
Mail list logo
