Re: FIS structure and Command List structure for AHCI SATA controller

2007-11-15 Thread mike zheng
Hi Jeff, Does kernel2.4 support this chip (Marvell's 88SE6121)? I assume kernel 2.4 supports AHCI device. Is there any patch for this chip I may apply? And which version of kernel2.4 shall I use? Thanks for your help, Mike On 11/9/07, Jeff Garzik <[EMAIL PROTECTED]> wrote: > mike zheng wrote: >

Re: FIS structure and Command List structure for AHCI SATA controller

2007-11-09 Thread Jeff Garzik
mike zheng wrote: Hi Jeff, Actually I am using Marvell's 88SE6121 on kernel 2.4. I just wonder do I have to enable the FIS? The SATA Command Table of the device have following definitions: 00h Command FIS 40h ATAPI Command (CDB) 60h RSVD 80h Physical Region Descriptor Table Does it mean I can

Re: FIS structure and Command List structure for AHCI SATA controller

2007-11-09 Thread mike zheng
Hi Jeff, Actually I am using Marvell's 88SE6121 on kernel 2.4. I just wonder do I have to enable the FIS? The SATA Command Table of the device have following definitions: 00h Command FIS 40h ATAPI Command (CDB) 60h RSVD 80h Physical Region Descriptor Table Does it mean I can only use FIS or ATAP

Re: FIS structure and Command List structure for AHCI SATA controller

2007-11-08 Thread Jeff Garzik
On Thu, Nov 08, 2007 at 10:38:25PM -0500, mike zheng wrote: > I am working on an AHCI SATA controller. For each port, there is one > FIS descriptor and one Command List, which points to a Received FIS > structure and Command List structure. So what is Received FIS > structure? The Command List stru

FIS structure and Command List structure for AHCI SATA controller

2007-11-08 Thread mike zheng
Hi All, I am working on an AHCI SATA controller. For each port, there is one FIS descriptor and one Command List, which points to a Received FIS structure and Command List structure. So what is Received FIS structure? The Command List structure points to Command Table, that has Command FIS field a