Jens Axboe wrote:
On Thu, Feb 17 2005, Jeff Garzik wrote:
It looks like I will need to do a workaround for all SATA ATAPI devices:
if the transfer is not a multiple of 4 bytes, pad it with an DMA 1-3
byte DMA segment.
Yeah we definitely need something like that. The optimal solution is to
make s
Mark Lord wrote:
Jens Axboe wrote:
It looks like I will need to do a workaround for all SATA ATAPI
devices: if the transfer is not a multiple of 4 bytes, pad it with an
DMA 1-3 byte DMA segment.
Yup, that requirement has existed on most of the hardware
I've done drivers for, both SATA and a lot
Jens Axboe wrote:
It looks like I will need to do a workaround for all SATA ATAPI devices:
if the transfer is not a multiple of 4 bytes, pad it with an DMA 1-3
byte DMA segment.
Yup, that requirement has existed on most of the hardware
I've done drivers for, both SATA and a lot of PATA chips too
On Thu, Feb 17 2005, Jeff Garzik wrote:
> Gary Poppitz wrote:
> >We tracked down a problem with the 964 chipset with a 0x180 ID code that
> >may save someone on the list some time.
> >
> >The chip will only transfer multiples of 4 bytes. Anything else will
> >cause it to hang.
>
>
> After furth
Another issue with ATAPI is that it _may_ or may not send an interrupt
prior writing the CDB.
This behavior is dependent on an obsolete and undocumented in ATAPI7 bit
5 of IDENTIFY PACKET DEVICE word 0, apparently.
Jeff
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Gary Poppitz wrote:
We tracked down a problem with the 964 chipset with a 0x180 ID code that
may save someone on the list some time.
The chip will only transfer multiples of 4 bytes. Anything else will
cause it to hang.
After further research, this is popping up on a number of chips (and
worke
Gary Poppitz wrote:
We tracked down a problem with the 964 chipset with a 0x180 ID code that
may save someone on the list some time.
The chip will only transfer multiples of 4 bytes. Anything else will
cause it to hang.
Interesting, either ULi or SiS set me a needs-to-be-cleaned-up-a-lot fix
fo
