To solve the puzzle, you need to review the actual binary machine
language instructions.
It happens that the XCHG instruction for exchanging a register with
accumulator is one byte long instruction, with the following contents
(Disclaimer: my source of information is an old 8086 user's manual, so
my information about 32-bit registers is based only upon guess):
Bit: 7 6 5 4 3 2 1 0
Value: 1 0 0 1 0 x1 x2 x3
where (x1,x2,x3) numbers the register to be exchanged with AX.
The register number assignments are:
AX 0
CX 1
DX 2
BX 3
SP 4
BP 5
SI 6
DI 7
(My guess that the corresponding 32-bit registers get the numbers 8-15,
but check it with an 80x86 user's manual, for x > '').
Therefore, the machine instruction corresponding to XCHG AX,AX is indeed
1 0 0 1 0 0 0 0
Which is 0x90.
If you exchange AX with another register, then the machine instruction
is 0x9y where y is as detailed above. For example, the machine
instruction for XCHG AX,CX is 0x91.
The machine language instruction for exchanging a register with memory
(or two registers, none of which is AX) is completely different. Its
opcode is:
1 0 0 0 0 1 1 w (i.e. 0x86 or 0x87)
And it is followed by 1-3 bytes describing the operands.
--- Omer
On Thu, 2004-11-11 at 23:16, Tal Achituv wrote:
> guy keren wrote:
>
> >
> >after all, a single machine-language op-code is _always_ translated into
> >the same command - no matter how you name the assembly-language mnemonic.
> >
> >
> OK.
>
> >as i said above, a machine-language opcode must have a single meaning. it
> >cannot mean different things in different times (unless you have different
> >_modes_ for the CPU, which cause it to interpret opcodes differently. i
> >assume this is not the same when it comes to non-priviledged op-codes).
> >
> >
> You got me confused. I'm familiar with assembly language, machine code,
> and the way one is translated to the other.
> BUT - I am uncertain about the different modes the CPU might be in.
>
> You implied in your response that only priviledged op-codes could have
> double interpertations - Are you _certain_ about that?
>
> It puzzles me too that there might be an option under-which 0x90 could
> be decoded into something else than the normal XCHG AX,AX. afaik it
> really causes the cpu to exchange AX with itself... :-)
>
> Please take a look at the response I wrote to Shachar Shemesh, and the
> following page out of the Intel op-code manual:
> http://www.achituv.com/intel_ref_3-462.jpg ("Intel Instruction Set
> Reference")
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