Signed-off-by: Michael Mueller
---
linux-headers/asm-s390/kvm.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h
index c5a93eb..bfe6925 100644
--- a/linux-headers/asm-s390/kvm.h
+++ b/linux-headers/a
Needed in several Chromebook models such as the Tegra-based ones.
Signed-off-by: Tomeu Vizoso
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 8e174ea..5b4d1c8 100644
--- a
This brings the DevFreq framework in and builds the ACTMON driver that
on Tegra124 will scale the external memory clock based on current load.
Signed-off-by: Tomeu Vizoso
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defco
This patch updates the binding information to reflect the
extra dt options which are now supported by the sdhci-st.c
driver which enable support for stih407 family silicon.
STiH410 SoC and later support UHS modes for eMMC, so the
driver now makes use of these common bindings. Examples
are provided
Add dt nodes to enable sdhci / eMMC for stih418-b2199 board.
Signed-off-by: Peter Griffin
---
arch/arm/boot/dts/stih418-b2199.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/stih418-b2199.dts
b/arch/arm/boot/dts/stih418-b2199.dts
index 926235c..a2fdada 10
The nodes have been split to allow as much commonality as possible.
The stih407 has a silicon bug with eMMC UHS modes (with top regs)
and as such doesn't have any of the uhs dt properties.
Signed-off-by: Peter Griffin
---
arch/arm/boot/dts/stih407-family.dtsi | 30 ++
To allow UHS modes to work properly we need to provide the st specific
set_uhs_signaling callback function. This function differs from the
generic sdhci_set_uhs_signaling callback in that we need to configure
the correct delay depending on the UHS mode, and also set the V18_EN
bit.
Signed-off-by:
Due to the tight timing constraints in some UHS modes, it is required to have
some delay management in the design. Two types of delay management are supported
in the HW: -
1) Static delay management
2) Dynamic delay management
NB: The delay management is only there when eMMC interface is selected
STiH407 family SoC's can have a reset signal for the controller which needs to
be managed. Also the eMMC controller has some additional 'top' memory mapped
registers which are used to manage the dynamic and static delay required for
UHS modes. This patch adds support for creating the mapping, which
Hi,
This series adds sd/emmc support to the sdhci-st.c driver for stih407
family silicon. The changes mainly involve configuring some extra glue
registers in the flashSS which configure the Arasan controller.
This series also adds support for UHS modes for eMMC. To allow
UHS HS200/SD104 modes to
Some additional quirks need to be enabled now we support UHS
modes. This avoids some spurious warnings like
"Got data interrupt 0x0002 even though no data operation was in progress"
Testing on stih410-b2120 board achieves the following speeds
with HS200 eMMC card.
max-frequency = 200Mhz
/dev
The stih407 family SoC's have additional glue registers in the flashSS which
are used to configure the Arasan controller.
This patch adds macros for the register offsets and bitfields which will be
used by subsequent patches to support stih407 family SoC's.
Signed-off-by: Peter Griffin
Signed-of
STiH407 family SoC's have glue registers in the flashSS subsystem which
are used to configure the Arasan HC. This patch configures these glue
registers according to what has been specified in the DT.
Signed-off-by: Peter Griffin
Signed-off-by: Giuseppe Cavallaro
Acked-by: Maxime Coquelin
---
d
27.03.2015 20:15, Florian Fainelli пишет:
> I think your concerns are valid, but I don't think there is going to be
> any problem with the approach I suggested because there is a contract
> that the fixed PHYs and regular PHYs need to
Hello Florian.
As promised, today I tried to resurrect my first
This patch implements the static part of the s390 cpu class definitions.
It defines s390 cpu models by means of virtual cpu ids (enum) which contain
information on the cpu generation, the machine class, the GA number and
the machine type. The cpu id is used to instantiate a cpu class per cpu
model.
The patch introduces S390 CPU facility bit numbers and names
as well as the architectural facility size limit in bytes.
Signed-off-by: Michael Mueller
---
target-s390x/cpu-facilities.h | 86 +++
1 file changed, 86 insertions(+)
create mode 100644 target-s
The patch implements routines to set and retrieve processor configuration
data and to retrieve machine configuration data. The machine related data
is used together with the cpu model facility lists to determine the list of
supported cpu models of this host. The above mentioned routines have QEMU
t
This patch set in combination with its kernel kvm patch set proposes an
implementation of S390 cpu models. The origin of this item is to provide
a means for management interfaces like libvirt to draw decisions if life
guest migration to a target hypervisor is reasonable.
A migration constraint is
On 30 March 2015 at 08:19, Alexander Shishkin
wrote:
> Mathieu Poirier writes:
>
>> Hey Alex,
>
> Hi Mathieu,
>
>> Have a look at the following patch and see if you agree with my approach.
>> If so
>> simply add the code to a third version.
>
> Greg's comment about the two levels of ioctls got
This patch implements the infrastructure to dynamically add cpu
model aliases.
Signed-off-by: Michael Mueller
Reviewed-by: Cornelia Huck
---
target-s390x/cpu-models.c | 89 +++
target-s390x/cpu-models.h | 11 ++
target-s390x/cpu.c| 1 +
3
This patch provides routines to dynamically update the previously defined
S390 cpu classes in the current host context. The main function performing
this process is s390_setup_cpu_classes(). It takes the current host context
and a facility list mask as parameter to setup the classes accordingly. It
On Mon, 30 Mar 2015, Steven Rostedt wrote:
> Hmm, I didn't realize there was an "and" version. I'm guessing this
> would bring down the instruction count even more?
Yes two segment prefixed instructions and a decrement.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" i
This patch defines S390 cpu facilities and their presence at the
different cpu model levels. Beside defining a base which facilities
have to be requested per cpu model, these sets are associated to the
defined cpu classes and used to calculate the list of supported
cpu models in context of the curr
This driver supports pinctrl/GPIO hardware found on Intel Sunrisepoint (a
Skylake PCH) providing users a pinctrl and GPIO interfaces (including GPIO
interrupts).
The driver is split into core and platform parts so that the same core
driver can be reused in other drivers for other Intel GPIO hardwa
On Mar 30, 2015 7:55 AM, "Christoph Lameter" wrote:
>
> On Sat, 14 Mar 2015, Andrew G. Morgan wrote:
>
> >
> > I thought I did. Please implement a lockable secure bit and I will
>
> Would this suffice? It puts the CAP_SETPCAP limitation back to how it
> was in my earlier patch.
>
I really don't l
The patch introduces routine s390_facility_test() which allows to
verify a specific facility bit is set.
Signed-off-by: Michael Mueller
---
target-s390x/cpu-models.c | 29 +
target-s390x/cpu-models.h | 1 +
2 files changed, 30 insertions(+)
diff --git a/target-s390x
This patch enables QEMU to instantiate S390 CPUs with cpu model types.
Signed-off-by: Michael Mueller
---
hw/s390x/s390-virtio.c | 12 +++-
target-s390x/helper.c | 9 ++---
2 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio
This patch implements the QMP command 'query-cpu-definitions' in the S390
context. The command returns a list of cpu model names in the current host
context. A consumer may successfully request each listed cpu model as long
for a given accelerator and machine this model is runnable.
request:
{"e
On Mon, Mar 30, 2015 at 7:27 AM, Denys Vlasenko wrote:
> On 03/26/2015 07:45 PM, Andy Lutomirski wrote:
>> On Thu, Mar 26, 2015 at 5:42 AM, Denys Vlasenko wrote:
>>> This change makes the check exact (no more false positives
>>> on kernel addresses).
>>>
>>> It isn't really important to be fully
The patch adds optional parameters to the QMP command query-cpu-definitions.
Thus the signature of routine arch_query_cpu_definitions needs to be changed
for the stub function and all target implementations:
target-arm
target-i386
target-ppc
target-s390
Signed-off-by: Michael Mueller
---
includ
After all of the earlier discussions I thought it would be better to
first get agreement on the basic way to allow implementation of the
bulk alloc in the common slab code. So this is a revision of the initial
proposal and it just covers the first patch.
This patch adds the basic infrastructure
This patch implements routine s390_cpu_model_init(). It is called by the
realize function during instantiation of an cpu object. Its task is to
initialize the current accelerator with the properties of the selected
processor model.
Signed-off-by: Michael Mueller
---
target-s390x/cpu-models.c | 3
This patch implements a new QMP request named 'query-cpu-model'.
It returns the cpu model of cpu 0 and its backing accelerator.
request:
{"execute" : "query-cpu-model" }
answer:
{"return" : {"name": "2827-ga2", "accel": "kvm" }}
Alias names are resolved to their respective machine type and G
This patch introduces the function cpu_desc_avail() which returns by
default true if not architecture specific implemented. Its intention
is to indicate if the cpu model description is available for display
by list_cpus(). This change allows cpu model descriptions to become
dynamically created by e
This patch introduces the helper "gen-facilities" which allows to generate
facility list definitions and masks at compile time. Its flexibility is
better and the error-proneness is lower when compared to static programming
time added statements.
The helper includes "target-s390x/cpu-facilities.h"
On 03/26/2015 07:45 PM, Andy Lutomirski wrote:
> On Thu, Mar 26, 2015 at 5:42 AM, Denys Vlasenko wrote:
>> This change makes the check exact (no more false positives
>> on kernel addresses).
>>
>> It isn't really important to be fully correct here -
>> almost all addresses we'll ever see will be u
> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Monday, March 30, 2015 2:03 AM
> To: KY Srinivasan
> Cc: da...@davemloft.net; net...@vger.kernel.org; linux-
> ker...@vger.kernel.org; de...@linuxdriverproject.org; o...@aepfle.de;
> a...@canonical.com; j
On Mon, Mar 30, 2015 at 02:02:27PM +, EunTaik Lee wrote:
>
> The problem was on 3.10.49.
>
> I carefully looked up the patches again and found out that there was
> a patch on 3.18 that will solve the problem
>
> commite4a60d139060975eb956717e4f63ae348d4d8cc5
> sysfs: driver core: Fix
On Sun, 29 Mar 2015, Hugh Dickins wrote:
> On Thu, 26 Mar 2015, David Rientjes wrote:
>
> > munmap(2) of hugetlb memory requires a length that is hugepage aligned,
> > otherwise it may fail. Add this to the documentation.
>
> Thanks for taking this on, David. But although munmap(2) is the one
"Kirill A. Shutemov" writes:
> Currently, we rely on compound_lock() to get page counts stable on
> splitting page refcounting. To get it work we also take the lock on
> get_page() and put_page() which is hot path.
>
> This patch rework splitting code to setup migration entries to stabilaze
> pag
Mathieu Poirier writes:
> Hey Alex,
Hi Mathieu,
> Have a look at the following patch and see if you agree with my approach. If
> so
> simply add the code to a third version.
Greg's comment about the two levels of ioctls got me thinking in the
direction of adding callbacks to stm_data on cas
On Wed, Mar 25, 2015 at 02:16:02PM +0530, Hariprasad S wrote:
> Hariprasad Shenai (1):
> cxgb4: update firmware to revision 1.13.32.0 for T4 and T5
>
> WHENCE | 8
> cxgb4/t4fw-1.12.25.0.bin | Bin 518656 -> 0 bytes
> cxgb4/t4fw-1.13.32.0.bin | Bin 0 -> 533504 b
On Mon, Mar 30, 2015 at 04:52:49PM +0300, Octavian Purdila wrote:
> What if we can do the pin configuration in gpiolib right after the
> GPIO controller is initialized. I am thinking of searching the ACPI
> namespace and looking for resources that have GpioInt entries for that
> particular GPIO con
On 3/27/2015 12:51 PM, Moore, Robert wrote:
+ cls_objects = obj_desc->package.elements;
+
+ if (obj_desc->common.type == ACPI_TYPE_PACKAGE &&
+ obj_desc->package.count == 3 &&
+ cls_objects[0]->common.type == ACPI_TYPE_INTEGER &&
+ cls_objects[1]->common.
- Original Message -
> debugfs_create_dir and debugfs_create_file may return -ENODEV when debugfs
> is not configured, so the return value should be checked against ERROR_VALUE
> as well, otherwise the later dereference of the dentry pointer would crash
> the kernel.
>
> Signed-off-by: Che
After TEST insn, JE actually performs "jump if zero",
let's use JZ mnemonic instead. No code changes,
but less confusion.
By the nature of TEST operation, it is often possible
to test a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
On 2015-03-30 15:31, Ard Biesheuvel wrote:
> On 30 March 2015 at 15:26, Russell King - ARM Linux
> wrote:
>> On Mon, Mar 30, 2015 at 02:38:35PM +0200, Michal Marek wrote:
>>> Is this a limitation of a particular ARM ABI or a limitation of a state
>>> of the art ARM linker or something else?
>>
>>
"Kirill A. Shutemov" writes:
> We're going to use migration entries instead of compound_lock() to
> stabilize page refcounts. Setup and remove migration entries require
> page to be locked.
>
> Some of split_huge_page() callers already have the page locked. Let's
> require everybody to lock the p
On Mon, 30 Mar 2015 12:38:15 +0900
Masami Hiramatsu wrote:
> (2015/03/28 6:37), Steven Rostedt wrote:
> > As there are many tracepoints that use __print_symbolic() to translate
> > numbers into ASCII strings, and several of these translate enums as
> > well, it causes a problem for user space too
Mathieu Poirier writes:
> +static int stm_send(void *addr, const void *data, u32 size)
> +{
> + u32 len = size;
> +
> + if (((unsigned long)data & 0x1) && (size >= 1)) {
> + writeb_relaxed(*(u8 *)data, addr);
> + data++;
> + size--;
> + }
> + if
On the Armada 375/38x/39x SoCs, in standby mode the SoC stay powered
and it is possible to wake-up from any interrupt sources. This patch
adds flag to the GIC irqchip driver to let linux know this.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/board-v7.c | 7 +++
1 file changed, 7 i
On the Armada 370/XP/38x/39x SoCs when the suspend to ram feature is
supported, the SoC is shutdown and will be wake up by an external
micro-controller, so there is no possibility to setup wake-up source
from Linux. However, in standby mode, as the SoC stay powered and it is
possible to wake-up fro
On the Armada 370/XP SoCs, in standby mode the SoC stay powered and it
is possible to wake-up from any interrupt sources. This patch adds
flag to the MPIC irqchip driver to let linux know this.
Signed-off-by: Gregory CLEMENT
---
drivers/irqchip/irq-armada-370-xp.c | 1 +
1 file changed, 1 insert
Until now only one Armada XP based board supported suspend to
ram. However most of the recent mvebu SoCs can support the standby
mode. Unlike for the suspend to ram, nothing special have to be done
for this SoC. This patch allow the system to use the standby mode on
Armada 370, 38x, 39x and XP SoCs
Hi,
Until now only one Armada XP based board supported suspend to
ram. This suspend to ram mode was unusual because it involved shutting
down the SoC and relied on a PIC to wake up the system.
However, most of the recent mvebu SoCs can support the standby
mode. Unlike for the suspend to ram, noth
mvebu_pm_init and mvebu_armada_xp_gp_pm_init are only called during
boot, so flag them with __init and save some memory.
Signed-off-by: Gregory CLEMENT
---
arch/arm/mach-mvebu/pm-board.c | 2 +-
arch/arm/mach-mvebu/pm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a
The problem was on 3.10.49.
I carefully looked up the patches again and found out that there was
a patch on 3.18 that will solve the problem
commit e4a60d139060975eb956717e4f63ae348d4d8cc5
sysfs: driver core: Fix glue dir race condition by gdp_mutex
Sorry for bothering you.
Thanks,
Eun Taik
Em Mon, Mar 30, 2015 at 10:06:35PM +0900, Namhyung Kim escreveu:
> On Mon, Mar 30, 2015 at 9:56 PM, Jiri Olsa wrote:
> > On Mon, Mar 30, 2015 at 09:48:52PM +0900, Namhyung Kim wrote:
> >> > @@ -380,10 +381,13 @@ static struct thread
> >> > *__machine__findnew_thread(struct machine *machine,
> >>
During hot-plugging of a disk(having a flaky link), the disk addition
stops and any further disk addition or removal doesn't happen on that
controller.
This is because, when driver receives DELAY_NOT_RESPONDING event for a disk
while
it is undergoing addition at the SCSI Transport layer, the dri
On Mon, Mar 30, 2015 at 02:06:07PM +0200, Peter Zijlstra wrote:
> On Mon, Feb 23, 2015 at 09:25:51AM -0500, Kan Liang wrote:
> > +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
> > @@ -673,6 +673,8 @@ void intel_pmu_pebs_enable(struct perf_event *event)
> > struct hw_perf_event *hwc = &event->h
On Mon, Mar 30, 2015 at 03:29:09PM +0200, Vincent Guittot wrote:
> On 30 March 2015 at 14:24, Peter Zijlstra wrote:
> > @@ -7647,6 +7648,8 @@ static void nohz_idle_balance(struct rq *this_rq,
> > enum cpu_idle_type idle)
> > break;
> >
> > rq = cpu_rq(balan
Update MPI 2.5 Release: MPI 2.5 Rev I (2.5.4) specification and 2.00.33 header
files
Below is the change set from the MPI specification for I Rev
1) Added Base Enclosure Level bit to the Flags field of Manufacturing Page 7.
2) Updated description of the MaxTargetPortConnectTime field of SAS IO U
Bump mpt3sas Driver version to v5.100.00.00
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h
b/drivers/scsi/mpt3sas/mpt3sas_base.h
index a182d26..29ecfd1 100644
---
On Mon, Mar 30, 2015 at 06:44:22PM +0530, Viresh Kumar wrote:
> On 30 March 2015 at 18:17, Peter Zijlstra wrote:
> > No, I means something else with that. We can remove the
> > tvec_base::running_timer field. Everything that uses that can use
> > tbase_running() AFAICT.
>
> Okay, there is one ins
Added the following Dell branding to the mpt3sas driver.
"VendorID" "DeviceID" "SubsystemVendor ID" "SubsystemDevice ID" Dell
Branding String
0x10000x0097 0x1028 0x1F46DELL
12Gbps HBA
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpt
For any SCSI command, if the driver receives IOC status = SCSI_IOC_TERMINATED
and log info = 0x32010081 then that command will be completed with DID_RESET
host status.
The definition of this log info value is "Virtual IO has failed and has to be
retried".
Firmware will provide this log info va
On Sun, Mar 29, 2015 at 02:20:25PM +0300, Anton Nayshtut wrote:
> Before commit 3900f29021f0bc7fe9815aa32f1a993b7dfdd402 ("bonding: slight
> optimizztion for bond_slave_override()") the override logic was to send
> packets
> with non-zero queue_id through the slave with corresponding queue_id, und
Em Mon, Mar 30, 2015 at 03:20:59PM +0200, Jiri Olsa escreveu:
> On Mon, Mar 30, 2015 at 10:07:08AM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Mon, Mar 30, 2015 at 02:56:31PM +0200, Jiri Olsa escreveu:
> > > On Mon, Mar 30, 2015 at 09:48:52PM +0900, Namhyung Kim wrote:
> > > > Hi Jiri,
> > > >
>
Bump mpt3sas driver version to v6.100.00.00.
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h
b/drivers/scsi/mpt3sas/mpt3sas_base.h
index 8f99024..402c2ee 100644
---
Added dma_mapping_error() API after mapping an address with dma_map_single()
API. Otherwise when CONFIG_DMA_API_DEBUG is enabled in the kernel, then it
complains about mpt3sas driver not calling dma_mapping_error after mapping an
address with dma_map_single
Signed-off-by: Sreekanth Reddy
---
Added support for below customer specific brandings
"VendorID" "DeviceID" "SubsystemVendor ID" "SubsystemDevice ID" Cisco
Branding String
0x1000 0x97 0x1137 0x154 Cisco
9300-8i 12Gbps SAS HBA
0x1000 0x97 0x1137 0
Add the following OEM's branding to the mpt3sas driver.
"VendorID" "DeviceID" "SubsystemVendor ID" "SubsystemDevice ID" Cisco
Branding String
0x1000 0x97 SVID = 0x1137 0x014C Cisco
9300-8E 12G SAS HBA
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/m
Below are the new changes to MPI 2.5 Rev K(2.5.6) specification and 2.00.35
header files
1) Added a minimum size requirement for target mode command buffers.
2) Added MinMSIxIndex and MaxMSIxIndex fields to CommandBufferPostBase Request.
3) For BIOS Page 1, added SSUTimeout field, and added Produc
Created a thread using alloc_ordered_workqueue() API in order to process the
works from firmware Work-queue sequentially instead of
create_singlethread_workqueue() API.
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpt3sas_scsih.c | 7 ++-
1 file changed, 6 insertions(+), 1 delet
scsi_dma_map API will return a negative value (i.e. -ENOMEM) if DMA mapping of
sg lists fails and zero if the sg list in the SCSI cmd is NULL. But drivers
doesn't handled sg list DMA mapping failure case properly.
So, Updated the code to return host busy error status to SCSI MID Layer (SML),
wh
On Fri, Mar 27, 2015 at 09:40:26PM +0800, Hanjun Guo wrote:
> On 2015年03月26日 11:49, Hanjun Guo wrote:
> >On 2015/3/26 1:21, Catalin Marinas wrote:
> >>On Tue, Mar 24, 2015 at 10:02:46PM +0800, Hanjun Guo wrote:
> >>>--- a/drivers/acpi/acpi_processor.c
> >>>+++ b/drivers/acpi/acpi_processor.c
> >>>@
Bump mpt3sas driver version to 9.100.00.00
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h
b/drivers/scsi/mpt3sas/mpt3sas_base.h
index 1fd1e7f..706f0a5 100644
--- a
Issue: When the disks are getting discovered and assigned device handles by the
kernel, a device block followed by an unblock (due to broadcast primitives)
issued by the driver is interspersed by the kernel changing the state of the
device. Therefore the unblock by the driver results in a no ope
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to
up-to 96.
Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post
free queue count is greater than 8.
2. Instead of using single ReplyPostHostInde
Removed the redundancy code while freeing the controller resources.
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 57 +
1 file changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c
b/drivers/sc
Following is the change set,
1. Added more defines for the BiosOptions field of MPI2_CONFIG_PAGE_BIOS_1.
2. Added MPI2_TOOLBOX_CLEAN_BIT26_PRODUCT_SPECIFIC definition.
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpi/mpi2.h | 5 +++--
drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h | 14 +
Update MPI2 strings to MPI2.5.
Signed-off-by: Sreekanth Reddy
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 3 +--
drivers/scsi/mpt3sas/mpt3sas_base.h | 1 -
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c
b/drivers/scsi/mpt3sas/mpt3sas_base.c
index
Driver initialization fails if driver tries to send IOC facts request message
when the IOC is in reset or in a fault state.
This patch will make sure that
1.Driver to send IOC facts request message only if HBA is in operational or
ready state.
2.If IOC is in fault state, a diagnostic reset wou
This Patch will provide more details of the devices such as slot number,
enclosure logical id, enclosure level & connector name in the following
scenarios,
- When end device is added in the topology,
- When the end device is removed from the setup,
- When the SCSI mid layer issues TASK ABORT/ DE
This patch set contains all the features and defect fixes from Phase4 to Phase8.
Please review this patch set and consider these patches for next kernel release.
Next time onwards we will make sure to post individual patches as and when we
develop a feature & done basic testing instead of postin
On Mon, Feb 23, 2015 at 09:25:53AM -0500, Kan Liang wrote:
> +/*
> + * Flags PEBS can handle without an PMI.
> + *
> + * TID can only be handled by flushing at context switch.
> + */
> +#define PEBS_FREERUNNING_FLAGS \
> + (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
> +
On Mon, Mar 30, 2015 at 4:33 PM, Mika Westerberg
wrote:
> On Mon, Mar 30, 2015 at 03:55:14PM +0300, Octavian Purdila wrote:
>> On Mon, Mar 30, 2015 at 12:52 PM, Mika Westerberg
>> wrote:
>> > On Fri, Mar 27, 2015 at 11:36:25AM +0100, Linus Walleij wrote:
>> >> On Fri, Mar 27, 2015 at 11:06 AM, Mi
On Mon, Feb 23, 2015 at 09:25:55AM -0500, Kan Liang wrote:
> From: Yan, Zheng
>
> Flush the PEBS buffer during context switch if PEBS interrupt threshold
> is larger than one. This allows perf to supply TID for sample outputs.
>
> Signed-off-by: Yan, Zheng
> Signed-off-by: Kan Liang
> ---
> a
On Mon, 30 Mar 2015 11:47:01 +0900
Namhyung Kim wrote:
> > Cc: Namjae Jeon
> > Cc: Pankaj Kumar
> > Cc: Jaegeuk Kim
>
> AFAIK Jaegeuk's samsung email is not valid anymore..
>
> $ grep -a Jaegeuk MAINTAINERS
> M: Jaegeuk Kim
>
Thanks. That's what I get for using git blame instead of
On Mon, 30 Mar 2015 11:41:00 +0900
Namhyung Kim wrote:
> > + * The trace_enum_maps are saved in an array whith two extra elements,
>
> s/whith/with/
Heh, thanks for catching that.
>
> > + * one at the beginning, and one at the end. The beginning item contains
> > + * the count of the saved m
On Mon, Feb 23, 2015 at 09:25:54AM -0500, Kan Liang wrote:
> From: Yan, Zheng
>
> When PEBS interrupt threshold is larger than one, the PEBS buffer
> may include multiple records for each PEBS event. This patch makes
> the code first count how many records each PEBS event has, then
> output the s
On 26 March 2015 at 14:02, Preeti U Murthy wrote:
> When a CPU is kicked to do nohz idle balancing, it wakes up to do load
> balancing on itself, followed by load balancing on behalf of idle CPUs.
> But it may end up with load after the load balancing attempt on itself.
> This aborts nohz idle bal
On Mon, 30 Mar 2015 07:07:10 +0800
Wanpeng Li wrote:
> +static int find_next_push_cpu(struct rq *rq)
> +{
> + struct rq *next_rq;
> + int cpu;
> +
> + while (1) {
> + cpu = dlo_next_cpu(rq);
> + if (cpu >= nr_cpu_ids)
> + break;
> +
On Mon, Mar 30, 2015 at 09:33:16PM +0800, Ouyang Zhaowei (Charles) wrote:
> If the VM has multi-cpu the vcpu_info of cpu0 is the member of the structure
> HYPERVISOR_shared_info,
> and the others is not, but after hold/release the VM, the vcpu_info will be
> reinitialized,
What is 'hold/release'
On Mon, 30 Mar 2015 07:44:30 -0500 (CDT)
Christoph Lameter wrote:
> > >
> > > or more compact
> > >
> > > unsigned int val = __this_cpu_read(current_context);
> > >
> > > __this_cpu_write(current_context, val & (val - 1));
> >
> > Maybe I'll just use your compact version.
>
> Hmmm... It cou
If the VM has multi-cpu the vcpu_info of cpu0 is the member of the structure
HYPERVISOR_shared_info,
and the others is not, but after hold/release the VM, the vcpu_info will be
reinitialized,
the vcpu_info of all the vcpus will be considered as the member of
HYPERVISOR_shared_info.
This will cau
On Mon, Mar 30, 2015 at 03:55:14PM +0300, Octavian Purdila wrote:
> On Mon, Mar 30, 2015 at 12:52 PM, Mika Westerberg
> wrote:
> > On Fri, Mar 27, 2015 at 11:36:25AM +0100, Linus Walleij wrote:
> >> On Fri, Mar 27, 2015 at 11:06 AM, Mika Westerberg
> >> wrote:
> >> > On Thu, Mar 26, 2015 at 06:28
On 30 March 2015 at 15:26, Russell King - ARM Linux
wrote:
> On Mon, Mar 30, 2015 at 02:38:35PM +0200, Michal Marek wrote:
>> Is this a limitation of a particular ARM ABI or a limitation of a state
>> of the art ARM linker or something else?
>
> It's a limitation of the ARM ISA.
>
> Normal PC-rela
On 30 March 2015 at 14:24, Peter Zijlstra wrote:
> On Mon, Mar 30, 2015 at 01:03:03PM +0100, Morten Rasmussen wrote:
>> On Mon, Mar 30, 2015 at 12:06:32PM +0100, Peter Zijlstra wrote:
>> > On Fri, Mar 27, 2015 at 05:56:51PM +, Morten Rasmussen wrote:
>> >
>> > > I agree that it is hard to pred
This patch fix a spelling typo in MODULE_DESCRIPTION in
wl1251/main.c
Signed-off-by: Masanari Iida
---
drivers/net/wireless/ti/wl1251/main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wireless/ti/wl1251/main.c
b/drivers/net/wireless/ti/wl1251/main.c
index d1
601 - 700 of 942 matches
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