在 2015年06月05日 14:32, Kever Yang 写道:
Hi Caesar,
Subject typo WIF/WFI.
OK
On 06/05/2015 12:47 PM, Caesar Wang wrote:
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.
Signed-off-by: Caesar Wang
---
* Andy Lutomirski wrote:
> On Thu, Jun 4, 2015 at 4:32 PM, Andy Lutomirski wrote:
>
> > AFAICT the sole purpose for the hideous x86_64 idle_notifier mess is to
> > support i7300_idle. IMO this junk does not belong in IRQ handling, etc.
> > Can
> > we redo this to work in some kind of gener
On 06/05/2015 08:02 AM, Suneel Garapati wrote:
> Adds support for Ceva sata host controller on Xilinx
> Zynq UltraScale+ MPSoC.
>
> Signed-off-by: Suneel Garapati
> ---
> Changes v2
> - Change module license string to GPL v2
> ---
> drivers/ata/Kconfig | 9 ++
> drivers/ata/Makefile|
At the moment DMA map/unmap requests are handled irrespective to
the container's state. This allows the user space to pin memory which
it might not be allowed to pin.
This adds checks to MAP/UNMAP that the container is enabled, otherwise
-EPERM is returned.
Signed-off-by: Alexey Kardashevskiy
[a
On 06/05/2015 08:02 AM, Suneel Garapati wrote:
> adds bindings for CEVA AHCI SATA controller. optional property
> broken-gen2 is useful incase of hardware speed limitation.
>
> Signed-off-by: Suneel Garapati
> ---
> Documentation/devicetree/bindings/ata/ahci-ceva.txt | 20
>
At the moment the DMA setup code looks for the "ibm,opal-tce-kill"
property which contains the TCE kill register address. Writing to
this register invalidates TCE cache on IODA/IODA2 hub.
This moves the register address from iommu_table to pnv_pnb as this
register belongs to PHB and invalidates TC
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such a
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map
TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
on huge guests (hundreds of GB of RAM) so the kernel might be unable to
allocate contiguous chunk of physical memory to store the TCE table.
To address this, POWER8 CPU (actually, IODA2) supports multi-level
TCE tables, up to 5
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag as the old TCE value (more precisely -
the permission bit
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table.
IODA2 actually needs PCI addresses to invalidate the cache. Those
can be calculated from host addresses but since
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
This reworks debug messages to show the current value and the limit.
This stores the locked pages number in the container so when unlocking
the iommu table pointer won't be needed. This does n
This moves page pinning (get_user_pages_fast()/put_page()) code out of
the platform IOMMU code and puts it to VFIO IOMMU driver where it belongs
to as the platform code does not deal with page pinning.
This makes iommu_take_ownership()/iommu_release_ownership() deal with
the IOMMU table bitmap onl
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds the requirement for @it_ops to be initialized before calling
iommu_init_table() to m
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
Since compoun
This is a part of moving TCE table allocation into an iommu_ops
callback to support multiple IOMMU groups per one VFIO container.
This moves the code which allocates the actual TCE tables to helpers:
pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages().
These do not allocate/free
This adds tce_iommu_take_ownership() and tce_iommu_release_ownership
which call in a loop iommu_take_ownership()/iommu_release_ownership()
for every table on the group. As there is just one now, no change in
behaviour is expected.
At the moment the iommu_table struct has a set_bypass() which enabl
This is a part of moving DMA window programming to an iommu_ops
callback. pnv_pci_ioda2_set_window() takes an iommu_table_group as
a first parameter (not pnv_ioda_pe) as it is going to be used as
a callback for VFIO DDW code.
This should cause no behavioural change.
Signed-off-by: Alexey Kardashe
[ CCed Zhang Yang ]
On 06/04/2015 04:36 PM, Paolo Bonzini wrote:
On 04/06/2015 10:23, Xiao Guangrong wrote:
So, why do you need to always use IPAT=0? Can patch 15 keep the current
logic for RAM, like this:
if (is_mmio || kvm_arch_has_noncoherent_dma(vcpu->kvm))
ret = kvm_mtr
This replaces direct accesses to TCE table with a helper which
returns an TCE entry address. This does not make difference now but will
when multi-level TCE tables get introduces.
No change in behavior is expected.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
Reviewed-by: Gavin
Before the IOMMU user (VFIO) would take control over the IOMMU table
belonging to a specific IOMMU group. This approach did not allow sharing
tables between IOMMU groups attached to the same container.
This introduces a new IOMMU ownership flavour when the user can not
just control the existing IO
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is supported.
This defines iommu_table_group struct which stores pointers to
iommu_group and iommu_table(s). This rep
So far an iommu_table lifetime was the same as PE. Dynamic DMA windows
will change this and iommu_free_table() will not always require
the group to be released.
This moves iommu_group_put() out of iommu_free_table().
This adds a iommu_pseries_free_table() helper which does
iommu_group_put() and i
* Alexei Starovoitov wrote:
> On 6/4/15 7:04 AM, Ingo Molnar wrote:
> >>> # perf record -e bpf_source.c cmdline
> >>>
> >>> to create a eBPF filter from source,
> >>>
> >>>Use
> >>>
> >>># perf record -e bpf_object.o cmdline
> >>>
> >>>to create a eBPF filter from object intermedia.
> >>>
> >>
The existing code has 3 calls to iommu_register_group() and
all 3 branches actually cover all possible cases.
This replaces 3 calls with one and moves the registration earlier;
the latter will make more sense when we add TCE table sharing.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: Gavin S
This adds a way for the IOMMU user to know how much a new table will
use so it can be accounted in the locked_vm limit before allocation
happens.
This stores the allocated table size in pnv_pci_ioda2_get_table_size()
so the locked_vm counter can be updated correctly when a table is
being disposed.
We are adding support for DMA memory pre-registration to be used in
conjunction with VFIO. The idea is that the userspace which is going to
run a guest may want to pre-register a user space memory region so
it all gets pinned once and never goes away. Having this done,
a hypervisor will not have to
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
This is a pretty mechanical patch to make next patches simpler.
New tce_iommu_unuse_page() helper does put_page() now but it might skip
that after the memory registering patch applied.
As we are here, this removes unnecessary checks for a value returned
by pfn_to_page() as it cannot possibly retu
This is to make extended ownership and multiple groups support patches
simpler for review.
This should cause no behavioural change.
Signed-off-by: Alexey Kardashevskiy
[aw: for the vfio related changes]
Acked-by: Alex Williamson
Reviewed-by: David Gibson
Reviewed-by: Gavin Shan
---
drivers/v
The existing code programmed TVT#0 with some address and then
immediately released that memory.
This makes use of pnv_pci_ioda2_unset_window() and
pnv_pci_ioda2_set_bypass() which do correct resource release and
TVT update.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
arch
At the moment iommu_free_table() only releases memory if
the table was initialized for the platform code use, i.e. it had
it_map initialized (which purpose is to track DMA memory space use).
With dynamic DMA windows, we will need to be able to release
iommu_table even if it was used for VFIO in wh
This extends iommu_table_group_ops by a set of callbacks to support
dynamic DMA windows management.
create_table() creates a TCE table with specific parameters.
it receives iommu_table_group to know nodeid in order to allocate
TCE table memory closer to the PHB. The exact format of allocated
multi
This enables sPAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PC
This moves iommu_table creation to the beginning to make following changes
easier to review. This starts using table parameters from the iommu_table
struct.
This should cause no behavioural change.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
Reviewed-by: Gavin Shan
---
Change
The iommu_table struct keeps a list of IOMMU groups it is used for.
At the moment there is just a single group attached but further
patches will add TCE table sharing. When sharing is enabled, TCE cache
in each PE needs to be invalidated so does the patch.
This does not change pnv_pci_ioda1_tce_in
The set_iommu_table_base_and_group() name suggests that the function
sets table base and add a device to an IOMMU group.
The actual purpose for table base setting is to put some reference
into a device so later iommu_add_device() can get the IOMMU group
reference and the device to the group.
At t
So far one TCE table could only be used by one IOMMU group. However
IODA2 hardware allows programming the same TCE table address to
multiple PE allowing sharing tables.
This replaces a single pointer to a group in a iommu_table struct
with a linked list of groups which provides the way of invalida
The existing implementation accounts the whole DMA window in
the locked_vm counter. This is going to be worse with multiple
containers and huge DMA windows. Also, real-time accounting would requite
additional tracking of accounted pages due to the page size difference -
IOMMU uses 4K pages and syst
This adds create/remove window ioctls to create and remove DMA windows.
sPAPR defines a Dynamic DMA windows capability which allows
para-virtualized guests to create additional DMA windows on a PCI bus.
The existing linux kernels use this new window to map the entire guest
memory and switch to the
This relies on the fact that a PCI device always has an IOMMU table
which may not be the case when we get dynamic DMA windows so
let's use more reliable check for IOMMU group here.
As we do not rely on the table presence here, remove the workaround
from pnv_pci_ioda2_set_bypass(); also remove the
On Thu, Jun 04, 2015 at 11:37:01AM -0700, Kees Cook wrote:
> Calling kthread_run with a single name parameter causes it to be handled
> as a format string. Since the uisthread interface lacks format parameters,
> use "%s" to avoid any potential accidents from callers passing in dynamic
> string con
On Fri, May 29, 2015 at 11:38:45AM -0500, Rob Herring wrote:
> Currently, ci_default_pdata is common to all instances of the driver and
> gets modified by the core driver code. This is bad if there are multiple
> instances of the device with different settings such as the phy type. Fix
> this by ma
On Fri, May 29, 2015 at 11:38:46AM -0500, Rob Herring wrote:
> The Marvell 28nm HSIC PHY requires the port to be forced to HS mode after
> the port power is applied. This is done using the test mode in the PORTSC
> register.
>
> As HSIC is always HS, this work-around should be safe to do with all
Hi Caesar,
Subject typo WIF/WFI.
On 06/05/2015 12:47 PM, Caesar Wang wrote:
In idle mode, core1/2/3 of Cortex-A17 should be either power off or in
WFI/WFE state.
we can delay 1ms to ensure the CPU enter WFI state.
Signed-off-by: Caesar Wang
---
arch/arm/mach-rockchip/platsmp.c | 3 +++
1
From: Andi Kleen
This is a modified version of an earlier patch by Andi Kleen.
We expect architectures to describe the performance monitoring events
for each CPU in a corresponding JSON file, which look like:
[
{
"EventCode": "0x00",
"UMask": "0x01",
"Eve
Separate the event parsing code in perf_pmu__new_alias() out into
a separate function __perf_pmu__new_alias() so that code can be
called indepdently.
This is based on an earlier patch from Andi Kleen.
Signed-off-by: Sukadev Bhattiprolu
---
tools/perf/util/pmu.c | 42 ++
At run time (when 'perf' is starting up), locate the specific table
of PMU events that corresponds to the current CPU. Using that table,
create aliases for the each of the PMU events in the CPU. The use
these aliases to parse the user specified perf event.
In short this would allow the user to spe
Implement code that returns the generic CPU ID string for Powerpc.
This will be used to identify the specific table of PMU events to
parse/compare user specified events against.
Signed-off-by: Sukadev Bhattiprolu
Changelog[v14]
- [Jiri Olsa] Move this independent code off into a separate
Jiri Olsa pointed out, that the defines the
attribute '__weak'. We might as well use that.
Signed-off-by: Sukadev Bhattiprolu
---
tools/perf/util/pmu.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 0fcc624..c6b16b1 1
From: Andi Kleen
Add support to print alias descriptions in perf list, which
are taken from the generated event files.
The sorting code is changed to put the events with descriptions
at the end. The descriptions are printed as possibly multiple word
wrapped lines.
Example output:
% perf list
.
From: Andi Kleen
Implement the code to match CPU types to mapfile types for x86
based on CPUID. This extends an existing similar function,
but changes it to use the x86 mapfile cpu description.
This allows to resolve event lists generated by jevents.
Signed-off-by: Andi Kleen
Signed-off-by: Suk
From: Andi Kleen
I need a JSON parser. This adds the simplest JSON
parser I could find -- Serge Zaitsev's jsmn `jasmine' --
to the perf library. I merely converted it to (mostly)
Linux style and added support for non 0 terminated input.
The parser is quite straight forward and does not
copy any
From: Andi Kleen
The Intel events use a dot to separate event name and unit mask.
Allow dot in names in the scanner, and remove special handling
of dot as EOF. Also remove the hack in jevents to replace dot
with underscore. This way dotted events can be specified
directly by the user.
I'm not fu
Allow assigning categories "Topics" field to the PMU events i.e.
process the topic field from the JSON file and add a corresponding
topic field to the generated C events tables.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
Changelog[v14]
[Jiri Olsa] Move this independen
Previously we were dropping the useful longer descriptions that some
events have in the event list completely. Now that jevents provides
support for longer descriptions (see previous patch), add support for
parsing the long descriptions
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
From: Andi Kleen
Add support to group the output of perf list by the Topic field
in the JSON file.
Example output:
% perf list
...
Cache:
l1d.replacement
[L1D data line replacements]
l1d_pend_miss.pending
[L1D miss oustandings duration in cycles]
l1d_pend_miss.pending_cycles
From: Andi Kleen
Automatically adapt the now wider and word wrapped perf list
output to wider terminals. This requires querying the terminal
before the auto pager takes over, and exporting this
information from the pager subsystem.
Acked-by: Namhyung Kim
Signed-off-by: Andi Kleen
Signed-off-by
Signed-off-by: Sukadev Bhattiprolu
---
tools/perf/pmu-events/README | 122 ++
1 file changed, 122 insertions(+)
create mode 100644 tools/perf/pmu-events/README
diff --git a/tools/perf/pmu-events/README b/tools/perf/pmu-events/README
new file mode 100644
From: Andi Kleen
To work with existing mapfiles, assume that the first line in
'mapfile.csv' is a header line and skip over it.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
Changelog[v2]
All architectures may not use the "Family" to identify. So,
assume first l
From: Andi Kleen
Add a --no-desc flag to perf list to not print the event descriptions
that were earlier added for JSON events. This may be useful to
get a less crowded listing.
It's still default to print descriptions as that is the more useful
default for most users.
Signed-off-by: Andi Kleen
Implement support in jevents to parse long descriptions for events
that may have them in the JSON files. A follow on patch will make this
long description available to user through the 'perf list' command.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
Changelog[v14]
- [Ji
Previously we were dropping the useful longer descriptions that some
events have in the event list completely. This patch makes them appear with
perf list.
Old perf list:
baclears:
baclears.all
[Counts the number of baclears]
vs new:
perf list -v:
...
baclears:
baclears.all
[T
From: Andi Kleen
Add a PERF_CPUID variable to override the CPUID of the current CPU (within
the current architecture). This is useful for testing, so that all event
lists can be tested on a single system.
Signed-off-by: Andi Kleen
Signed-off-by: Sukadev Bhattiprolu
v2: Fix double free in earl
CPUs support a large number of performance monitoring events (PMU events)
and often these events are very specific to an architecture/model of the
CPU. To use most of these PMU events with perf, we currently have to identify
them by their raw codes:
perf stat -e r100f2 sleep 1
This patchs
On Fri, May 29, 2015 at 11:38:44AM -0500, Rob Herring wrote:
> Combine the ChipIdea USB binding into a single document to reduce
> duplication and fragmentation. This marks use of the old PHY bindings as
> deprecated. Future compatible bindings should use generic PHY binding.
>
> Signed-off-by: Ro
Adds support for CEVA SATA Host controller found on Xilinx Zynq
Ultrascale+ MPSoC.
Changes v2
- change module license to GPL v2
Suneel Garapati (2):
devicetree:bindings: add devicetree bindings for ceva ahci
drivers: ata: add support for Ceva sata host controller
.../devicetree/bindings/at
* George Spelvin wrote:
> It's running at 3.4 GHz, so I expect 729478 ticks per 256 PIT counts, and
> 415039
> ticks per 8192 Hz RTC tick.
> (PIT reads are 1353 ns each, while RTC reads are 1142 ns.)
>
> RTC edge at 99172986783, delta 0, range 7764, iter 7
> RTC edge at 99173401719
On Mon, 2015-05-25 at 10:14 +0800, Yingjoe Chen wrote:
> On Thu, 2015-05-21 at 21:29 +0800, YH Huang wrote:
This patch series add the use of display PWM driver and documentation
for Mediatek SoCs. The driver is used to support the backlight of
the panel. This is based on v4.1-rc1.
> > YH Huang
Hi Guenter,
I based my work on the work done in mpc8xxx_wdt.c, which is in mainline.
The point of my patch is for a built-in scenario.
I have an external chip who controls the watchdog, and it need to have
it IN pin toggle within 1.6s, otherwise it trigger the watchdog.
With a default gpio_wdt
adds bindings for CEVA AHCI SATA controller. optional property
broken-gen2 is useful incase of hardware speed limitation.
Signed-off-by: Suneel Garapati
---
Documentation/devicetree/bindings/ata/ahci-ceva.txt | 20
1 file changed, 20 insertions(+)
create mode 100644 Documen
Adds support for Ceva sata host controller on Xilinx
Zynq UltraScale+ MPSoC.
Signed-off-by: Suneel Garapati
---
Changes v2
- Change module license string to GPL v2
---
drivers/ata/Kconfig | 9 ++
drivers/ata/Makefile| 1 +
drivers/ata/ahci_ceva.c | 225 ++
* George Spelvin wrote:
> Ingo Molnar wrote:
> > - Alternatively, I also tried a different method: to set up the RTC
> > periodic IRQ during early boot, but not have an IRQ handler, polling
> > RTC_PF in the rtc_cmos_read(RTC_INTR_FLAGS) IRQ status byte.
> >
> > Unfortunately when I do thi
This patch adds a new field in struct irq_2_iommu, which can
capture whether the entry is in posted mode or remapped mode.
Signed-off-by: Feng Wu
Suggested-by: Thomas Gleixner
---
drivers/iommu/intel_irq_remapping.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/iommu/inte
Implement irq_set_vcpu_affinity for intel_ir_chip.
Signed-off-by: Feng Wu
Reviewed-by: Jiang Liu
Acked-by: David Woodhouse
---
arch/x86/include/asm/irq_remapping.h | 5 +
drivers/iommu/intel_irq_remapping.c | 43
2 files changed, 48 insertions(+)
dif
Return error when inserting a new IOMMU which doesn't support PI
if PI is currently in use.
Signed-off-by: Feng Wu
---
drivers/iommu/intel_irq_remapping.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/intel_irq_remapping.c
b/drivers/iommu/intel_irq_remapping.c
index 554e2
We don't need to migrate the irqs for VT-d Posted-Interrupts here.
When 'pst' is set in IRTE, the associated irq will be posted to
guests instead of interrupt remapping. The destination of the
interrupt is set in Posted-Interrupts Descriptor, and the migration
happens during vCPU scheduling.
Howev
From: Thomas Gleixner
The IRTE (Interrupt Remapping Table Entry) is either an entry for
remapped or for posted interrupts. The hardware distiguishes between
remapped and posted entries by bit 15 in the low 64 bit of the
IRTE. If cleared the entry is remapped, if set it's posted.
The entries have
Add helper function to detect VT-d Posted-Interrupts capability.
Signed-off-by: Feng Wu
Reviewed-by: Jiang Liu
Acked-by: David Woodhouse
---
include/linux/intel-iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 0af9b03..
FWIW, I wrote my own test routine, with some interesting results.
It's a rude bodge and obviously not kernel-quality, but included if
anyone wants to mess with it.
My machine is an X79 motherboard with a common ITE IT8728F SuperIO
chip providing both RTC and PIT.
The intersting bit is that I can
Set Posted-Interrupts capability for Intel iommu when IR is enabled,
clear it when IR is disabled.
Signed-off-by: Feng Wu
---
drivers/iommu/intel_irq_remapping.c | 30 ++
drivers/iommu/irq_remapping.c | 2 ++
drivers/iommu/irq_remapping.h | 3 +++
3 file
This patch adds a new interface irq_remapping_cap() to detect
whether irq remapping supports new features, such as VT-d
Posted-Interrupts. We export this function out, so that KVM
code can check this and use this mechanism properly.
Signed-off-by: Feng Wu
Reviewed-by: Jiang Liu
---
arch/x86/inc
VT-d Posted-Interrupts is an enhancement to CPU side Posted-Interrupt.
With VT-d Posted-Interrupts enabled, external interrupts from
direct-assigned devices can be delivered to guests without VMM
intervention when guest is running in non-root mode.
You can find the VT-d Posted-Interrtups Spec. in
This patch adds a new member capability to struct irq_remap_ops,
this new function ops can be used to check whether some
features are supported, such as VT-d Posted-Interrupts.
Signed-off-by: Feng Wu
Reviewed-by: Jiang Liu
---
arch/x86/include/asm/irq_remapping.h | 4
drivers/iommu/irq_rem
Hi Al,
Today's linux-next merge of the vfs tree got a conflict in fs/namei.c between
commit 890458a43dbd ("path: New helpers path_get_pin/path_put_unpin for path
pin") from the nfsd tree and commit 894bc8c4662b ("namei: remove restrictions
on nesting depth") from the vfs tree.
I fixed it up (see
On Fri, 2015-06-05 at 10:22 +0530, Sudip Mukherjee wrote:
> On Thu, Jun 04, 2015 at 01:48:31PM -0700, Joe Perches wrote:
[]
> ccing you just slipped out of my mind.
No worries.
> > > diff --git a/drivers/staging/fbtft/fbtft-core.c
> > > b/drivers/staging/fbtft/fbtft-core.c
> > []
> > > @@ -1067,
On Tue, May 12, 2015 at 7:47 AM, Jerome Glisse wrote:
> On Tue, May 12, 2015 at 10:53:47AM +1000, Dave Chinner wrote:
>> On Mon, May 11, 2015 at 11:18:36AM +0200, Ingo Molnar wrote:
>> IMO, we need to be designing around the concept that the filesytem
>> manages the pmem space, and the MM subsyste
This patch introduced a few functions to print the event trace log to
STM buffer when the trace event happen and the event information
would be committed to ring buffer.
Before outputting the trace log to STM, we have to get the human readable
trace log content and print it into a local buffer in
Hi James,
On Wed, Jun 03, 2015 at 03:06:16PM +0800, james.chen wrote:
> From: "james.chen"
>
> This patch refer 3.10 driver code to solve firmware upgrade
> issue(Change 266813) and enable noise-immunity(Change 243875).
>
> BUG=chrome-os-partner:39373
> TEST=Test Elan Touch Screen on cyan proje
Adding the function 'trace_event_stm_output_##call' for printing events
trace log into STM blocks.
This patch also added a function call at where the events have been
committed to ring buffer to export the trace event information to
STM blocks.
Signed-off-by: Chunyan Zhang
---
include/linux/ftr
IP blocks allowing a variety of trace sources to log debugging
information to a pre-defined area have been introduced on a couple of
architecture [1][2]. These system trace blocks (also known as STM)
typically follow the MIPI STPv2 protocol [3] and provide a system wide
logging facility to any devi
From: Mathieu Poirier
This patch adds a driver that models itself as an stm_source and
who's sole purpose is to export an interface to the rest of the
kernel. Once the stm and stm_source have been linked via sysfs,
everything that is passed to the interface will endup in the STM
trace engine.
S
On Monday 25 May 2015 09:24 AM, Noam Camus wrote:
> From: Noam Camus
>
> Support command line parameters of the form:
> earlycon=,io|mmio|mmio32|mmio32be,,
>
> This commit seem to be needed even after commit:
> serial: 8250: Add support for big-endian MMIO accesses
> c627f2ceb692e8a9358b64ac2d13
On Tue, May 19, 2015 at 10:18:05PM +0800, Herbert Xu wrote:
> On Tue, May 19, 2015 at 09:50:28AM -0400, Theodore Ts'o wrote:
> >
> > Finally, this is only going to block *once*, when the system is
> > initially botting up. Why is it so important that we get the
> > asynchronous nature of this righ
RAID stripe and/or chunk
>> > size boundaries.
>>
>> I'll test it on large HW raid setup.
>>
>> Here is HW RAID5 setup with 19 278G HDDs on Dell R730xd(2sockets/48
>> logical cpus/264G mem).
>> http://minggr.net/pub/20150604/hw_raid5.jpg
>>
>&
On 06/05/2015 01:54 PM, MyungJoo Ham wrote:
>>
>> IRQ signal before driver probe is needless because driver sends
>> current state after platform booting done.
>> So, this patch clears MUIC IRQ bits before request IRQ.
>>
>> Signed-off-by: Jaewon Kim
>> ---
>> drivers/extcon/extcon-max77843.c
Hi Jeremiah,
thanks for responding!
I did have my mobile phone very nearby also connected to the bluetooth
headphones while my laptop was still using 11n wifi. I didn't have any
noticeable issues with bluetooth there.
But I got the feeling that my phone's android drivers + hardware for
bluetooth
Hi Kyle,
Great to hear you haven't had any problems since applying this patch!
I'm looking forward to seeing it in the Linux master branch too.
Version 5 of the patch has been accepted and committed to the media tree
by Mauro:
http://git.linuxtv.org/cgit.cgi/media_tree.git/commit/?id=7797808
+CC linux-serial
On Thursday 14 May 2015 06:34 PM, Vineet Gupta wrote:
> On Thursday 14 May 2015 06:23 PM, Arnd Bergmann wrote:
>
> On Thursday 14 May 2015 15:48:42 Alexey Brodkin wrote:
>
>
>> >
>> > chosen {
>> > - bootargs = "console=tty0 console=ttyS3,115200n8
>> > c
What Time?
Did you get my mail? What time should i call you?
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org
1 - 100 of 777 matches
Mail list logo
