When a CPU is offlined all interrupts that have action are migrated to
other still online CPUs. However, if the interrupt has chained handler
installed this is not done. Chained handlers are used by GPIO drivers which
support interrupts, for instance.
When affinity is not corrected properly we end
In some cases it is useful to know if the interrupt in question has chained
handler installed. For example when a cpu is offlined the architecture code
needs to know if it has any users so that it can fixup affinity
accordingly.
To make this possible we introduce a new flag IRQ_IS_CHAINED that is
Hi Rabin,
your commit ("CRIS v32: remove old GPIO and LEDs code") is in today's
linux-next tree (i.e., 20151002). Among other Kconfig options, the
commit removes ETRAX_VIRTUAL_GPIO but leaves the following references in
the code:
0 arch/cris/arch-v32/kernel/setup.c 132 #ifdef CONFIG_ETRAX_
Updates hot cpu notification handling for code data prioritization(cdp).
The capacity bitmask(cbm) is global for both data and instruction and we
need to update the new online package with all the cbms by writing to
the IA32_L3_QOS_n MSRs.
Signed-off-by: Vikas Shivappa
Signed-off-by: Fenghua Yu
On Intel SKUs that support Code Data Prioritization(CDP), intel_rdt
operates in 2 modes - legacy cache allocation mode/default or CDP mode.
When CDP is enabled, the number of available CLOSids is halved. Hence the
enabling is done when less than half the number of CLOSids available are
used. When
This patch set supports Intel code data prioritization which is an
extension of cache allocation and allows to allocate code and data cache
seperately. It also includes cgroup interface for the user as seperate
patches. The cgroup interface for cache alloc is also resent.
Details of the feature ca
This patch adds enumeration support for Code Data Prioritization(CDP)
feature found in future Intel Xeon processors. It includes CPUID
enumeration routines for CDP.
CDP is an extension to Cache Allocation and lets threads allocate subset
of L3 cache for code and data separately. The allocation is
Adds two files to the intel_rdt cgroup 'dcache_cbm' and 'icache_cbm'
when code data prioritization(cdp) support is present. The files
represent the data capacity bit mask(cbm) and instruction cbm for L3
cache. User can specify the data and code cbm and the threads belonging
to the cgroup would get
Add support to manage CLOSid(CLass Of Service id) and capacity
bitmask(cbm) for code data prioritization(CDP).
Closid management includes changes to allocating, freeing closid and
closid_get and closid_put and changes to closid availability map during
mode switch. CDP has a separate cbm for code a
On Fri, 25 Sep 2015 09:39:51 -0700
Linus Walleij wrote:
> On Tue, Sep 1, 2015 at 2:38 AM, Alban Bedel wrote:
>
> > Turn the ath79 driver into a true driver supporting multiple
> > instances. While at it also removed unneed includes and make use of
> > the BIT() macro.
> >
> > Signed-off-by: Alb
On 01. okt. 2015 13:52, Eric Dumazet wrote:
On Thu, Oct 1, 2015 at 4:43 AM, Holger Hoffstätte
wrote:
On 10/01/15 13:29, Eric Dumazet wrote:
commit 83fccfc3940c4a2db90fd7e7079f5b465cd8c6af
Author: Eric Dumazet
Date: Thu Aug 13 15:44:51 2015 -0700
inet: fix potential deadlock in reqsk
>> +config SND_SOC_SUNXI_DAI_SPDIF
>> +tristate
>> + depends on OF
>> +select SND_SOC_GENERIC_DMAENGINE_PCM
>> +select REGMAP_MMIO
>> +
>> +config SND_SOC_SUNXI_MACHINE_SPDIF
>> +tristate "APB on-chip sun4i/sun5i/sun7i SPDIF"
>> + depends on OF
>> +se
On 09/30/2015 01:37 AM, Suman Anna wrote:
The default clock enabling functions for TI clocks -
omap2_dflt_clk_enable() and omap2_dflt_clk_disable() perform a
NULL check for the enable_reg field of the clk_hw_omap structure.
This enable_reg field however is merely a combination of the index
of the
Adds a description of Cache allocation technology, overview of kernel
framework implementation. The framework has APIs to manage class of
service, capacity bitmask(CBM), scheduling support and other
architecture specific implementation. The APIs are used to build the
cgroup interface in later patch
This patch adds different APIs to manage the L3 cache capacity bitmask.
The capacity bit mask(CBM) needs to have only contiguous bits set. The
current implementation has a global CBM for each class of service id.
There are APIs added to update the CBM via MSR write to IA32_L3_MASK_n
on all packages
On Tue, 15 Sep 2015 08:12:01 +0900,
Stephen Rothwell wrote:
>
> Hi Yoshinori,
>
> On Tue, 15 Sep 2015 09:10:30 +1000 Stephen Rothwell
> wrote:
> >
> > Please do "gitk 9751a9e449da..h8300-next" in your tree and look at
> > it (9751a9e449da is in Linus' tree). As I suggested above, maybe you
> >
Adds some data-structures and APIs to support Class of service
management(closid). There is a new clos_cbm table which keeps a 1:1
mapping between closid and capacity bit mask (cbm)
and a count of usage of closid. Each task would be associated with a
Closid at a time and this patch adds a new field
This patch includes CPUID enumeration routines for Cache allocation and
new values to track resources to the cpuinfo_x86 structure.
Cache allocation provides a way for the Software (OS/VMM) to restrict
cache allocation to a defined 'subset' of cache which may be overlapping
with other 'subsets'. T
Adds support for IA32_PQR_ASSOC MSR writes during task scheduling. For
Cache Allocation, MSR write would let the task fill in the cache
'subset' represented by the task's capacity bit mask.
The high 32 bits in the per processor MSR IA32_PQR_ASSOC represents the
CLOSid. During context switch kernel
This patch adds hot plug cpu support for Intel Cache allocation. Support
includes updating the cache bitmask MSRs IA32_L3_QOS_n when a new CPU
package comes online or goes offline. The IA32_L3_QOS_n MSRs are one per
Class of service on each CPU package. The new package's MSRs are
synchronized with
This patch is specific to Intel haswell (hsw) server SKUs. Cache
Allocation on hsw server needs to be enumerated separately as HSW does
not have support for CPUID enumeration for Cache Allocation. This patch
does a probe by writing a CLOSid (Class of service id) into high 32 bits
of IA32_PQR_MSR an
Add a new cgroup 'intel_rdt' to manage cache allocation. Each cgroup
directory is associated with a class of service id(closid). To map a
task with closid during scheduling, this patch removes the closid field
from task_struct and uses the already existing 'cgroups' field in
task_struct.
The cgrou
Add documentation on using the cache allocation cgroup interface with
examples.
Signed-off-by: Vikas Shivappa
Signed-off-by: Fenghua Yu
---
Documentation/cgroups/rdt.txt | 133 ++
1 file changed, 133 insertions(+)
create mode 100644 Documentation/cgroups
- In rapl_cpu_init, use the existing package<->core map instead of
looping through all cpus in rapl_cpumask.
- In rapl_cpu_exit, use the same mapping instead of looping all online
cpus. In large systems with large number of cpus the time taken to
loop may be expensive and also the time increa
- In cqm_pick_event_reader, use the existing package<->core map instead
of looping through all cpus in cqm_cpumask.
- In intel_cqm_cpu_exit, use the same map instead of looping through
all online cpus. In large systems with large number of cpus the time
taken to loop may be expensive and also
Brian, Archit,
On Thu, 1 Oct 2015 19:44:34 -0700
Brian Norris wrote:
> On Wed, Aug 19, 2015 at 10:19:02AM +0530, Archit Taneja wrote:
> > Some controllers can access the factory bad block marker from OOB only
> > when they read it in raw mode. When ECC is enabled, these controllers
> > discard r
This series has some preparatory patches and Intel cache allocation
support.
Prep patches :
Has some changes to hot cpu handling code in existing cache
monitoring and RAPL kernel code. This improves hot cpu notification
handling by not looping through all online cpus which could b
On Thu, Oct 01, 2015 at 11:31:36AM +0200, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.1.10 release.
> There are 29 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
* Andy Lutomirski wrote:
> >> Assuming it boots up fine on a typical distro, i.e. assuming that there
> >> are no
> >> surprises where PROT_READ && PROT_EXEC sections are accessed as data.
> >
> > I can't wait to find out what implicitly expects PROT_READ from
> > PROT_EXEC mappings. :)
So wha
On Fri, Oct 2, 2015 at 8:55 AM, Greg KH wrote:
> On Thu, Oct 01, 2015 at 09:17:42PM +0300, Alexander Kapshuk wrote:
>> Neither 'libg++.so', nor 'libstdc++.so' were found where the current
>> implementation expects them to be found in the distros below.
>>
>>
>> Gentoo Linux
>> Debian 6.0.10
>> Ora
This patch adds the support for Device tree bindings of extcon-gpio driver.
The extcon-gpio device tree node must include the both 'extcon-id' and
'extcon-gpio' property.
For exmaple:
usb_cable: extcon-gpio-0 {
compatible = "extcon-gpio";
extcon-id = <1>;
> > > 4.2.0 worked fine, 4.3.0-rc3-00042-g3225031 was the next one tested
> > > after that and with this kernel, ACPI enabling fails. This is Pentium
> > > III, 1 GHz, Intel 815 chipset, DMI tells something about "Packard Bell
> > > NEC" as the mainboard type.
> > >
> > > Full dmesg and config
* Dave Hansen wrote:
> On 10/01/2015 01:39 PM, Kees Cook wrote:
> > On Thu, Oct 1, 2015 at 4:17 AM, Ingo Molnar wrote:
> >> So could we try to add an (opt-in) kernel option that enables this
> >> transparently
> >> and automatically for all PROT_EXEC && !PROT_WRITE mappings, without any
> >> u
The qce driver use two dma_map_sg path according to SG are chained
or not.
Since dma_map_sg can handle both case, clean the code with all
references to sg chained.
Thus removing qce_mapsg, qce_unmapsg and qce_countsg functions.
Signed-off-by: LABBE Corentin
---
drivers/crypto/qce/ablkcipher.c |
On Thu, Oct 01, 2015 at 09:17:42PM +0300, Alexander Kapshuk wrote:
> Neither 'libg++.so', nor 'libstdc++.so' were found where the current
> implementation expects them to be found in the distros below.
>
>
> Gentoo Linux
> Debian 6.0.10
> Oracle Linux Server release 7.1
>
> The proposed implemen
This is a patch to fix up instances where quoted strings are split
across multiple lines in several instances in ieee80211_crypt_ccmp.c
Signed-off-by: Mike Dupuis
---
.../rtl8192u/ieee80211/ieee80211_crypt_ccmp.c | 27 +-
1 file changed, 11 insertions(+), 16 deletions(-)
This is a patch to add missing lines after variable decalarations
in two functions in ieee80211_crypt_ccmp.c
Signed-off-by: Mike Dupuis
---
drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211
This is a patch to correct block comment formatting in two
instances in ieee80211_crypt_ccmp.c
Signed-off-by: Mike Dupuis
---
drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/rtl8192u/ieee8021
This is a patch to correct indentation in one instance in
ieee80211_crypt_ccmp.c
Signed-off-by: Mike Dupuis
---
drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c
The ->read_xxx() methods are all passed the page number the NAND controller
is supposed to read, but ->write_xxx() do not have such a parameter.
This is a problem if we want to properly implement data
scrambling/randomization in order to mitigate MLC sensibility to repeated
pattern: to prevent bit
This is a patch to move open braces to the appropriate lines in
two instances in ieee80211_crypt_ccmp.c
Signed-off-by: Mike Dupuis
---
drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_ccmp.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/rtl8192u/ieee
This is a series of patches to correct several checkpatch.pl warnings
and errors in ieee80211_crypt_ccmp.c.
Checkpatch.pl before/after summary:
before: total: 2 errors, 23 warnings, 23 checks, 474 lines checked
after: total: 0 errors, 10 warnings, 27 checks, 469 lines checked
Mike Dupuis (5):
VM_BUG_ONs in PF_NO_TAIL() and PF_NO_COMPOUND() add 4+ KiB to
mm/build-in.o for DEBUG_VM kernel.
Let's hide them under new config option -- CONFIG_DEBUG_VM_PGFLAGS.
With the option enabled VM_BUG_ON_PGFLAGS() is equal to VM_BUG_ON_PAGE.
Signed-off-by: Kirill A. Shutemov
---
include/linux/mmdebu
On Thu, Oct 01, 2015 at 12:29:32PM -0500, Felipe Balbi wrote:
> On Thu, Sep 24, 2015 at 10:39:23AM -0700, Baolin Wang wrote:
> > The usb charger framework is based on usb gadget. The usb charger
> > need to be notified the state changing of usb gadget to confirm the
> > usb charger state.
> >
> >
The patch adds description for page flags policies.
Signed-off-by: Kirill A. Shutemov
---
include/linux/page-flags.h | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index 465ca42af633..19e4129f00e5 100
Few updates based on Andrew's feedback.
Kirill A. Shutemov (3):
page-flags: do not corrupt caller 'page' in PF_NO_TAIL
page-flags: add documentation for policies
page-flags: hide PF_* validation check under separate config option
include/linux/mmdebug.h| 6 ++
include/linux/page-f
Andrew noticed that PF_NO_TAIL() modifies caller's 'page'. This doesn't
trigger any bad results, because all users are inline functions which
doesn't use the variable beyond the point. But still not good.
The patch changes PF_NO_TAIL() to always return head page, regardless
'enforce'. This makes o
It is more convenient saving mmap length rather than (bit) mask. With
this patch, we can eliminate dependency to perf_evlist other than
getting mmap_desc for dealing with mmaps. The mask and length can be
converted using perf_evlist__mmap_mask/len().
Cc: Jiri Olsa
Cc: Adrian Hunter
Signed-off-
When indexed data file support is enabled, a dummy tracking event will
be used to track metadata (like task, comm and mmap events) for a
session and actual samples will be recorded in separate (intermediate)
files and then merged (with index table).
Provide separate mmap to the dummy tracking even
Since it's gonna share struct mmap with dummy tracking evsel to track
meta events only, let's move auxtrace out of struct perf_mmap.
Cc: Adrian Hunter
Signed-off-by: Namhyung Kim
---
tools/perf/builtin-record.c | 4 ++--
tools/perf/util/evlist.c| 30 +-
tools/pe
On Fri, Oct 02, 2015 at 07:19:04AM +0800, Boqun Feng wrote:
> Hi Peter,
>
> Please forgive me for the format of my reply. I'm travelling,
> and replying from my phone.
>
> 2015年10月1日 下午7:28，"Peter Zijlstra" 写道：
> >
> > On Wed, Sep 16, 2015 at 11:49:34PM +0800, Boqun Feng wrote:
> > > According to
When perf detects data file has index table, process header part first
and then rest data files in a row. Note that the indexed sample data is
recorded for each cpu/thread separately, it's already ordered with
respect to themselves so no need to use the ordered event queue
interface.
Signed-off-b
The dummy tracking event is only for tracking task/comom/mmap events
and has no sample data for itself. So no need to report, just skip it.
Signed-off-by: Namhyung Kim
---
tools/perf/builtin-report.c| 3 +++
tools/perf/ui/browsers/hists.c | 30 --
tools/perf/ui/
Hello,
Commit b0a688ddcc50 "usb: musb: cppi41: allow it to work again" seems
to fix a regression. It applies cleanly on v4.1 and removes the
"musb-hdrc musb-hdrc.1.auto: Need DT for the DMA engine." error.
Any chance you can queue it for -stable?
Thanks!
--
Ezequiel García, VanguardiaSur
www.va
Now thread->comm can be handled with time properly, use it to find
the correct comm at the time when adding hist entries.
Cc: Frederic Weisbecker
Signed-off-by: Namhyung Kim
---
tools/perf/builtin-annotate.c | 5 +++--
tools/perf/builtin-diff.c | 8
tools/perf/tests/hists_link.c
With data file indexing is enabled, it needs to search thread based on
sample time since sample processing is done after other (task, comm and
mmap) events are processed. This can be a problem if a session is very
long and pid is recycled - in that case it'll only see the last one.
So keep thread
Hi all,
There will be no linux-next release on Monday.
Changes since 20151001:
I used the h8300 tree from next-20150828 since the current tree has been
rebased onto linux-next again :-(
The battery tree still had its build failure so I used the version from
next-20150925.
The target-updates
To support multi-threaded perf report, we need to maintain time-sorted
map groups. Add ->mg_list member to struct thread and sort the list
by time. Now leader threads have one more refcnt for map groups in
the list so also update the thread-mg-share test case.
Currently only add a new map groups
Find correct thread/map/symbol using proper functions.
Cc: Frederic Weisbecker
Signed-off-by: Namhyung Kim
---
tools/perf/util/machine.c | 25 -
tools/perf/util/unwind-libdw.c | 12 +++-
tools/perf/util/unwind-libunwind.c | 27 ++-
On Fri, Oct 2, 2015 at 4:14 AM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Oct 01, 2015 at 11:33:48PM +0800, Chen-Yu Tsai wrote:
>> The device tree node name is typically "interrupt-controller", which is
>> rather useless when used in printk messages and irq chip names for
>> identification purposes.
The util/event.h includes util/build-id.h only for BUILD_ID_SIZE.
This is a problem when I include util/event.h from util/tool.h which
is also included by util/build-id.h since it now makes a circular
dependency resulting in incomplete type error.
Signed-off-by: Namhyung Kim
---
tools/perf/perf.
Use timestamp to find a corresponding map so that it can find a match
symbol eventually.
Cc: Stephane Eranian
Signed-off-by: Namhyung Kim
---
tools/perf/util/event.c | 81 ++--
tools/perf/util/thread.c | 8 +++--
2 files changed, 77 insertions(+), 1
Currently the address_space was kept in thread struct but it's more
appropriate to keep it in map_groups as it's maintained throughout
exec's with timestamps. Also we should not flush the address space
after exec since it still can be accessed when used with an indexed
data file.
Cc: Frederic Wei
It'll manage maps using timestamp so that it can find correct
map/symbol for sample at a certain time. With this API, it can
maintain overlapping maps in a map_groups.
Cc: Stephane Eranian
Signed-off-by: Namhyung Kim
---
tools/perf/util/map.c | 64 ++
It'll be used to support multiple maps on a same address like dlopen()
and/or JIT compile cases.
Cc: Stephane Eranian
Cc: Frederic Weisbecker
Signed-off-by: Namhyung Kim
---
tools/perf/util/dso.c | 2 +-
tools/perf/util/machine.c | 29 +
tools/perf/util
Pass stats structure so that it can point separate object when used in
multi-thread environment.
Signed-off-by: Namhyung Kim
---
tools/perf/util/session.c | 71 ++-
1 file changed, 45 insertions(+), 26 deletions(-)
diff --git a/tools/perf/util/session
This is a preparation for perf report multi-thread support. When
multi-thread is enable, each thread will have its own hists during the
sample processing.
Signed-off-by: Namhyung Kim
---
tools/perf/builtin-report.c | 1 +
tools/perf/builtin-top.c | 1 +
tools/perf/tests/hists_c
The util/event.h includes util/build-id.h only for BUILD_ID_SIZE.
This is a problem when I include util/event.h from util/tool.h which
is also included by util/build-id.h since it now makes a circular
dependency resulting in incomplete type error.
Signed-off-by: Namhyung Kim
---
tools/perf/perf.
>> +
>> + - compatible : should be one of the following:
>> +- "allwinner,sun4i-a10-spdif": for the Allwinner A10 SoC
>> +- "allwinner,sun7i-a20-spdif": for the Allwinner A20 SoC
>> +- "allwinner,sun6i-a31-spdif": for the Allwinner A31 SoC
>
> Are all these compatibles re
A test case for verifying live and dead thread tree management during
time change and new machine__find{,new}_thread_time().
Cc: Frederic Weisbecker
Signed-off-by: Namhyung Kim
---
tools/perf/tests/Build| 1 +
tools/perf/tests/builtin-test.c | 4 +
tools/perf/tests/tes
A test case for verifying thread->mg and ->mg_list handling during
time change and new thread__find_addr_map_by_time() and friends.
Cc: Frederic Weisbecker
Signed-off-by: Namhyung Kim
---
tools/perf/tests/Build| 1 +
tools/perf/tests/builtin-test.c | 4 ++
tools/perf/tests/tests
The new test case checks various thread comm handling APIs like
overridding and time sorting.
Cc: Frederic Weisbecker
Signed-off-by: Namhyung Kim
---
tools/perf/tests/Build | 1 +
tools/perf/tests/builtin-test.c | 4
tools/perf/tests/tests.h| 1 +
tools/perf/tests/threa
The perf_evlist__mmap_ex function creates data and auxtrace mmaps and
optionally tracking mmaps for events now. It'll be used for perf
record to save events in a separate files and build an index table.
Checking dummy tracking event in perf_evlist__mmap() alone is not
enough as users can specify a
These new functions are for find appropriate map (and symbol) at the
given time when used with an indexed data file. This is based on the
fact that map_groups list is sorted by time in the previous patch.
Cc: Frederic Weisbecker
Signed-off-by: Namhyung Kim
---
tools/perf/util/event.c | 59 ++
When data file indexing is enabled, it processes all task, comm and mmap
events first and then goes to the sample events. So all it sees is the
last comm of a thread although it has information at the time of sample.
Sort thread's comm by time so that it can find appropriate comm at the
sample ti
Currently perf maintains dead threads in a linked list but this can be
a problem if someone needs to search from it especially in a large
session which might have many dead threads. Convert it to a rbtree
like normal threads and it'll be used later with multi-thread changes.
The list node is now
This tests new map_groups__{insert,find}_by_time() API working
correctly by using 3 * 100 maps.
Cc: Stephane Eranian
Signed-off-by: Namhyung Kim
---
tools/perf/tests/Build | 1 +
tools/perf/tests/builtin-test.c| 4 ++
tools/perf/tests/tests.h | 1 +
tools/perf/tests
The new --index option will create indexed data file which can be
processed by multiple threads parallelly. It saves meta event and
sample data in separate files and merges them with an index table.
If there's an index table in the data file, the HEADER_DATA_INDEX
feature bit is set and session->
The HEADER_DATA_INDEX feature is to record index table for sample data
so that they can be processed by multiple thread concurrently. Each
item is a struct perf_file_section which consists of an offset and size.
Signed-off-by: Namhyung Kim
---
tools/perf/builtin-record.c | 2 ++
tools/perf/uti
Add APIs for software dummy event to track task/comm/mmap events
separately. The perf record will use them to save such events in a
separate mmap buffer to make it easy to index. This is a preparation of
multi-thread support which will come later.
Cc: Adrian Hunter
Signed-off-by: Namhyung Kim
Pass struct perf_mmap to mmap handling functions directly. This will
be used by both of normal mmap and track mmap later.
Signed-off-by: Namhyung Kim
---
tools/perf/util/evlist.c | 24 +++-
tools/perf/util/evlist.h | 1 +
2 files changed, 16 insertions(+), 9 deletions(-)
d
Hello,
This patchset converts perf report to use multiple threads in order to
speed up the processing on large data files. I can see a minimum ~30%
of speedup with this change. The code is still experimental and
contains many rough edges. But I'd like to share and give some
feedbacks.
* chang
On Thu, Oct 01, 2015 at 11:21:22AM +0200, Greg Kroah-Hartman wrote:
> This is the start of the stable review cycle for the 4.2.3 release.
> There are 30 patches in this series, all will be posted as a response
> to this one. If anyone has any issues with these being applied, please
> let me know.
Hi Lars,
[auto build test results on v4.3-rc3 -- if it's inappropriate base, please
ignore]
config: arm-rpc_defconfig (attached as .config)
reproduce:
wget
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
-O ~/bin/make.cross
chmod +x ~/bin/ma
On Wed, Aug 19, 2015 at 7:52 PM, Lee Jones wrote:
> +
> +#define MBOX_BASE(mdev, inst) ((mdev)->base + (inst * 4))
>
It should be(inst) * 4
> +/**
> + * STi Mailbox device data
> + *
> + * An IP Mailbox is currently composed of 4 instances
> + * Each instance is currently composed of
On Thu, Oct 01, 2015 at 11:45:23PM +0200, Thomas Gleixner wrote:
> On Thu, 1 Oct 2015, Thomas Gleixner wrote:
> > On Thu, 1 Oct 2015, Mika Westerberg wrote:
> > > Now if I plug/unplug the card I may get few interrupts to CPU0 but rest
> > > of the interrupts never happen. Probably because IO-APIC f
Mathieu Poirier writes:
> On 30 September 2015 at 02:52, Alexander Shishkin
> wrote:
>> Mathieu Poirier writes:
>>
>>> This patchset aims to integrate configuration and control of
>>> the Coresight tracers with the perf sub-system.
>>>
>>> The goal is to use PMUs to represent tracers and the au
With unsigned values underflow in loops can occur resulting in
theoretically infinite loops.
The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1].
[1]: http://permalink.gmane.org/gmane.linux.kernel/2038576
Signed-off-by: Andrzej
Mathieu Poirier writes:
> On 30 September 2015 at 05:50, Alexander Shishkin
> wrote:
>> Mathieu Poirier writes:
>>
>>> +static void *etm_setup_aux(int cpu, void **pages,
>>> + int nr_pages, bool overwrite)
>>> +{
>>> + struct coresight_device *csdev;
>>> +
>>> +
Mathieu Poirier writes:
> On 30 September 2015 at 05:33, Alexander Shishkin
> wrote:
>> Mathieu Poirier writes:
>>
>>> Calling function 'smp_call_function_single()' to unlock the
>>> tracer and calling it right after to perform the default
>>> initialisation doesn't make sense.
>>>
>>> Moving '
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada
Acked-by: Rob Herring
---
.../bindings/arm/uniphier/cache-uniphier.txt | 60
Hi Olof,
Now Linux 4.3-rc1 is out, so I am back to this.
1/3: add outer cache support
2/3: rework SMP operations
3/3: add device tree nodes
Because 2/3 highly depends on 1/3, I hope whole of this series
is applied through ARM-SOC tree.
Changes in v5:
- Add __init to __uniphier_cache_set_lock
Add L2 cache controller nodes for all the UniPhier SoC DTSI.
Also, add an L3 cache controller node for PH1-Pro5 DTSI.
Signed-off-by: Masahiro Yamada
---
arch/arm/boot/dts/uniphier-ph1-ld4.dtsi | 13 +
arch/arm/boot/dts/uniphier-ph1-pro4.dtsi| 14 ++
arch/arm/boot
The complexity of the boot sequence of UniPhier SoC family is
a PITA due to the following hardware limitations:
[1] No dedicated on-chip SRAM
SoCs in general have small SRAM, on which a tiny firmware or a boot
loader can run before SDRAM is initialized. As UniPhier SoCs do not
have any dedicated
Mathieu Poirier writes:
> On 30 September 2015 at 03:58, Alexander Shishkin
> wrote:
>> Most of these things can also be bypassed, as at least initially perf
>> events won't be using trigger/sequencer configurations, so we could
>> simply clear all these things out when a first perf event is cre
2015-09-30 20:01 GMT+09:00 Masahiro Yamada :
> Hi Olof,
>
> Now Linux 4.3-rc1 is out, so I am back to this.
>
> 1/3: add outer cache support
> 2/3: rework SMP operations
> 3/3: add device tree nodes
>
> Because 2/3 highly depends on 1/3, I hope whole of this series
> is applied through ARM-SOC tree
Hi Andrew,
Today's linux-next merge of the akpm-current tree got conflicts in:
Documentation/filesystems/proc.txt
fs/proc/array.c
fs/proc/base.c
between commit:
b2f73922d119 ("fs/proc, core/debug: Don't expose absolute kernel addresses
via wchan")
from the tip tree and commit:
f01d
Hi Linus,
On Fri, 25 Sep 2015 13:34:10 +1000 Stephen Rothwell
wrote:
>
> After merging the pinctrl tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> drivers/pinctrl/pinctrl-at91-pio4.c: In function 'atmel_gpio_irq_set_type':
> drivers/pinctrl/pinctrl-at91-pio4.c:17
Hi Nicholas,
Today's linux-next merge of the target-updates tree got a conflict in:
samples/Makefile
between commit:
2d41f8138508 ("kdbus: add walk-through user space example")
from the kdbus tree and commit:
f71933438300 ("configfs: remove old API")
from the target-updates tree.
I fi
On Thu, Sep 24, 2015 at 12:10:34PM +0300, igal.liber...@freescale.com wrote:
> +int fman_get_rx_extra_headroom(void)
> +{
> + static bool fm_check_rx_extra_headroom;
> +
> + if (!fm_check_rx_extra_headroom) {
> + if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX ||
> +
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