Em Fri, Jul 01, 2016 at 05:04:10PM +0900, Masami Hiramatsu escreveu:
> From: Masami Hiramatsu
>
> perf buildid-cache --add scans given binary and add
> the SDT events to probe cache. "sdt_" prefix is appended for
> all SDT providers to avoid event-name clash
Em Fri, Jul 01, 2016 at 05:04:10PM +0900, Masami Hiramatsu escreveu:
> From: Masami Hiramatsu
>
> perf buildid-cache --add scans given binary and add
> the SDT events to probe cache. "sdt_" prefix is appended for
> all SDT providers to avoid event-name clash with other pre-defined
> events. It
On 07/01/16 09:56, Pantelis Antoniou wrote:
> Hi Frank,
>
>> On Jul 1, 2016, at 19:31 , Frank Rowand wrote:
>>
>> On 07/01/16 03:59, Pantelis Antoniou wrote:
>>> Hi Frank,
>>>
>>> Comments inline.
>>>
On Jul 1, 2016, at 03:02 , Frank Rowand
On 07/01/16 09:56, Pantelis Antoniou wrote:
> Hi Frank,
>
>> On Jul 1, 2016, at 19:31 , Frank Rowand wrote:
>>
>> On 07/01/16 03:59, Pantelis Antoniou wrote:
>>> Hi Frank,
>>>
>>> Comments inline.
>>>
On Jul 1, 2016, at 03:02 , Frank Rowand wrote:
Hi All,
I've been
Em Fri, 01 Jul 2016 20:24:48 +0300
Jani Nikula escreveu:
> On Fri, 01 Jul 2016, Markus Heiser wrote:
> > Am 01.07.2016 um 14:58 schrieb Jonathan Corbet :
> >
> >> On Fri, 01 Jul 2016 13:44:17 +0300
> >> Jani Nikula
Em Fri, 01 Jul 2016 20:24:48 +0300
Jani Nikula escreveu:
> On Fri, 01 Jul 2016, Markus Heiser wrote:
> > Am 01.07.2016 um 14:58 schrieb Jonathan Corbet :
> >
> >> On Fri, 01 Jul 2016 13:44:17 +0300
> >> Jani Nikula wrote:
> >>
> >>> This is also one of the reasons why I so much want to
> yes, we do in fact see a POLLRDHUP from the FIN in this case and
> read of zero, but we still have more data to write to the socket, and
> b/c the RST is dropped here, the socket stays in TIME_WAIT until
> things eventually time out...
After the FIN when you send/retransmit your next segment do
> yes, we do in fact see a POLLRDHUP from the FIN in this case and
> read of zero, but we still have more data to write to the socket, and
> b/c the RST is dropped here, the socket stays in TIME_WAIT until
> things eventually time out...
After the FIN when you send/retransmit your next segment do
On Thu, Jun 30, 2016 at 1:54 PM, Radim Krčmář wrote:
> KVM_CAP_X2APIC_API can be enabled to extend APIC ID in get/set ioctl and MSI
> addresses to 32 bits. Both are needed to support x2APIC.
>
> The capability has to be toggleable and disabled by default, because get/set
>
On Thu, Jun 30, 2016 at 1:54 PM, Radim Krčmář wrote:
> KVM_CAP_X2APIC_API can be enabled to extend APIC ID in get/set ioctl and MSI
> addresses to 32 bits. Both are needed to support x2APIC.
>
> The capability has to be toggleable and disabled by default, because get/set
> ioctl shifted and
> From: Borislav Petkov [mailto:b...@suse.de]
> Sent: Friday, July 01, 2016 10:28 AM
> To: Luck, Tony
> Cc: Yu, Fenghua ; Thomas Gleixner
> ; Ingo Molnar ; Anvin, H Peter
> ; Peter Zijlstra
> From: Borislav Petkov [mailto:b...@suse.de]
> Sent: Friday, July 01, 2016 10:28 AM
> To: Luck, Tony
> Cc: Yu, Fenghua ; Thomas Gleixner
> ; Ingo Molnar ; Anvin, H Peter
> ; Peter Zijlstra ;
> Stephane Eranian ; Shankar, Ravi V
> ; Vikas Shivappa
> ; linux-kernel ker...@vger.kernel.org>; x86
>
> Basically all cache indices carry the APIC ID of the core, so L1D on
> CPU0 has ID 0 and then L1I has ID 0 too and then L2 has also the same
> ID.
>
> How does that look on a CAT system? Do all the different cache levels
> get different IDs?
For CAT we only need the IDs to be unique at each
On Fri, Jul 1, 2016 at 5:19 AM, Yakir Yang wrote:
> The PSR driver have exported four symbols for specific device driver:
> - rockchip_drm_psr_register()
> - rockchip_drm_psr_unregister()
> - rockchip_drm_psr_enable()
> - rockchip_drm_psr_disable()
> -
> Basically all cache indices carry the APIC ID of the core, so L1D on
> CPU0 has ID 0 and then L1I has ID 0 too and then L2 has also the same
> ID.
>
> How does that look on a CAT system? Do all the different cache levels
> get different IDs?
For CAT we only need the IDs to be unique at each
On Fri, Jul 1, 2016 at 5:19 AM, Yakir Yang wrote:
> The PSR driver have exported four symbols for specific device driver:
> - rockchip_drm_psr_register()
> - rockchip_drm_psr_unregister()
> - rockchip_drm_psr_enable()
> - rockchip_drm_psr_disable()
> - rockchip_drm_psr_flush()
>
> Encoder driver
On 07/01/2016 05:15 PM, Dmitry Vyukov wrote:
> On Fri, Jul 1, 2016 at 4:09 PM, Joonsoo Kim wrote:
>> 2016-07-01 23:03 GMT+09:00 Dmitry Vyukov :
+
+ if (obj_cache == cache)
+ qlist_put(to, qlink,
On 07/01/2016 05:15 PM, Dmitry Vyukov wrote:
> On Fri, Jul 1, 2016 at 4:09 PM, Joonsoo Kim wrote:
>> 2016-07-01 23:03 GMT+09:00 Dmitry Vyukov :
+
+ if (obj_cache == cache)
+ qlist_put(to, qlink, cache->size);
+ else
+
Am Donnerstag, 30 Juni 2016, 17:43:57 schrieb Dave Young:
> On 06/30/16 at 01:42pm, Thiago Jung Bauermann wrote:
> > Am Donnerstag, 30 Juni 2016, 12:49:44 schrieb Thiago Jung Bauermann:
> > > To be honest I think struct kexec_buf is an implementation detail
> > > inside
> > >
Am Donnerstag, 30 Juni 2016, 17:43:57 schrieb Dave Young:
> On 06/30/16 at 01:42pm, Thiago Jung Bauermann wrote:
> > Am Donnerstag, 30 Juni 2016, 12:49:44 schrieb Thiago Jung Bauermann:
> > > To be honest I think struct kexec_buf is an implementation detail
> > > inside
> > >
From: Sergio Valverde
The interrupt worker code for the enc28j60 relies only on the TXIF flag to
determinate if the packet transmission was completed. However the datasheet
specifies in section 12.1.3 that TXERIF will clear the TXRTS after a
transmit abort. Also in
From: Sergio Valverde
The interrupt worker code for the enc28j60 relies only on the TXIF flag to
determinate if the packet transmission was completed. However the datasheet
specifies in section 12.1.3 that TXERIF will clear the TXRTS after a
transmit abort. Also in section 12.1.4 that TXIF will
This is very lightly tested. I haven't even run it on the affected
hardware. Just sending it quickly in case someone can easily see
something fatally wrong with it.
This seems a lot less fragile than the previous patches that relied
on TLB flushing. Those seemed like it would be easy to add
The erratum we are fixing here can lead to stray setting of the
A and D bits. That means that a pte that we cleared might
suddenly have A/D set. So, stop considering those bits when
determining if a pte is pte_none(). The same goes for the
other pmd_none() and pud_none(). pgd_none() can be
This is very lightly tested. I haven't even run it on the affected
hardware. Just sending it quickly in case someone can easily see
something fatally wrong with it.
This seems a lot less fragile than the previous patches that relied
on TLB flushing. Those seemed like it would be easy to add
The erratum we are fixing here can lead to stray setting of the
A and D bits. That means that a pte that we cleared might
suddenly have A/D set. So, stop considering those bits when
determining if a pte is pte_none(). The same goes for the
other pmd_none() and pud_none(). pgd_none() can be
The Intel(R) Xeon Phi(TM) Processor x200 Family (codename: Knights
Landing) has an erratum where a processor thread setting the Accessed
or Dirty bits may not do so atomically against its checks for the
Present bit. This may cause a thread (which is about to page fault)
to set A and/or D, even
This erratum can result in Accessed/Dirty getting set by the hardware
when we do not expect them to be (on !Present PTEs).
Instead of trying to fix them up after this happens, we just
allow the bits to get set and try to ignore them. We do this by
shifting the layout of the bits we use for swap
The Intel(R) Xeon Phi(TM) Processor x200 Family (codename: Knights
Landing) has an erratum where a processor thread setting the Accessed
or Dirty bits may not do so atomically against its checks for the
Present bit. This may cause a thread (which is about to page fault)
to set A and/or D, even
This erratum can result in Accessed/Dirty getting set by the hardware
when we do not expect them to be (on !Present PTEs).
Instead of trying to fix them up after this happens, we just
allow the bits to get set and try to ignore them. We do this by
shifting the layout of the bits we use for swap
The page table manipulation code seems to have grown a couple of
sites that are looking for empty PTEs. Just in case one of these
entries got a stray bit set, use pte_none() instead of checking
for a zero pte_val().
The use pte_same() makes me a bit nervous. If we were doing a
pte_same() check
The page table manipulation code seems to have grown a couple of
sites that are looking for empty PTEs. Just in case one of these
entries got a stray bit set, use pte_none() instead of checking
for a zero pte_val().
The use pte_same() makes me a bit nervous. If we were doing a
pte_same() check
Hi,
On Thu, Jun 30, 2016 at 3:21 PM, Brian Norris wrote:
> The PCIe driver didn't mask the host interrupts before trying to tear
> down. This causes lockups at reboot or rmmod when using MSI-X on 8997,
> since the MSI handler gets confused and locks up the system.
>
>
Hi,
On Thu, Jun 30, 2016 at 3:21 PM, Brian Norris wrote:
> The PCIe driver didn't mask the host interrupts before trying to tear
> down. This causes lockups at reboot or rmmod when using MSI-X on 8997,
> since the MSI handler gets confused and locks up the system.
>
> Also tested on 8897, which
I've hit a GPF in depot_fetch_stack when it was given
bogus stack handle. I think it was caused by a distant
out-of-bounds that hit a different object, as the result
we treated uninit garbage as stack handle. Maybe there is
something to fix in KASAN logic, but I think it makes
sense to make
I've hit a GPF in depot_fetch_stack when it was given
bogus stack handle. I think it was caused by a distant
out-of-bounds that hit a different object, as the result
we treated uninit garbage as stack handle. Maybe there is
something to fix in KASAN logic, but I think it makes
sense to make
On Fri, Jul 01, 2016 at 12:00:50PM +0200, Jan Kara wrote:
> Hello,
>
> On Thu 30-06-16 14:18:14, Nikolay Borisov wrote:
> > In light of the discussion in https://patchwork.kernel.org/patch/9187411/
> > and
> > the discussion at
> > https://groups.google.com/forum/#!topic/syzkaller/XvxH3cBQ134
On Fri, Jul 01, 2016 at 12:00:50PM +0200, Jan Kara wrote:
> Hello,
>
> On Thu 30-06-16 14:18:14, Nikolay Borisov wrote:
> > In light of the discussion in https://patchwork.kernel.org/patch/9187411/
> > and
> > the discussion at
> > https://groups.google.com/forum/#!topic/syzkaller/XvxH3cBQ134
From: Markus Elfring
Adjust jump targets according to the Linux coding style convention.
Another check for the variable "status" can be omitted then at the end.
Signed-off-by: Markus Elfring
---
v4: Further feedback was integrated
Thanks for the quick reply Tejun, really appreciate it.
On 01-07-16, 12:22, Tejun Heo wrote:
> Hello, Viresh.
>
> On Fri, Jul 01, 2016 at 09:59:59AM -0700, Viresh Kumar wrote:
> > The system watchdog uses a delayed-work (1 second) for petting the
> > watchdog (resetting its counter) and if the
From: Markus Elfring
Adjust jump targets according to the Linux coding style convention.
Another check for the variable "status" can be omitted then at the end.
Signed-off-by: Markus Elfring
---
v4: Further feedback was integrated into this message.
v3: Deletion of another blank line
v2:
Thanks for the quick reply Tejun, really appreciate it.
On 01-07-16, 12:22, Tejun Heo wrote:
> Hello, Viresh.
>
> On Fri, Jul 01, 2016 at 09:59:59AM -0700, Viresh Kumar wrote:
> > The system watchdog uses a delayed-work (1 second) for petting the
> > watchdog (resetting its counter) and if the
On Fri 01 Jul 08:52 PDT 2016, Linus Walleij wrote:
> Add support to mux in the second external bus interface as
> function 1 on pins 123 thru 158. This external bus is used on
> the APQ8060 Dragonboard to connect an external SMSC9211 ethernet
> adapter.
>
> Cc: Stephen Boyd
On Fri 01 Jul 08:52 PDT 2016, Linus Walleij wrote:
> Add support to mux in the second external bus interface as
> function 1 on pins 123 thru 158. This external bus is used on
> the APQ8060 Dragonboard to connect an external SMSC9211 ethernet
> adapter.
>
> Cc: Stephen Boyd
> Cc: Bjorn
On 06/30/2016 05:42 PM, Florian Fainelli wrote:
> SUN_TOP_CTRL_FAMILY_ID is at a fixed absolute address for all of our supported
> chips, so utilize its value to determine what the UARTA base address should
> be.
>
> Since the code is called both during decompressor when the MMU is off, and
>
On Fri, 01 Jul 2016, Markus Mayer wrote:
> On 1 July 2016 at 03:52, Jani Nikula wrote:
>> On Fri, 01 Jul 2016, Markus Mayer wrote:
>>> Add a function called strtolower() to convert strings to lower case
>>> in-place,
On 06/30/2016 05:42 PM, Florian Fainelli wrote:
> SUN_TOP_CTRL_FAMILY_ID is at a fixed absolute address for all of our supported
> chips, so utilize its value to determine what the UARTA base address should
> be.
>
> Since the code is called both during decompressor when the MMU is off, and
>
On Fri, 01 Jul 2016, Markus Mayer wrote:
> On 1 July 2016 at 03:52, Jani Nikula wrote:
>> On Fri, 01 Jul 2016, Markus Mayer wrote:
>>> Add a function called strtolower() to convert strings to lower case
>>> in-place, overwriting the original string.
>>>
>>> This seems to be a recurring
On 07/01/2016 05:37 PM, Arnd Bergmann wrote:
> On Friday, July 1, 2016 5:22:32 PM CEST Hans Verkuil wrote:
>>> diff --git a/drivers/media/platform/vivid/Kconfig
>>> b/drivers/media/platform/vivid/Kconfig
>>> index 8e6918c5c87c..8e31146d079a 100644
>>> --- a/drivers/media/platform/vivid/Kconfig
On 07/01/2016 05:37 PM, Arnd Bergmann wrote:
> On Friday, July 1, 2016 5:22:32 PM CEST Hans Verkuil wrote:
>>> diff --git a/drivers/media/platform/vivid/Kconfig
>>> b/drivers/media/platform/vivid/Kconfig
>>> index 8e6918c5c87c..8e31146d079a 100644
>>> --- a/drivers/media/platform/vivid/Kconfig
On Fri, Jul 01, 2016 at 09:50:41AM -0700, Luck, Tony wrote:
> Here's the situation. We have lots of (mostly) independent caches on a
> system.
> The L3 cache (also called LLC - Last Level Cache - in some documentation) is
> usually shared by all cpus on a physical socket. The L1 and L2 caches
On Fri, Jul 01, 2016 at 09:50:41AM -0700, Luck, Tony wrote:
> Here's the situation. We have lots of (mostly) independent caches on a
> system.
> The L3 cache (also called LLC - Last Level Cache - in some documentation) is
> usually shared by all cpus on a physical socket. The L1 and L2 caches
On 07/01/2016 11:54 AM, Stuart Yoder wrote:
Re-opening a thread from back in early 2015...
-Original Message-
From: Jon Masters
Date: Wed, Jan 14, 2015 at 11:18 AM
Subject: Re: sysfs topology for arm64 cluster_id
To: Mark Rutland
Cc:
On 07/01/2016 11:54 AM, Stuart Yoder wrote:
Re-opening a thread from back in early 2015...
-Original Message-
From: Jon Masters
Date: Wed, Jan 14, 2015 at 11:18 AM
Subject: Re: sysfs topology for arm64 cluster_id
To: Mark Rutland
Cc: "linux-arm-ker...@lists.infradead.org"
,
On Fri, 01 Jul 2016, Markus Heiser wrote:
> Am 01.07.2016 um 14:58 schrieb Jonathan Corbet :
>
>> On Fri, 01 Jul 2016 13:44:17 +0300
>> Jani Nikula wrote:
>>
>>> This is also one of the reasons why I so much want to keep
On Fri, 01 Jul 2016, Markus Heiser wrote:
> Am 01.07.2016 um 14:58 schrieb Jonathan Corbet :
>
>> On Fri, 01 Jul 2016 13:44:17 +0300
>> Jani Nikula wrote:
>>
>>> This is also one of the reasons why I so much want to keep everything
>>> behind one configuration file, and build everything in the
Hello Caesar,
On Fri, Jul 1, 2016 at 12:32 AM, Caesar Wang wrote:
> From: Elaine Zhang
>
> In order to meet low power requirements, a power management unit (PMU) is
> designed for controlling power resources in RK3399. The RK3399 PMU is
> dedicated
Hello, Viresh.
On Fri, Jul 01, 2016 at 09:59:59AM -0700, Viresh Kumar wrote:
> The system watchdog uses a delayed-work (1 second) for petting the
> watchdog (resetting its counter) and if the work doesn't reset the
> counters in time (another 1 second), the watchdog resets the system.
>
>
Hello, Viresh.
On Fri, Jul 01, 2016 at 09:59:59AM -0700, Viresh Kumar wrote:
> The system watchdog uses a delayed-work (1 second) for petting the
> watchdog (resetting its counter) and if the work doesn't reset the
> counters in time (another 1 second), the watchdog resets the system.
>
>
Hello Caesar,
On Fri, Jul 1, 2016 at 12:32 AM, Caesar Wang wrote:
> From: Elaine Zhang
>
> In order to meet low power requirements, a power management unit (PMU) is
> designed for controlling power resources in RK3399. The RK3399 PMU is
> dedicated for managing the power of the whole chip.
>
>
On 07/01/16 09:44, Frank Rowand wrote:
> On 06/30/16 17:02, Frank Rowand wrote:
>> Hi All,
>>
>> I've been trying to wrap my head around what Pantelis and Rob have written
>> on the subject of a device tree representation of a connector for a
>> daughter board to connect to (eg a cape or a shield)
On 07/01/16 09:44, Frank Rowand wrote:
> On 06/30/16 17:02, Frank Rowand wrote:
>> Hi All,
>>
>> I've been trying to wrap my head around what Pantelis and Rob have written
>> on the subject of a device tree representation of a connector for a
>> daughter board to connect to (eg a cape or a shield)
Am Freitag, 1. Juli 2016, 09:56:31 schrieb Doug Anderson:
> Caesar
>
> On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang wrote:
> > From: Elaine Zhang
> >
> > In order to meet low power requirements, a power management unit (PMU)
> > is
> > designed
Am Freitag, 1. Juli 2016, 09:56:31 schrieb Doug Anderson:
> Caesar
>
> On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang wrote:
> > From: Elaine Zhang
> >
> > In order to meet low power requirements, a power management unit (PMU)
> > is
> > designed for controlling power resources in RK3399. The
On 07/01/2016 01:08 PM, Rick Jones wrote:
> On 07/01/2016 08:10 AM, Jason Baron wrote:
>> I'm wondering if anybody else has run into this...
>>
>> On Mac OSX 10.11.5 (latest version), we have found that when tcp
>> connections are abruptly terminated (via ^C), a FIN is sent followed
>> by an RST
On 07/01/2016 01:08 PM, Rick Jones wrote:
> On 07/01/2016 08:10 AM, Jason Baron wrote:
>> I'm wondering if anybody else has run into this...
>>
>> On Mac OSX 10.11.5 (latest version), we have found that when tcp
>> connections are abruptly terminated (via ^C), a FIN is sent followed
>> by an RST
On Fri, Jul 01, 2016 at 10:05:50AM -0700, Doug Anderson wrote:
> I'm curious why you you need a timer at all. Can't you just keep
> track of the jiffies that you last sent and do subtraction? ...or you
> could get even more accurate and use a ktime_t. That avoids a whole
> lot of
On Fri, Jul 01, 2016 at 10:05:50AM -0700, Doug Anderson wrote:
> I'm curious why you you need a timer at all. Can't you just keep
> track of the jiffies that you last sent and do subtraction? ...or you
> could get even more accurate and use a ktime_t. That avoids a whole
> lot of
On 07/01/2016 08:10 AM, Jason Baron wrote:
I'm wondering if anybody else has run into this...
On Mac OSX 10.11.5 (latest version), we have found that when tcp
connections are abruptly terminated (via ^C), a FIN is sent followed
by an RST packet.
That just seems, well, silly. If the client
On 07/01/2016 08:10 AM, Jason Baron wrote:
I'm wondering if anybody else has run into this...
On Mac OSX 10.11.5 (latest version), we have found that when tcp
connections are abruptly terminated (via ^C), a FIN is sent followed
by an RST packet.
That just seems, well, silly. If the client
On 1 July 2016 at 03:52, Jani Nikula wrote:
> On Fri, 01 Jul 2016, Markus Mayer wrote:
>> Add a function called strtolower() to convert strings to lower case
>> in-place, overwriting the original string.
>>
>> This seems to be a recurring
On 1 July 2016 at 03:52, Jani Nikula wrote:
> On Fri, 01 Jul 2016, Markus Mayer wrote:
>> Add a function called strtolower() to convert strings to lower case
>> in-place, overwriting the original string.
>>
>> This seems to be a recurring requirement in the kernel that is
>> currently being
Hello. I'm posting here because someone asked (a long time ago) for a
driver or app that would drive a little usb gadget (mini vga display)
called the screenDUO that comes with Asus motherboards. I recently put
a bunch of work into it (multiline support, color text, pixel drawing,
etc.) And
Hello. I'm posting here because someone asked (a long time ago) for a
driver or app that would drive a little usb gadget (mini vga display)
called the screenDUO that comes with Asus motherboards. I recently put
a bunch of work into it (multiline support, color text, pixel drawing,
etc.) And
Hi,
On Fri, Jul 1, 2016 at 1:21 AM, Mark Brown wrote:
> On Thu, Jun 30, 2016 at 09:23:26PM -0700, Doug Anderson wrote:
>
>> Also, something doesn't seem terribly robust about this, buy maybe I'm
>> being paranoid. If something happens where the timer hasn't fired
>> quickly
Hi Frank,
> On Jul 1, 2016, at 19:31 , Frank Rowand wrote:
>
> On 07/01/16 03:59, Pantelis Antoniou wrote:
>> Hi Frank,
>>
>> Comments inline.
>>
>>> On Jul 1, 2016, at 03:02 , Frank Rowand wrote:
>>>
>>> Hi All,
>>>
>>> I've been trying to
Hi,
On Fri, Jul 1, 2016 at 1:21 AM, Mark Brown wrote:
> On Thu, Jun 30, 2016 at 09:23:26PM -0700, Doug Anderson wrote:
>
>> Also, something doesn't seem terribly robust about this, buy maybe I'm
>> being paranoid. If something happens where the timer hasn't fired
>> quickly enough then you
Hi Frank,
> On Jul 1, 2016, at 19:31 , Frank Rowand wrote:
>
> On 07/01/16 03:59, Pantelis Antoniou wrote:
>> Hi Frank,
>>
>> Comments inline.
>>
>>> On Jul 1, 2016, at 03:02 , Frank Rowand wrote:
>>>
>>> Hi All,
>>>
>>> I've been trying to wrap my head around what Pantelis and Rob have
Caesar
On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang wrote:
> From: Elaine Zhang
>
> In order to meet low power requirements, a power management unit (PMU) is
> designed for controlling power resources in RK3399. The RK3399 PMU is
> dedicated for
Caesar
On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang wrote:
> From: Elaine Zhang
>
> In order to meet low power requirements, a power management unit (PMU) is
> designed for controlling power resources in RK3399. The RK3399 PMU is
> dedicated for managing the power of the whole chip.
>
> 1. add
Hi Tejun,
we are stuck with a typical issue on our octa-core ARM platform and
wanted to make sure that we aren't abusing the workqueue API by using
it for the wrong usecase.
Setup:
The system watchdog uses a delayed-work (1 second) for petting the
watchdog (resetting its counter) and if the
Hi Tejun,
we are stuck with a typical issue on our octa-core ARM platform and
wanted to make sure that we aren't abusing the workqueue API by using
it for the wrong usecase.
Setup:
The system watchdog uses a delayed-work (1 second) for petting the
watchdog (resetting its counter) and if the
On Thu, 30 Jun 2016, Manfred Spraul wrote:
On 06/28/2016 07:27 AM, Davidlohr Bueso wrote:
If I understand it right, it means that spin_lock() is both an acquire
and a release - for qspinlocks.
I wouldn't say that: the _Q_LOCKED_VAL stores are still unordered inside
the acquire region but
On Thu, 30 Jun 2016, Manfred Spraul wrote:
On 06/28/2016 07:27 AM, Davidlohr Bueso wrote:
If I understand it right, it means that spin_lock() is both an acquire
and a release - for qspinlocks.
I wouldn't say that: the _Q_LOCKED_VAL stores are still unordered inside
the acquire region but
On Fri, Jul 01, 2016 at 12:21:43PM +0200, Borislav Petkov wrote:
> On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> > From: Fenghua Yu
> >
> > Each cache node is described by cacheinfo and is a unique node across
>
> What is a cache node?
Clearly not a good
On Fri, Jul 01, 2016 at 12:21:43PM +0200, Borislav Petkov wrote:
> On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> > From: Fenghua Yu
> >
> > Each cache node is described by cacheinfo and is a unique node across
>
> What is a cache node?
Clearly not a good name for the concept we
On 16/06/2016 10:21, Paolo Bonzini wrote:
> This saves about 20 clock cycles per vmexit by avoiding a
> local_irq_save/restore pair. The price is that nested VMX will break
> with KVM hosts < 3.16, because the "acknowledge interrupt on exit"
> feature becomes mandatory. What do you think?
I'm
On 16/06/2016 10:21, Paolo Bonzini wrote:
> This saves about 20 clock cycles per vmexit by avoiding a
> local_irq_save/restore pair. The price is that nested VMX will break
> with KVM hosts < 3.16, because the "acknowledge interrupt on exit"
> feature becomes mandatory. What do you think?
I'm
On Fri, Jul 01, 2016 at 09:30:37AM -0700, Andy Lutomirski wrote:
> I put the ifdef there to prevent anyone from accidentally using it in
> a 64-bit code path, not to save a bit. We could put in the middle of
> the list to make the mistake much less likely to be repeated, I
> suppose.
Well, if
On Fri, Jul 01, 2016 at 09:30:37AM -0700, Andy Lutomirski wrote:
> I put the ifdef there to prevent anyone from accidentally using it in
> a 64-bit code path, not to save a bit. We could put in the middle of
> the list to make the mistake much less likely to be repeated, I
> suppose.
Well, if
On 06/30/16 17:02, Frank Rowand wrote:
> Hi All,
>
> I've been trying to wrap my head around what Pantelis and Rob have written
> on the subject of a device tree representation of a connector for a
> daughter board to connect to (eg a cape or a shield) and the representation
> of the daughter
On 06/30/16 17:02, Frank Rowand wrote:
> Hi All,
>
> I've been trying to wrap my head around what Pantelis and Rob have written
> on the subject of a device tree representation of a connector for a
> daughter board to connect to (eg a cape or a shield) and the representation
> of the daughter
On 01/07/2016 17:53, Radim Krčmář wrote:
>> >> enable_xapic()
>> >> id = apic_id()
>> >> set_apic_id(id+1) // ?
>> >> enable_x2apic()
>> >> id == apic_id() & 0xff
>> >> disable_apic()
>> >> enable_xapic()
>> >> id == apic_id()
>> >>
> >
> > Yes, plus checking that it "moves"
On 01/07/2016 17:53, Radim Krčmář wrote:
>> >> enable_xapic()
>> >> id = apic_id()
>> >> set_apic_id(id+1) // ?
>> >> enable_x2apic()
>> >> id == apic_id() & 0xff
>> >> disable_apic()
>> >> enable_xapic()
>> >> id == apic_id()
>> >>
> >
> > Yes, plus checking that it "moves"
On 01/07/2016 17:43, Radim Krčmář wrote:
> > Forgot to reply about this: letting SET_LAPIC change x2APIC IDs is nonsense.
> >
> > In x2APIC mode + new capability disabled SET_LAPIC should ignore the id
> > register altogether for backwards compatibility.
>
> I'd still shift SET_LAPIC APIC ID
On 01/07/2016 17:43, Radim Krčmář wrote:
> > Forgot to reply about this: letting SET_LAPIC change x2APIC IDs is nonsense.
> >
> > In x2APIC mode + new capability disabled SET_LAPIC should ignore the id
> > register altogether for backwards compatibility.
>
> I'd still shift SET_LAPIC APIC ID
On Jun 30, 2016 2:25 PM, "Dave Hansen" wrote:
>
> On 06/30/2016 10:36 AM, Andy Lutomirski wrote:
> >>> We make baseline_pkru a process-wide baseline and store it in
> >>> mm->context. That way, no matter which thread gets interrupted for a
> >>> signal, they see
On Jun 30, 2016 2:25 PM, "Dave Hansen" wrote:
>
> On 06/30/2016 10:36 AM, Andy Lutomirski wrote:
> >>> We make baseline_pkru a process-wide baseline and store it in
> >>> mm->context. That way, no matter which thread gets interrupted for a
> >>> signal, they see consistent values. We only write
On 07/01/16 03:59, Pantelis Antoniou wrote:
> Hi Frank,
>
> Comments inline.
>
>> On Jul 1, 2016, at 03:02 , Frank Rowand wrote:
>>
>> Hi All,
>>
>> I've been trying to wrap my head around what Pantelis and Rob have written
>> on the subject of a device tree
On 07/01/16 03:59, Pantelis Antoniou wrote:
> Hi Frank,
>
> Comments inline.
>
>> On Jul 1, 2016, at 03:02 , Frank Rowand wrote:
>>
>> Hi All,
>>
>> I've been trying to wrap my head around what Pantelis and Rob have written
>> on the subject of a device tree representation of a connector for a
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