[PATCH 05/10] perf sched timehist: Cleanup idle_max_cpu handling

It treats the idle_max_cpu little bit confusingly IMHO. Let's make it more straight forward. Signed-off-by: Namhyung Kim --- tools/perf/builtin-sched.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/tools/perf/builtin-sched.c

[PATCH 05/10] perf sched timehist: Cleanup idle_max_cpu handling

It treats the idle_max_cpu little bit confusingly IMHO. Let's make it more straight forward. Signed-off-by: Namhyung Kim --- tools/perf/builtin-sched.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index

[PATCHSET 00/10] perf sched timehist: Introduce --idle-hist option (v1)

Hi, This patchset implements the idle hist feature which analyze reason of system idle. Sometimes I need to investigate what makes CPUs to go idle even though I have jobs to do. It may be due to I/O, waiting on lock or whatever. To identify the reasons it only accounts events related to idle

[PATCH 01/10] perf sched: Cleanup option processing

The -D/--dump-raw-trace option is in the parent option so no need to repeat it. Also move -f/--force option to parent as it's common to handle data file. Signed-off-by: Namhyung Kim --- tools/perf/builtin-sched.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-)

[PATCH 03/10] perf sched timehist: Handle zero sample->tid properly

Sometimes samples have tid of 0 but non-0 pid. It ends up having a new thread of 0 tid/pid (instead of referring idle task) since tid is used to search matching task. But I guess it's wrong to use 0 as a tid when pid is set. This patch uses tid only if it has a non-zero value or same as pid (of

[PATCHSET 00/10] perf sched timehist: Introduce --idle-hist option (v1)

Hi, This patchset implements the idle hist feature which analyze reason of system idle. Sometimes I need to investigate what makes CPUs to go idle even though I have jobs to do. It may be due to I/O, waiting on lock or whatever. To identify the reasons it only accounts events related to idle

[PATCH 01/10] perf sched: Cleanup option processing

The -D/--dump-raw-trace option is in the parent option so no need to repeat it. Also move -f/--force option to parent as it's common to handle data file. Signed-off-by: Namhyung Kim --- tools/perf/builtin-sched.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git

[PATCH 03/10] perf sched timehist: Handle zero sample->tid properly

Sometimes samples have tid of 0 but non-0 pid. It ends up having a new thread of 0 tid/pid (instead of referring idle task) since tid is used to search matching task. But I guess it's wrong to use 0 as a tid when pid is set. This patch uses tid only if it has a non-zero value or same as pid (of

Re: [PATCH] sd: make ->no_write_same independent of reported ->max_ws_blocks

> "Nicolai" == Nicolai Stange writes: Nicolai, Nicolai> Due to reported problems with Write Same on ATA devices, commit Nicolai> 0ce1b18c42a5 ("libata: Some drives failing on SCT Write Same") Nicolai> strived to report non-support for Write Same on non-zoned ATA

Re: [PATCH] sd: make ->no_write_same independent of reported ->max_ws_blocks

> "Nicolai" == Nicolai Stange writes: Nicolai, Nicolai> Due to reported problems with Write Same on ATA devices, commit Nicolai> 0ce1b18c42a5 ("libata: Some drives failing on SCT Write Same") Nicolai> strived to report non-support for Write Same on non-zoned ATA Nicolai> devices. Nicolai>

[PATCH v1 4/4] scsi: ufs-qcom: fix bug with read/modify write of UFS_CFG1

ufs_qcom_print_hw_debug_reg_all() function is having a bug where it might incorrectly modify undesired bits in UFS_CFG1 register, this change fixes it. Reviewed-by: Venkat Gopalakrishnan Signed-off-by: Subhash Jadavani ---

[PATCH v1 4/4] scsi: ufs-qcom: fix bug with read/modify write of UFS_CFG1

ufs_qcom_print_hw_debug_reg_all() function is having a bug where it might incorrectly modify undesired bits in UFS_CFG1 register, this change fixes it. Reviewed-by: Venkat Gopalakrishnan Signed-off-by: Subhash Jadavani --- drivers/scsi/ufs/ufs-qcom.c | 3 ++- 1 file changed, 2 insertions(+), 1

[PATCH v1 2/4] scsi: ufs-qcom: add probe_defer in case phy driver not probed yet

From: Yaniv Gardi In case UFS driver is probed before the phy driver does, the UFS driver should return a PROBE_DEFER code. Signed-off-by: Yaniv Gardi Signed-off-by: Subhash Jadavani --- drivers/scsi/ufs/ufs-qcom.c | 11

[PATCH v1 3/4] scsi: ufs: add quirk to increase host PA_SaveConfigTime

The maximum value PA_SaveConfigTime is 250 (10us) but this is not enough for some vendors. Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime. Gear switch can be issued by host controller as an error recovery and any software delay will not help on this case so we need to

[PATCH v1 2/4] scsi: ufs-qcom: add probe_defer in case phy driver not probed yet

From: Yaniv Gardi In case UFS driver is probed before the phy driver does, the UFS driver should return a PROBE_DEFER code. Signed-off-by: Yaniv Gardi Signed-off-by: Subhash Jadavani --- drivers/scsi/ufs/ufs-qcom.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git

[PATCH v1 3/4] scsi: ufs: add quirk to increase host PA_SaveConfigTime

The maximum value PA_SaveConfigTime is 250 (10us) but this is not enough for some vendors. Gear switch from PWM to HS may fail even with this max. PA_SaveConfigTime. Gear switch can be issued by host controller as an error recovery and any software delay will not help on this case so we need to

[PATCH v1 1/4] scsi: ufs: add support for UFS HCI 2.1

From: Yaniv Gardi The UFS HCI v2.1 includes a few additional registers. This change updates the HCI register, the UFS version register content and the Interrupt Status register. Signed-off-by: Yaniv Gardi Signed-off-by: Subhash Jadavani

[PATCH v1 1/4] scsi: ufs: add support for UFS HCI 2.1

From: Yaniv Gardi The UFS HCI v2.1 includes a few additional registers. This change updates the HCI register, the UFS version register content and the Interrupt Status register. Signed-off-by: Yaniv Gardi Signed-off-by: Subhash Jadavani --- drivers/scsi/ufs/ufshcd.c | 29

[PATCH v3 3/4] pinctrl: aspeed-g5: Add mux configuration for all pins

The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and

[PATCH v3 4/4] pinctrl: aspeed: Fix kerneldoc return descriptions

Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 782c5c97f853..76f62bd45f02 100644

[PATCH v3 3/4] pinctrl: aspeed-g5: Add mux configuration for all pins

The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and

[PATCH v3 4/4] pinctrl: aspeed: Fix kerneldoc return descriptions

Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 782c5c97f853..76f62bd45f02 100644 ---

[PATCH v3 1/4] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these

[PATCH v3 2/4] pinctrl: aspeed-g4: Add mux configuration for all pins

The patch introducing the g4 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms. Now, update the bindings document to reflect the complete functionality and implement the necessary pin

[PATCH v3 1/4] pinctrl: aspeed: Read and write bits in LPC and GFX controllers

The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these

[PATCH v3 2/4] pinctrl: aspeed-g4: Add mux configuration for all pins

The patch introducing the g4 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms. Now, update the bindings document to reflect the complete functionality and implement the necessary pin

[PATCH v3 0/4] pinctrl: aspeed: Implement remaining pins

Hi all, This is v3 of the series implementing the remainder of the pinmux tables for the AST2400 and AST2500 SoCs. v2 of the series can be found here: https://lkml.org/lkml/2016/11/2/263 Cheers, Andrew Significant changes since v2: * The fix for touching bit SCU90[6] has been applied, so

[PATCH v3 0/4] pinctrl: aspeed: Implement remaining pins

Hi all, This is v3 of the series implementing the remainder of the pinmux tables for the AST2400 and AST2500 SoCs. v2 of the series can be found here: https://lkml.org/lkml/2016/11/2/263 Cheers, Andrew Significant changes since v2: * The fix for touching bit SCU90[6] has been applied, so

RE: [PATCH] pci-hyperv: use kmalloc to allocate hypercall params buffer

> -Original Message- > From: Stephen Hemminger [mailto:step...@networkplumber.org] > Sent: Monday, December 5, 2016 8:53 AM > To: Long Li > Cc: KY Srinivasan ; Haiyang Zhang > ; Bjorn Helgaas ; >

RE: [PATCH] pci-hyperv: use kmalloc to allocate hypercall params buffer

> -Original Message- > From: Stephen Hemminger [mailto:step...@networkplumber.org] > Sent: Monday, December 5, 2016 8:53 AM > To: Long Li > Cc: KY Srinivasan ; Haiyang Zhang > ; Bjorn Helgaas ; > de...@linuxdriverproject.org; linux-kernel@vger.kernel.org; linux- > p...@vger.kernel.org >

[PATCH] ipmi: bt-bmc: Use a regmap for register access

The registers for the bt-bmc device live under the Aspeed LPC controller. Devicetree bindings have recently been introduced for the LPC controller where the "host" portion of the LPC register space is described as a syscon device. Future devicetrees describing the bt-bmc device should nest its

[PATCH] ipmi: bt-bmc: Use a regmap for register access

The registers for the bt-bmc device live under the Aspeed LPC controller. Devicetree bindings have recently been introduced for the LPC controller where the "host" portion of the LPC register space is described as a syscon device. Future devicetrees describing the bt-bmc device should nest its

Re: [PATCH] virtio-net: Fix DMA-from-the-stack in virtnet_set_mac_address()

On Mon, Dec 05, 2016 at 06:10:58PM -0800, Andy Lutomirski wrote: > With CONFIG_VMAP_STACK=y, virtnet_set_mac_address() can be passed a > pointer to the stack and it will OOPS. Copy the address to the heap > to prevent the crash. > > Cc: Michael S. Tsirkin > Cc: Jason Wang

Re: [PATCH] virtio-net: Fix DMA-from-the-stack in virtnet_set_mac_address()

On Mon, Dec 05, 2016 at 06:10:58PM -0800, Andy Lutomirski wrote: > With CONFIG_VMAP_STACK=y, virtnet_set_mac_address() can be passed a > pointer to the stack and it will OOPS. Copy the address to the heap > to prevent the crash. > > Cc: Michael S. Tsirkin > Cc: Jason Wang > Cc: Laura Abbott >

[PATCH v3 0/6] mfd: dt: Add bindings for the Aspeed MFDs

Hi Lee, Here's a series describing the bindings for some MFDs in the Aspeed SoCs. I expect there will be discussion about how I've gone about this with adding a ranges property to the MFD bindings: The motivation here is to allow re-use of the standard regs property to describe resources used

[PATCH v3 6/6] mfd: dt: Move syscon bindings to syscon subdirectory

The use of syscons is growing, lets collate them in their own part of the bindings tree. Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/mfd/{ => syscon}/aspeed-scu.txt | 0 Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-gpbr.txt |

[PATCH v3 3/6] mfd: dt: Add Aspeed Low Pin Count Controller bindings

Signed-off-by: Andrew Jeffery --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 111 + 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt diff --git

[PATCH v3 5/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)

The Aspeed SoC Display Controller is presented as a syscon device to arbitrate access by display and pinmux drivers. Video pinmux configuration on fifth generation SoCs depends on bits in both the System Control Unit and the Display Controller. Signed-off-by: Andrew Jeffery

[PATCH v3 0/6] mfd: dt: Add bindings for the Aspeed MFDs

Hi Lee, Here's a series describing the bindings for some MFDs in the Aspeed SoCs. I expect there will be discussion about how I've gone about this with adding a ranges property to the MFD bindings: The motivation here is to allow re-use of the standard regs property to describe resources used

[PATCH v3 6/6] mfd: dt: Move syscon bindings to syscon subdirectory

The use of syscons is growing, lets collate them in their own part of the bindings tree. Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/mfd/{ => syscon}/aspeed-scu.txt | 0 Documentation/devicetree/bindings/mfd/{ => syscon}/atmel-gpbr.txt | 0

[PATCH v3 3/6] mfd: dt: Add Aspeed Low Pin Count Controller bindings

Signed-off-by: Andrew Jeffery --- .../devicetree/bindings/mfd/aspeed-lpc.txt | 111 + 1 file changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt

[PATCH v3 5/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)

The Aspeed SoC Display Controller is presented as a syscon device to arbitrate access by display and pinmux drivers. Video pinmux configuration on fifth generation SoCs depends on bits in both the System Control Unit and the Display Controller. Signed-off-by: Andrew Jeffery Acked-by: Rob Herring

[PATCH v3 1/6] mfd: dt: Fix "indicates" typo in mfd bindings document

Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/mfd/mfd.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/mfd.txt b/Documentation/devicetree/bindings/mfd/mfd.txt index af9d6931a1a2..f1fceeda12f1

[PATCH v3 1/6] mfd: dt: Fix "indicates" typo in mfd bindings document

Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/mfd/mfd.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/mfd.txt b/Documentation/devicetree/bindings/mfd/mfd.txt index af9d6931a1a2..f1fceeda12f1 100644 ---

[PATCH v3 2/6] mfd: dt: ranges, #address-cells and #size-cells as optional properties

Whilst describing a device and not a bus, simple-mfd is modelled on simple-bus where child nodes are iterated and registered as platform devices. Some complex devices, e.g. the Aspeed LPC controller, can benefit from address space mapping such that child nodes can use the regs property to describe

[PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux

[PATCH v3 2/6] mfd: dt: ranges, #address-cells and #size-cells as optional properties

Whilst describing a device and not a bus, simple-mfd is modelled on simple-bus where child nodes are iterated and registered as platform devices. Some complex devices, e.g. the Aspeed LPC controller, can benefit from address space mapping such that child nodes can use the regs property to describe

[PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)

The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux

Re: [PATCH 2/2] mm: page_alloc: High-order per-cpu page allocator v5

On Mon, Dec 05, 2016 at 09:57:39AM +, Mel Gorman wrote: > On Mon, Dec 05, 2016 at 12:06:19PM +0900, Joonsoo Kim wrote: > > On Fri, Dec 02, 2016 at 09:04:49AM +, Mel Gorman wrote: > > > On Fri, Dec 02, 2016 at 03:03:46PM +0900, Joonsoo Kim wrote: > > > > > @@ -1132,14 +1134,17 @@ static

Re: [PATCH 2/2] mm: page_alloc: High-order per-cpu page allocator v5

On Mon, Dec 05, 2016 at 09:57:39AM +, Mel Gorman wrote: > On Mon, Dec 05, 2016 at 12:06:19PM +0900, Joonsoo Kim wrote: > > On Fri, Dec 02, 2016 at 09:04:49AM +, Mel Gorman wrote: > > > On Fri, Dec 02, 2016 at 03:03:46PM +0900, Joonsoo Kim wrote: > > > > > @@ -1132,14 +1134,17 @@ static

[FIX][PATCH 02/10] ia64: Fix wrong start cputime assignment on task switch

On task switch we must initialize the current cputime of the next task using the value of the previous task which got freshly updated. But we are confusing that with doing the opposite, which should result in wrong cputime accounting. Cc: Benjamin Herrenschmidt Cc:

[FIX][PATCH 02/10] ia64: Fix wrong start cputime assignment on task switch

On task switch we must initialize the current cputime of the next task using the value of the previous task which got freshly updated. But we are confusing that with doing the opposite, which should result in wrong cputime accounting. Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael

[PATCH 05/10] powerpc: Prepare accounting structure for cputime flush on tick

In order to prepare for CONFIG_VIRT_CPU_ACCOUNTING_NATIVE to delay cputime accounting to the tick, provide finegrained accumulators to powerpc in order to store the cputime until flushing. While at it, normalize the name of several fields according to common cputime naming. Cc: Benjamin

[PATCH 05/10] powerpc: Prepare accounting structure for cputime flush on tick

In order to prepare for CONFIG_VIRT_CPU_ACCOUNTING_NATIVE to delay cputime accounting to the tick, provide finegrained accumulators to powerpc in order to store the cputime until flushing. While at it, normalize the name of several fields according to common cputime naming. Cc: Benjamin

[PATCH 09/10] s390/cputime: delayed accounting of system time

From: Martin Schwidefsky The account_system_time() function is called with a cputime that occurred while running in the kernel. The function detects which context the CPU is currently running in and accounts the time to the correct bucket. This forces the arch code to

[PATCH 10/10] vtime: Rename vtime_account_user() to vtime_flush()

CONFIG_VIRT_CPU_ACCOUNTING_NATIVE used to accumulate user time and account it on ticks and context switches only through the vtime_account_user() function. Now this model has been generalized on the 3 archs for all kind of cputime (system, irq, ...) and all the cputime flushing happens under

[PATCH 08/10] ia64: Accumulate cputime and account only on tick/task switch

Currently CONFIG_VIRT_CPU_ACCOUNTING_NATIVE accounts the cputime on any context boundary: irq entry/exit, guest entry/exit, context switch, etc... Calling functions such as account_system_time(), account_user_time() and such can be costly, especially if they are called on many fastpath such as

[PATCH 09/10] s390/cputime: delayed accounting of system time

From: Martin Schwidefsky The account_system_time() function is called with a cputime that occurred while running in the kernel. The function detects which context the CPU is currently running in and accounts the time to the correct bucket. This forces the arch code to account the cputime for

[PATCH 10/10] vtime: Rename vtime_account_user() to vtime_flush()

CONFIG_VIRT_CPU_ACCOUNTING_NATIVE used to accumulate user time and account it on ticks and context switches only through the vtime_account_user() function. Now this model has been generalized on the 3 archs for all kind of cputime (system, irq, ...) and all the cputime flushing happens under

[PATCH 08/10] ia64: Accumulate cputime and account only on tick/task switch

Currently CONFIG_VIRT_CPU_ACCOUNTING_NATIVE accounts the cputime on any context boundary: irq entry/exit, guest entry/exit, context switch, etc... Calling functions such as account_system_time(), account_user_time() and such can be costly, especially if they are called on many fastpath such as

[PATCH 04/10] cputime: Export account_guest_time

In order to prepare for CONFIG_VIRT_CPU_ACCOUNTING_NATIVE to delay cputime accounting to the tick, let's allow archs to account cputime directly to gtime. Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael Ellerman Cc:

[PATCH 07/10] powerpc/vtime: Accumulate cputime and account only on tick/task switch

Currently CONFIG_VIRT_CPU_ACCOUNTING_NATIVE accounts the cputime on any context boundary: irq entry/exit, guest entry/exit, context switch, etc... Calling functions such as account_system_time(), account_user_time() and such can be costly, especially if they are called on many fastpath such as

[PATCH 06/10] powerpc: Migrate stolen_time field to accounting structure

That in order to gather all cputime accumulation to the same place. Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael Ellerman Cc: Heiko Carstens Cc: Martin Schwidefsky

[PATCH 04/10] cputime: Export account_guest_time

In order to prepare for CONFIG_VIRT_CPU_ACCOUNTING_NATIVE to delay cputime accounting to the tick, let's allow archs to account cputime directly to gtime. Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael Ellerman Cc: Heiko Carstens Cc: Martin Schwidefsky Cc: Tony Luck Cc: Fenghua

[PATCH 07/10] powerpc/vtime: Accumulate cputime and account only on tick/task switch

Currently CONFIG_VIRT_CPU_ACCOUNTING_NATIVE accounts the cputime on any context boundary: irq entry/exit, guest entry/exit, context switch, etc... Calling functions such as account_system_time(), account_user_time() and such can be costly, especially if they are called on many fastpath such as

[PATCH 06/10] powerpc: Migrate stolen_time field to accounting structure

That in order to gather all cputime accumulation to the same place. Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael Ellerman Cc: Heiko Carstens Cc: Martin Schwidefsky Cc: Tony Luck Cc: Fenghua Yu Cc: Peter Zijlstra Cc: Rik van Riel Cc: Thomas Gleixner Cc: Ingo Molnar Cc:

[FIX][PATCH 01/10] powerpc32: Fix stale scaled stime on context switch

On context switch with powerpc32, the cputime is accumulated in the thread_info struct. So the switching-in task must move forward its start time snapshot to the current time in order to later compute the delta spent in system mode. This is what we do for the normal cputime by initializing the

[FIX][PATCH 01/10] powerpc32: Fix stale scaled stime on context switch

On context switch with powerpc32, the cputime is accumulated in the thread_info struct. So the switching-in task must move forward its start time snapshot to the current time in order to later compute the delta spent in system mode. This is what we do for the normal cputime by initializing the

[PATCH 00/10] vtime: Delay cputime accounting to tick

This follows up Martin Schwidefsky's patch which propose to delay cputime accounting to the tick in order to minimize the calls to account_system_time() and alikes as these functions can carry quite some overhead: http://lkml.kernel.org/r/2016112728.13a0a3db@mschwide The set includes

[PATCH 03/10] cputime: Allow accounting system time using cpustat index

In order to prepare for CONFIG_VIRT_CPU_ACCOUNTING_NATIVE to delay cputime accounting to the tick, let's provide APIs to account system time to precise contexts: hardirq, softirq, pure system, ... Inspired-by: Martin Schwidefsky Cc: Benjamin Herrenschmidt

[PATCH 00/10] vtime: Delay cputime accounting to tick

This follows up Martin Schwidefsky's patch which propose to delay cputime accounting to the tick in order to minimize the calls to account_system_time() and alikes as these functions can carry quite some overhead: http://lkml.kernel.org/r/2016112728.13a0a3db@mschwide The set includes

[PATCH 03/10] cputime: Allow accounting system time using cpustat index

In order to prepare for CONFIG_VIRT_CPU_ACCOUNTING_NATIVE to delay cputime accounting to the tick, let's provide APIs to account system time to precise contexts: hardirq, softirq, pure system, ... Inspired-by: Martin Schwidefsky Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: Michael

Re: [PATCH] virtio-net: Fix DMA-from-the-stack in virtnet_set_mac_address()

On 2016年12月06日 10:10, Andy Lutomirski wrote: With CONFIG_VMAP_STACK=y, virtnet_set_mac_address() can be passed a pointer to the stack and it will OOPS. Copy the address to the heap to prevent the crash. Cc: Michael S. Tsirkin Cc: Jason Wang Cc: Laura

Re: [PATCH] virtio-net: Fix DMA-from-the-stack in virtnet_set_mac_address()

On 2016年12月06日 10:10, Andy Lutomirski wrote: With CONFIG_VMAP_STACK=y, virtnet_set_mac_address() can be passed a pointer to the stack and it will OOPS. Copy the address to the heap to prevent the crash. Cc: Michael S. Tsirkin Cc: Jason Wang Cc: Laura Abbott Reported-by: zbys...@in.waw.pl

Re: [PATCH] SPCR: check bit width for the 16550 UART

Hi Duc, all, So after regenerating the initrd override (I must have fat fingered) it is now detecting the correct bit width on boot (attached dmesg log). HOWEVER while the console does come up, the use of "earlycon" on the command line (with no parameters) doesn't result in the early SPCR

Re: [PATCH] SPCR: check bit width for the 16550 UART

Hi Duc, all, So after regenerating the initrd override (I must have fat fingered) it is now detecting the correct bit width on boot (attached dmesg log). HOWEVER while the console does come up, the use of "earlycon" on the command line (with no parameters) doesn't result in the early SPCR

Re: [PATCH v9 00/12] Add Mediated device support

On 12/06/2016 01:44 AM, Gerd Hoffmann wrote: > Hi, > >> Just want to share that we have published a KVMGT implementation >> based on this v9 patchset, to: >> >> https://github.com/01org/gvt-linux/tree/gvt-next-kvmgt >> >> It doesn't utilize common routines introduced by 05+ patches yet. >>

Re: [PATCH v9 00/12] Add Mediated device support

On 12/06/2016 01:44 AM, Gerd Hoffmann wrote: > Hi, > >> Just want to share that we have published a KVMGT implementation >> based on this v9 patchset, to: >> >> https://github.com/01org/gvt-linux/tree/gvt-next-kvmgt >> >> It doesn't utilize common routines introduced by 05+ patches yet. >>

Re: [PATCHv13 0/3] rdmacg: IB/core: rdma controller support

ok. Thanks Tejun. Parav On Tue, Dec 6, 2016 at 1:05 AM, Tejun Heo wrote: > Parav, it's a bit too late for this cycle. Let's target v4.11. I'll > review the patches after the merge window. Please ping me if I don't. > > Thanks. > > -- > tejun

Re: [PATCHv13 0/3] rdmacg: IB/core: rdma controller support

ok. Thanks Tejun. Parav On Tue, Dec 6, 2016 at 1:05 AM, Tejun Heo wrote: > Parav, it's a bit too late for this cycle. Let's target v4.11. I'll > review the patches after the merge window. Please ping me if I don't. > > Thanks. > > -- > tejun

Re: [PATCH v8 2/6] powerpc: pSeries/Kconfig: Add qspinlock build config

在 2016/12/6 09:24, Pan Xinhui 写道: 在 2016/12/6 08:58, Boqun Feng 写道: On Mon, Dec 05, 2016 at 10:19:22AM -0500, Pan Xinhui wrote: pSeries/powerNV will use qspinlock from now on. Signed-off-by: Pan Xinhui --- arch/powerpc/platforms/pseries/Kconfig | 8

Re: [PATCH v8 2/6] powerpc: pSeries/Kconfig: Add qspinlock build config

在 2016/12/6 09:24, Pan Xinhui 写道: 在 2016/12/6 08:58, Boqun Feng 写道: On Mon, Dec 05, 2016 at 10:19:22AM -0500, Pan Xinhui wrote: pSeries/powerNV will use qspinlock from now on. Signed-off-by: Pan Xinhui --- arch/powerpc/platforms/pseries/Kconfig | 8 1 file changed, 8

Re: [PATCH v3 10/30] perf clang: Add builtin clang support ant test case

On 2016/12/6 5:48, Arnaldo Carvalho de Melo wrote: Em Mon, Dec 05, 2016 at 07:02:48PM -0200, Arnaldo Carvalho de Melo escreveu: Em Mon, Dec 05, 2016 at 08:51:01AM -0800, Alexei Starovoitov escreveu: yeah. it's kinda high. I'm guessing rpm llvm libs are in debug mode. Try llvm-config

[PATCH] virtio-net: Fix DMA-from-the-stack in virtnet_set_mac_address()

With CONFIG_VMAP_STACK=y, virtnet_set_mac_address() can be passed a pointer to the stack and it will OOPS. Copy the address to the heap to prevent the crash. Cc: Michael S. Tsirkin Cc: Jason Wang Cc: Laura Abbott Reported-by:

Re: [PATCH v3 10/30] perf clang: Add builtin clang support ant test case

On 2016/12/6 5:48, Arnaldo Carvalho de Melo wrote: Em Mon, Dec 05, 2016 at 07:02:48PM -0200, Arnaldo Carvalho de Melo escreveu: Em Mon, Dec 05, 2016 at 08:51:01AM -0800, Alexei Starovoitov escreveu: yeah. it's kinda high. I'm guessing rpm llvm libs are in debug mode. Try llvm-config

[PATCH] virtio-net: Fix DMA-from-the-stack in virtnet_set_mac_address()

With CONFIG_VMAP_STACK=y, virtnet_set_mac_address() can be passed a pointer to the stack and it will OOPS. Copy the address to the heap to prevent the crash. Cc: Michael S. Tsirkin Cc: Jason Wang Cc: Laura Abbott Reported-by: zbys...@in.waw.pl Signed-off-by: Andy Lutomirski --- Very lightly

Re: [PATCH v3 -next 1/2] ARM: sunxi: add support for H2+ SoC

On 05/12/16 20:19, Maxime Ripard wrote: > On Fri, Dec 02, 2016 at 11:05:12PM +0800, Icenowy Zheng wrote: >> Allwinner H2+ is a quad-core Cortex-A7 SoC. >> >> It is very like H3, that they share the same SoC ID (0x1680), and H3 >> memory maps as well as drivers works well on the SoC. >> >>

Re: [PATCH v3 -next 1/2] ARM: sunxi: add support for H2+ SoC

On 05/12/16 20:19, Maxime Ripard wrote: > On Fri, Dec 02, 2016 at 11:05:12PM +0800, Icenowy Zheng wrote: >> Allwinner H2+ is a quad-core Cortex-A7 SoC. >> >> It is very like H3, that they share the same SoC ID (0x1680), and H3 >> memory maps as well as drivers works well on the SoC. >> >>

Re: [RESEND][PATCH v4] cgroup: Use CAP_SYS_RESOURCE to allow a process to migrate other tasks between cgroups

On Mon, Dec 05, 2016 at 04:36:51PM -0800, Andy Lutomirski wrote: > On Mon, Dec 5, 2016 at 4:28 PM, John Stultz wrote: > > On Tue, Nov 22, 2016 at 4:57 PM, John Stultz wrote: > >> On Tue, Nov 8, 2016 at 4:12 PM, Andy Lutomirski

Re: [RESEND][PATCH v4] cgroup: Use CAP_SYS_RESOURCE to allow a process to migrate other tasks between cgroups

On Mon, Dec 05, 2016 at 04:36:51PM -0800, Andy Lutomirski wrote: > On Mon, Dec 5, 2016 at 4:28 PM, John Stultz wrote: > > On Tue, Nov 22, 2016 at 4:57 PM, John Stultz wrote: > >> On Tue, Nov 8, 2016 at 4:12 PM, Andy Lutomirski > >> wrote: > >>> On Tue, Nov 8, 2016 at 4:03 PM, Alexei

Re: [PATCH v3 -next 2/2] ARM: dts: sunxi: add support for Orange Pi Zero board

ORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +/dts-v1/; > +#include "sun8i-h3.dtsi" > +#include "sunxi-common-regulators.dtsi" > + > +#include > +#in

Re: [PATCH v3 -next 2/2] ARM: dts: sunxi: add support for Orange Pi Zero board

E OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +/dts-v1/; > +#include "sun8i-h3.dtsi" > +#include "sunxi-common-regulators.dtsi" > + > +#include > +#include > +#include > + > +/ { > + model = "Xunlo

[RFC PATCH v3] mm: use READ_ONCE in page_cpupid_xchg_last()

A compiler could re-read "old_flags" from the memory location after reading and calculation "flags" and passes a newer value into the cmpxchg making the comparison succeed while it should actually fail. Signed-off-by: Xishi Qiu Suggested-by: Christian Borntraeger

[RFC PATCH v3] mm: use READ_ONCE in page_cpupid_xchg_last()

A compiler could re-read "old_flags" from the memory location after reading and calculation "flags" and passes a newer value into the cmpxchg making the comparison succeed while it should actually fail. Signed-off-by: Xishi Qiu Suggested-by: Christian Borntraeger --- mm/mmzone.c | 2 +- 1

[PATCH] net: ethernet: ti: cpsw: fix early budget split

The budget split function requires the phy speed to be known. While ndo open a phy speed identification is postponed till the moment link is up. Hence, move it to appropriate callback, when link is up. Reported-by: Grygorii Strashko Fixes: 8feb0a196507 ("net: ethernet:

[PATCH] net: ethernet: ti: cpsw: fix early budget split

The budget split function requires the phy speed to be known. While ndo open a phy speed identification is postponed till the moment link is up. Hence, move it to appropriate callback, when link is up. Reported-by: Grygorii Strashko Fixes: 8feb0a196507 ("net: ethernet: ti: cpsw: split tx budget

Re: [PATCH 1/2] Documentation/core-api/device_link: Add initial documentation

On Sun, Dec 04, 2016 at 01:10:04PM +0100, Lukas Wunner wrote: > Document device links as introduced in v4.10 with commits: > 4bdb35506b89 ("driver core: Add a wrapper around >__device_release_driver()") > 9ed9895370ae ("driver core: Functional dependencies tracking >

Re: [PATCH 1/2] Documentation/core-api/device_link: Add initial documentation

On Sun, Dec 04, 2016 at 01:10:04PM +0100, Lukas Wunner wrote: > Document device links as introduced in v4.10 with commits: > 4bdb35506b89 ("driver core: Add a wrapper around >__device_release_driver()") > 9ed9895370ae ("driver core: Functional dependencies tracking >

[PATCH v2 1/2] soc: zte: pm_domains: Prepare for supporting ARMv8 2967 family

The ARMv8 2967 family (296718, 296716 etc) uses different value for controlling the power domain on/off registers, Choose the value depending on the compatible. Multiple domains are prepared for the family, they'are privated by the drivers of boards. This patch prepares the common functions.

[PATCH v2 1/2] soc: zte: pm_domains: Prepare for supporting ARMv8 2967 family

The ARMv8 2967 family (296718, 296716 etc) uses different value for controlling the power domain on/off registers, Choose the value depending on the compatible. Multiple domains are prepared for the family, they'are privated by the drivers of boards. This patch prepares the common functions.

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