STM32 ADC trigger polarity can be set to either rising, falling
or both edges. Add dt option to configure it.
Note: default value may be overridden later via trigger_polarity
sysfs attribute.
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-adc.c | 7 +++
1 file changed, 7 insertions
Add dt documentation for st,stm32-exti-trigger.
EXTi gpio signal can be routed internally as trigger source for various
IPs (e.g. for ADC or DAC conversions).
Signed-off-by: Fabrice Gasnier
---
.../bindings/iio/trigger/st,stm32-exti-trigger.txt | 17 +
1 file changed, 17 ins
EXTi[0..15] gpio signal can be routed internally as trigger source for
ADC or DAC conversions. Configure them as interrupts to configure
trigger path in HW.
Note: interrupt handler isn't required here, and corresponding interrupt
can be kept masked at exti controller level.
Signed-off-by: Fabrice
STM32 ADC, can use GPIOs configured as EXTI line (external interrupt)
as trigger source for conversions.
This patchset is based on latest IIO testing branch, and adds support
for EXTi GPIO triggers in IIO.
It also adds a dt option to configure default trigger polarity in
STM32 ADC driver.
---
Chan
On Mon, Jan 30, 2017 at 05:46:43AM +0100, Frederic Weisbecker wrote:
> Now lets admit one drawback: s390 and powerpc with
> CONFIG_VIRT_CPU_ACCOUNTING_NATIVE have new cputime_t to nsecs conversion
> on cputime accounting path. But this should be leveraged by the recent
> changes which delay the cpu
Hi Lee,
On Fri, 27 Jan 2017, Lee Jones wrote:
> On Wed, 25 Jan 2017, Peter Griffin wrote:
>
> > Hi Lee,
> >
> > On Tue, 24 Jan 2017, Lee Jones wrote:
> >
> > > There are now 2 possible separate/different Pinctrl states which can
> > > be provided from platform data. One which encompasses the
Hi Chris,
On lun., janv. 30 2017, Chris Packham
wrote:
> These boards are Marvell's evaluation boards for the 98DX4251 and
> 98DX3336 SoCs.
>
> Signed-off-by: Chris Packham
Applied on mvebu/dt
Thanks,
Gregory
> ---
>
> Notes:
> Changes in v5:
> - update license text
> - use n
This fixes the following smatch and coccinelle warnings:
drivers/net/ethernet/cavium/thunder/thunder_xcv.c:119 xcv_setup_link() error:
we previously assumed 'xcv' could be null (see line 118) [smatch]
drivers/net/ethernet/cavium/thunder/thunder_xcv.c:119:16-20: ERROR: xcv is
NULL but derefer
Hi Chris,
On lun., janv. 30 2017, Chris Packham
wrote:
> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
> with integrated CPUs. They are similar to the Armada XP SoCs but have
> different I/O interfaces.
>
> Signed-off-by: Chris Packham
> Acked-by: Rob Herring
Appli
STM32 ADC, can use GPIOs configured as EXTI line (external interrupt)
as trigger source for conversions.
This patchset is based on latest IIO testing branch, and adds support
for EXTi GPIO triggers in IIO.
It also adds a dt option to configure default trigger polarity in
STM32 ADC driver.
Fabrice
Hi Chris,
On lun., janv. 30 2017, Chris Packham
wrote:
> Compared to the armada-xp the 98DX3336 uses different registers to set
> the boot address for the secondary CPU so a new enable-method is needed.
> This will only work if the machine definition doesn't define an overall
> smp_ops becaus
On Mon, Jan 30, 2017 at 04:55:33PM +0300, Alexander Kochetkov wrote:
>
> > 30 янв. 2017 г., в 16:12, Daniel Lezcano
> > написал(а):
> >
> > I don't get the point of these changes. The patch does not explain why they
> > are
> > needed.
>
> I’d like to extract timer API from current implementa
From: Stephen Boyd
The high-speed phy on qcom SoCs is controlled via the ULPI
viewport.
Cc: Kishon Vijay Abraham I
Cc:
Acked-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/qcom,usb-hs-phy.txt| 84 ++
drivers/phy/K
From: Stephen Boyd
The HSIC USB controller on qcom SoCs has an integrated all
digital phy controlled via the ULPI viewport.
Cc: Kishon Vijay Abraham I
Acked-by: Rob Herring
Cc:
Signed-off-by: Stephen Boyd
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/qcom,usb-hsic-p
From: Stephen Boyd
The high-speed phy on qcom SoCs is controlled via the ULPI
viewport.
Cc: Kishon Vijay Abraham I
Cc:
Acked-by: Rob Herring
Signed-off-by: Stephen Boyd
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/qcom,usb-hs-phy.txt| 84 ++
drivers/phy/K
From: Bjorn Andersson
When regulator_get() tries to resolve a regulator supply but fail to
find a matching property in DeviceTree it returns a dummy regulator, if
a matching supply is specified but unavailable the regulator core will
return an error.
Based on this we should not ignore errors upo
STM32F4 ADC can use exti11 (gpio) signal as trigger source for
conversions.
Signed-off-by: Fabrice Gasnier
---
drivers/iio/adc/stm32-adc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
index be0e457..0118c9c 100644
--- a/driv
Dear Friend,
I did not forgot your past effort and attempts to assist me, now i am happy to
inform you that i have succeeded in getting those funds transferred with the
help of a new partner from India. Now Contact my secretary, ask her for Seven
Hundred And Fifty Thousand United States Dolla
On Fri, Jan 27, 2017 at 11:07 AM, Mika Westerberg
wrote:
> This driver adds pinctrl/GPIO support for Intel Gemini Lake SoC. The
> GPIO controller is based on the next generation GPIO hardware but still
> compatible with the one supported by the Intel core pinctrl/GPIO driver.
>
> This commit incl
On 01/30, Pavel Tikhomirov wrote:
>
> On 01/30/2017 03:51 PM, Oleg Nesterov wrote:
> >>+ /*
> >>+* Inherit has_child_subreaper flag under the same
> >>+* tasklist_lock with adding child to the process tree
> >>+* for prop
On Sun, Jan 22, 2017 at 08:52:12AM +0530, afzal mohammed wrote:
> The exception base address is now dynamically estimated for no-MMU,
> display it. As it is the case, now limit VECTORS_BASE usage to MMU
> scenario.
>
> Signed-off-by: afzal mohammed
As I wrote elsewhere...
> diff --git a/arch/ar
STM32 ADC trigger polarity can be set to either rising, falling
or both edges. Allow to configure it from dt.
Signed-off-by: Fabrice Gasnier
---
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio
Hi all,
Please discard this series. I'll send a V2.
Sorry for the noise.
Best regards,
Fabrice
On 01/30/2017 02:57 PM, Fabrice Gasnier wrote:
STM32 ADC, can use GPIOs configured as EXTI line (external interrupt)
as trigger source for conversions.
This patchset is based on latest IIO testing br
On Fri, Jan 27, 2017 at 11:07 AM, Mika Westerberg
wrote:
> The next generation Intel GPIO hardware has two additional registers
> PADCFG2 and PADCFG3. The latter is marked as reserved but the former
> includes configuration for per-pad hardware debouncer.
>
> This patch adds support for that in t
On Mon, 2017-01-30 at 12:30 +, Mark Brown wrote:
> On Mon, Jan 30, 2017 at 12:41:16PM +0100, Philipp Zabel wrote:
> > As of commit bb475230b8e5 ("reset: make optional functions really
> > optional"), the reset framework API calls use NULL pointers to describe
> > optional, non-present reset con
On Fri, Jan 27, 2017 at 11:07 AM, Mika Westerberg
wrote:
> The next generation Intel GPIO hardware supports additional 1k pull-down
> per-pad. Add support for this to the Intel core pinctrl driver.
>
> Signed-off-by: Mika Westerberg
> Reviewed-by: Andy Shevchenko
Patch applied.
And if you one
Em Sun, Jan 29, 2017 at 02:35:20PM -0500, Tejun Heo escreveu:
> perf_event is a utility controller whose primary role is identifying
> cgroup membership to filter perf events; however, because it also
> tracks some per-css state, it can't be replaced by pure cgroup
> membership test. Mark the cont
EXTi[0..15] gpio signal can be routed internally as trigger source for
ADC or DAC conversions. Configure them as interrupts to configure
trigger path in HW.
Note: interrupt handler isn't required here, and corresponding interrupt
can be kept masked at exti controller level.
Signed-off-by: Fabrice
On 01/30/2017 10:49 AM, Michal Hocko wrote:
From: Michal Hocko
alloc_bucket_locks allocation pattern is quite unusual. We are
preferring vmalloc when CONFIG_NUMA is enabled. The rationale is that
vmalloc will respect the memory policy of the current process and so the
backing memory will get di
Matt Fleming wrote:
> > Matt argues, however, that boot_params->secure_boot should be propagated
> > from
> > the bootloader and if the bootloader wants to set it, then we should skip
> > the
> > check in efi_main() and go with the bootloader's opinion. This is something
> > we probably want t
The stx104_dev structure was used to hold private data for use in the
stx104_remove function. Now that the stx104_remove function is gone, the
stx104_dev structure and relevant code is no longer needed. This patch
removes the unnecessary code.
Signed-off-by: William Breathitt Gray
---
drivers/ii
On Fri, Jan 20, 2017 at 01:04:03PM -0800, Bart Van Assche wrote:
> Now that all set_dma_ops() implementations are identical (ignoring
> BUG_ON() statements), remove the architecture specific definitions
> and add a definition in .
>
> Signed-off-by: Bart Van Assche
> Cc: Benjamin Herrenschmidt
>
On 01/25, Kees Cook wrote:
>
> On Mon, Jan 23, 2017 at 4:52 AM, Oleg Nesterov wrote:
> > On 01/23, Oleg Nesterov wrote:
> >>
> >> Btw task_is_descendant() looks wrong at first glance.
> >
> > No, I missed the 2nd ->group_leader dereference. Still this function looks
> > overcomplicated and the usa
On Mon, Jan 30, 2017 at 12:20 AM, Chris Packham
wrote:
> From: Kalyan Kinthada
>
> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
> from Marvell.
>
> Signed-off-by: Kalyan Kinthada
> Signed-off-by: Chris Packham
> Acked-by: Rob Herring
> Acked-by: Sebastian Hesselbarth
On Sat, Jan 28, 2017 at 04:28:13PM +0100, Frederic Weisbecker wrote:
> On Sat, Jan 28, 2017 at 12:57:40PM +0100, Stanislaw Gruszka wrote:
> > On 32 bit architectures 64bit store/load is not atomic and if not
> > protected - 64bit variables can be mangled. I do not see any protection
> > (lock) betw
On Mon, 30 Jan, at 12:10:29PM, David Howells wrote:
>
> Matt argues, however, that boot_params->secure_boot should be propagated from
> the bootloader and if the bootloader wants to set it, then we should skip the
> check in efi_main() and go with the bootloader's opinion. This is something
> we
> 30 янв. 2017 г., в 16:12, Daniel Lezcano
> написал(а):
>
> I don't get the point of these changes. The patch does not explain why they
> are
> needed.
I’d like to extract timer API from current implementation.
And to make code more readable I’d like to introduce 'struct rk_timer’ what can
On Tue, Jan 24, 2017 at 03:16:43PM +0300, Alexander Kochetkov wrote:
> The clock supplying the arm-global-timer on the rk3188 is coming from the
> the cpu clock itself and thus changes its rate everytime cpufreq adjusts
> the cpu frequency making this timer unsuitable as a stable clocksource
> and
Hi Jens/Omar,
I used git.kernel.dk/linux-block branch - blk-mq-sched (commit
0efe27068ecf37ece2728a99b863763286049ab5) and confirm that issue reported in
this thread is resolved.
Now I am seeing MQ and SQ mode both are resulting in sequential IO pattern
while IO is getting re-queued in block lay
On 01/30/2017 03:51 PM, Oleg Nesterov wrote:
On 01/27, Pavel Tikhomirov wrote:
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -1725,6 +1725,8 @@ struct task_struct {
struct signal_struct *signal;
struct sighand_struct *sighand;
+ struct list_head csr_descend
On Mon, Jan 30, 2017 at 09:02:49AM +, Benjamin GAIGNARD wrote:
>
>
> On 01/28/2017 01:19 PM, Jens Wiklander wrote:
[...]
> > +/**
> > + * tee_shm_alloc() - Allocate shared memory
> > + * @ctx: Context that allocates the shared memory
> > + * @size: Requested size of shared memory
> > + * @
Commit-ID: da6adaea2b7ef658c61a557c28508668eac29fe1
Gitweb: http://git.kernel.org/tip/da6adaea2b7ef658c61a557c28508668eac29fe1
Author: Janakarajan Natarajan
AuthorDate: Mon, 16 Jan 2017 17:36:23 -0600
Committer: Ingo Molnar
CommitDate: Mon, 30 Jan 2017 12:01:18 +0100
perf/x86/amd/uncor
Commit-ID: 612f0c0b859ee99f800dc88ad470d938d90ad111
Gitweb: http://git.kernel.org/tip/612f0c0b859ee99f800dc88ad470d938d90ad111
Author: Borislav Petkov
AuthorDate: Thu, 26 Jan 2017 09:08:19 +0100
Committer: Ingo Molnar
CommitDate: Mon, 30 Jan 2017 12:01:19 +0100
perf/x86/events: Add an
This is driver for USB DRD Phy used in Broadcom's Northstar2
SoC. The phy can be configured to be in Device mode or Host
mode based on the type of cable connected to the port. The
driver registers to extcon framework to get appropriate
connect events for Host/Device cables connect/disconnect
state
Changes from v2:
===
Remove unnecessary checks for poweron as suggested in review.
Changes from v1:
===
1. Initialize file operations .owner field with THIS_MODULE.
2. Remove unnecessary gpio example in DT bindings documentation.
This is previously acked by Rob Herring
This patch adds device tree nodes for USB Dual Role Device Phy for
Broadcom's Northstar2 SoC.
Signed-off-by: Raviteja Garimella
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi
b/arch/arm64/boot/d
On Fri, Jan 27, 2017 at 01:07:35PM -0800, Kees Cook wrote:
> On Fri, Jan 27, 2017 at 1:58 AM, Peter Zijlstra wrote:
> > Nothing much, except lack of time. I spend the last several days hunting
> > bugs, that trumps new features on my todo list.
>
> Totally understood. I was just trying to see if
This patch adds documentation for NS2 DRD Phy driver DT bindings
Signed-off-by: Raviteja Garimella
Acked-by: Rob Herring
---
.../devicetree/bindings/phy/brcm,ns2-drd-phy.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy
On Fri 2017-01-27 19:19:30, Borislav Petkov wrote:
> + printk folk.
>
> On Fri, Jan 27, 2017 at 04:42:30PM +0100, Rabin Vincent wrote:
> > proc_dostring() eats the '\n' and stops
>
> Not a problem, see diff below.
>
> Please do it this way instead because after a month no one will remember
> wha
On Mon, Jan 30, 2017 at 04:13:07PM +0300, Alexander Kochetkov wrote:
>
> > 30 янв. 2017 г., в 15:04, Daniel Lezcano
> > написал(а):
> >
> > There is no case when the rockchip timer is used for the clockevent.
> The is already timer entry for rk3228 in the DT. And it act as clockevent. I
> gues
On Fri, Jan 27, 2017 at 05:23:24PM +, Brian Starkey wrote:
> Hi,
>
> We're looking to enable the per-plane color management hardware in
> Mali-DP with atomic properties, which has sparked some conversation
> around how to handle YCbCr formats.
>
> As it stands today, it's assumed that a drive
On 01/30/2017 06:04 AM, Shailendra Verma wrote:
> of_device_get_match_data could return NULL, and so can cause
> a NULL pointer dereference later.
>
> Signed-off-by: Shailendra Verma
> ---
> sound/soc/samsung/i2s.c |7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git
On Fri, 13 Jan 2017, David Daney wrote:
> At the point where the handle_*_irq() functions call handle_irq_event(), we
> need to 9optionally) do something both immediately before and after the call
> to handle_irq_event().
>
> In irq_chip add a function:
>
> void (*irq_handle)(struct irq_data
We introduced recently a new compatible to deal with the A64 eMMC
controller, let's document its binding.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
From: Bjorn Andersson
The fact that a regulator is always-on is a property of the regulator,
not a specific consumer. Implementing this in the driver leads to a
system behaviour that is dependent on if the Qualcomm UFS PHY was ever
(partially) probed.
If the specific regulator should be always o
On Mon, Jan 30, 2017 at 11:00:28AM +0100, Geert Uytterhoeven wrote:
> On Mon, Jan 30, 2017 at 5:55 AM, Shailendra Verma
> wrote:
> > of_match_device could return NULL, and so can cause a NULL
> > pointer dereference later.
> Can it? The driver uses DT exclusively.
> There is no legacy platform co
> 30 янв. 2017 г., в 15:04, Daniel Lezcano
> написал(а):
>
> There is no case when the rockchip timer is used for the clockevent.
The is already timer entry for rk3228 in the DT. And it act as clockevent. I
guess it work as backup,
but I cannot test it also. In order to not break DT compatibil
On Tue, Jan 24, 2017 at 03:16:40PM +0300, Alexander Kochetkov wrote:
> The patch move ce field out of struct bc_timer into struct
> rk_clock_event_device and rename struct bc_timer to struct rk_timer.
>
> The main idea for the commit is to exctact low level timer
> routines from current implementa
On 30/01/17 11:58, walter harms wrote:
>
>
> Am 30.01.2017 12:25, schrieb Colin King:
>> From: Colin Ian King
>>
>> scrub_mode and scrub_count are both unsigned ints, however, the %d
>> format string specifier is being used instead of %u. Trivial fix,
>> use %u.
>>
>> Signed-off-by: Colin Ian Ki
On Sat, 28 Jan 2017, Laura Abbott wrote:
> > > Was out for a few days, reporter says the below patch does not work.
> > > There was some confusion with secure boot so I've asked them to re-test
> > > with efi=old_map and secure boot off.
> >
> > FYI, you may want to ask the reporter to try out Ji
> The central issue seems to be that I think media pad links / media bus
> formats should describe physical links, such as parallel or serial
> buses, and the formats of pixels flowing through them, whereas Steve
> would like to extend them to describe software transports and in-memory
> formats.
g new PMU register defines to separate patch (requested by
Krzysztof Kozlowski)
- rebased onto Linux next-20170130 (removed "soc: samsung: pmu: Add dummy
support for Exynos5433 SoC" and "arm64: dts: exynos: Add clocks to
Exynos5433 LPASS module" patches, which are already
Hi Dmitri,
On Tue, Jan 10, 2017 at 5:11 PM, Benjamin Tissoires
wrote:
> Hi,
>
> Well, this is the last series which enables RMI4 over SMBus for the Thinkpad
> t*40, t*50, t*60 series. Few comments on the patches:
>
> patches 1 to 3 allows the re-routing of the trackstick buttons from the
> touch
Hi all,
Le 21/12/2016 à 08:23, John Crispin a écrit :
> From: "Larry D. Pinney"
>
> Add Support for the ESMT_F25L32QA and ESMT_F25L64QA
> These are 4MB and 8MB SPI NOR Chips from Elite Semiconductor Memory
> Technology
>
> Acked-by: Marek Vasut
> Signed-off-by: John Crispin
> Signed-off-by: L
From: Bjorn Andersson
Upon failing to acquire regulator supplies the qcom-ufs driver calls
kfree() on the devm allocated memory used to store the name of the
regulator, leading to devres corruption.
Rather than switching to using the appropriate free function the patch
acknowledge the fact that
On Mon, 30 Jan 2017, Henning Schild wrote:
> On Mon, 30 Jan 2017 11:20:25 +0100
> Thomas Gleixner wrote:
> > There is nothing you can ever be sure about, but I doubt that the
> > ADJUST MSR is going to vanish.
>
> That sounds very much like i expected. But assuming the MSR has come to
> stay, the
Resending to a larger e-mail list...
On Mon, 2017-01-30 at 04:57 -0800, Michael Zoran wrote:
> I'm looking at linux-next:
> drivers/staging/vc04_services/interface/vchiq_arm/vchiq_connected.c
>
> First it looks this is some kind of startup notification mechanism
> and
> it is used by the custom R
On Sun, Jan 29, 2017 at 10:29 PM, Luis R. Rodriguez wrote:
> Commit e7d316a02f6838 ("sysctl: handle error writing UINT_MAX to u32 fields")
> added proc_douintvec() to start help adding support for unsigned int,
> this however was only half the work needed, all these issues are present
> with the c
This patch adds support for the ultrasonic ranger srf04 of devantech.
This device is measuring the distance of objects in a range between 1 cm
and 3 meters and a theoretical resolution of 3 mm.
There are two GPIOs used:
- trigger: set as output to the device when the measurement should start
Hi Philipp,
On Mon, 30 Jan 2017 12:41:11 +0100
Philipp Zabel wrote:
> As of commit bb475230b8e5 ("reset: make optional functions really
> optional"), the reset framework API calls use NULL pointers to describe
> optional, non-present reset controls.
>
> This allows to return errors from devm_re
5 kernel, and found it hanged on boot. The exact
> >> reason is
> >> panic on dereferencing of the 0xffc8 address, which is most probably
> >> the
> >> attempt to dereference the ENOSYS error code as the address. next-20170124
> >> works
> >> f
Hello Shailendra,
The subject line is wrong, please always use the convention used in
previous commits, i.e: git log --oneline drivers/gpu/drm/exynos/
On 01/30/2017 02:02 AM, Shailendra Verma wrote:
> of_device_get_match_data could return NULL, and so can cause
> a NULL pointer dereference later.
On 01/27, Pavel Tikhomirov wrote:
>
> --- a/include/linux/sched.h
> +++ b/include/linux/sched.h
> @@ -1725,6 +1725,8 @@ struct task_struct {
> struct signal_struct *signal;
> struct sighand_struct *sighand;
>
> + struct list_head csr_descendant;
> +
You forgot to remove this part
When pin controller device is a part of power domain, there is no guarantee
that the power domain was not turned off and then on during boot process
before probing of the pin control driver. If it happened, then pin control
driver should ensure that pad retention is turned off during its probe call
This patch adds dt binding for devantech ultrasonic ranger srf04.
The vendor "devantech" was already added to the vendor list with
"[PATCH v4 1/3] iio: distance: srf08: add trivial DT binding"
Signed-off-by: Andreas Klinger
---
.../bindings/iio/proximity/devantech-srf04.txt | 28 +++
This patch series adds support for the devantech srf04 ultrasonic ranger as
IIO device.
The device is able to recognize objects in a range of 1 cm and 3 meters.
The theoretical resolution is about 3 mm, practically more or less 1 cm.
Use cases for this device are level metering in tanks or distan
Pad retention should be controlled from pin control driver, so remove it
from Exynos LPASS driver. After this change, no more access to PMU regmap
is needed, so remove also the code for handling PMU regmap.
Signed-off-by: Marek Szyprowski
Acked-by: Krzysztof Kozlowski
Acked-by: Sylwester Nawrock
Exynos LPASS requires some clocks to be enabled to make any access to its
registers. This patch adds code for handling such clocks. For current set
of registers it is enough to keep sfr0_ctrl clock enabled. Till now it
worked only because those clocks were enabled by bootloader and driver
probe() h
Le 27/01/2017 à 23:29, Rob Herring a écrit :
> On Wed, Jan 25, 2017 at 11:38:34AM +0800, Guochun Mao wrote:
>> Add "mediatek,mt2701-nor" for nor flash node's compatible.
>>
>> Signed-off-by: Guochun Mao
>> ---
>> .../devicetree/bindings/mtd/mtk-quadspi.txt|8 +++-
>> 1 file change
The purpose of USB Type-C connector class is to provide
unified interface for the user space to get the status and
basic information about USB Type-C connectors on a system,
control over data role swapping, and when the port supports
USB Power Delivery, also control over power role swapping
and Alt
Make a simple helper for matching strings with sysfs
attribute files. In most parts the same as match_string(),
except sysfs_match_string() uses sysfs_streq() instead of
strcmp() for matching. This is more convenient when used
with sysfs attributes.
Signed-off-by: Heikki Krogerus
Reviewed-by: Mik
Disable device on driver remove and release allocated regmap.
Signed-off-by: Marek Szyprowski
Reviewed-by: Krzysztof Kozlowski
Acked-by: Sylwester Nawrocki
---
drivers/mfd/exynos-lpass.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/e
This patch adds support for retention control for Exynos5433 SoCs. Three
groups of pins has been defined for retention control: common shared group
for ALIVE, CPIF, eSE, FINGER, IMEM, NFC, PERIC, TOUCH pin banks and
separate control for FSYS and AUD pin banks, for which PMU retention
registers matc
This adds driver for the USB Type-C PHY on Intel WhiskeyCove
PMIC which is available on some of the Intel Broxton SoC
based platforms.
Signed-off-by: Heikki Krogerus
Reviewed-by: Mika Westerberg
Reviewed-by: Felipe Balbi
---
drivers/usb/typec/Kconfig | 14 ++
drivers/usb/typec/Makefile
The USB Type-C class is meant to provide unified interface to the
userspace to present the USB Type-C ports in a system.
Changes since v15:
- "stingification" as proposed by Felipe
- Checking ARRAY_SIZE in supported_accessory_modes() as proposed by Guenter
Changes since v14:
- Fixes proposed by M
On Mon, Jan 30, 2017 at 07:37:58PM +0900, Taeung Song wrote:
>
>
> On 01/30/2017 06:01 PM, Jiri Olsa wrote:
> > On Mon, Jan 30, 2017 at 02:23:38PM +0900, Taeung Song wrote:
> > > Currently there are several parts not checking NULL
> > > after allocating with zalloc() or asigning NULL value
> > >
On Mon, Jan 30, 2017 at 07:32:03PM +0900, Taeung Song wrote:
SNIP
> > looks almost the same as for_each_event_system macro,
> > what's the difference other than 'ftrace' check?
>
> Little thing.
> In parse-events.c for_each_event macro contains
> tp_event_has_id() function But this function isn'
On Tue, 17 Jan 2017 14:22:46 +
Wei Yongjun wrote:
> From: Wei Yongjun
>
> There is a error message within devm_ioremap_resource
> already, so remove the dev_err call to avoid redundant
> error message.
>
Applied.
Thanks,
Boris
> Signed-off-by: Wei Yongjun
> ---
> drivers/mtd/nand/mtk
Wat?
I'm sorry but this patch makes no sense at all.
On Sat, Jan 28, 2017 at 07:04:41PM -0500, James Simmons wrote:
> From: Bruno Faccini
>
> When a LBUG has occurred, without panic_on_lbug being set,
> health_check sysfs file must return an unhealthy state.
Why?
>
> Signed-off-by: Bruno Fac
On Jan 30 2017 or thereabouts, Johan Hovold wrote:
> These patches fix a sleep-while-atomic and an error-handling issue
> introduced by a patch that went into 4.9.
>
> Note that this series has only been compile tested.
Tested the series, and:
Reviewed-by: Benjamin Tissoires
Thanks for spotting
We can't just add segfault handler and use addr, returned by compat
mmap() syscall, because the lower 4 bytes can be the same as already
existed VMA. So, the test parses /proc/self/maps file, founds new
VMAs those appeared after compatible sys_mmap() and checks if mmaped
VMA is in that list.
On fa
Add PMU defines related to pad retention control. Will be later used
by the Exynos pin controller driver.
Signed-off-by: Marek Szyprowski
---
include/linux/soc/samsung/exynos-regs-pmu.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/linux/soc/samsung/exynos-regs-pm
Convert exisitng lpass-suspend/resume callbacks into runtime PM callbacks.
This way Exynos LPASS driver will be ready for use with power domains
enabled. LPASS will be runtime resumed/suspended as a result of its child
devices runtime PM transitions.
Signed-off-by: Marek Szyprowski
Acked-by: Krzy
On 01/30/2017 12:41 PM, Philipp Zabel wrote:
> As of commit bb475230b8e5 ("reset: make optional functions really
> optional"), the reset framework API calls use NULL pointers to describe
> optional, non-present reset controls.
>
> This allows to return errors from reset_control_get_optional and t
On Mon, Jan 30, 2017 at 09:41:21AM +0100, John Ogness wrote:
> Although wbinvd() is faster than flushing many individual pages, it
> blocks the memory bus for "long" periods of time (>100us), thus
> directly causing unusually large latencies on all CPUs, regardless
> of any CPU isolation features t
Add the CPT options in crypto Kconfig and update the
crypto Makefile
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/Makefile | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 7956
Enable the CPT VF driver. CPT is the cryptographic Acceleration Unit
in Octeon-tx series of processors.
Signed-off-by: George Cherian
Reviewed-by: David Daney
---
drivers/crypto/cavium/cpt/Makefile | 3 +-
drivers/crypto/cavium/cpt/cptvf.h| 135
drivers/crypto/caviu
Enable the Physical Function driver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Accelaration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric engines (AEs).
Signed-off-by: George Cherian
Reviewed-by: David Daney
-
This series adds the support for Cavium Cryptographic Accelerarion Unit (CPT)
CPT is available in Cavium's Octeon-Tx SoC series.
The series was tested with ecryptfs and dm-crypt for in kernel
On Mon, Jan 30, 2017 at 12:41:16PM +0100, Philipp Zabel wrote:
> As of commit bb475230b8e5 ("reset: make optional functions really
> optional"), the reset framework API calls use NULL pointers to describe
> optional, non-present reset controls.
I've only got this patch from the series, what's the
701 - 800 of 1053 matches
Mail list logo
