Re: [PATCH 17/35] drivers/gpu: Convert remaining uses of pr_warning to pr_warn

Am 17.02.2017 um 08:11 schrieb Joe Perches: To enable eventual removal of pr_warning This makes pr_warn use consistent for drivers/gpu Prior to this patch, there were 15 uses of pr_warning and 20 uses of pr_warn in drivers/gpu Signed-off-by: Joe Perches Acked-by:

Re: [PATCH 17/35] drivers/gpu: Convert remaining uses of pr_warning to pr_warn

Am 17.02.2017 um 08:11 schrieb Joe Perches: To enable eventual removal of pr_warning This makes pr_warn use consistent for drivers/gpu Prior to this patch, there were 15 uses of pr_warning and 20 uses of pr_warn in drivers/gpu Signed-off-by: Joe Perches Acked-by: Christian König . ---

[PATCHv3 08/33] x86: basic changes into headers for 5-level paging

This patch extends x86 headers to enable 5-level paging support. It's still based on . We will get to the point where we can have later. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/pgtable-2level_types.h | 1 +

[PATCHv3 04/33] arch, mm: convert all architectures to use 5level-fixup.h

If an architecture uses 4level-fixup.h we don't need to do anything as it includes 5level-fixup.h. If an architecture uses pgtable-nop*d.h, define __ARCH_USE_5LEVEL_HACK before inclusion of the header. It makes asm-generic code to use 5level-fixup.h. If an architecture has 4-level paging or

[PATCHv3 08/33] x86: basic changes into headers for 5-level paging

This patch extends x86 headers to enable 5-level paging support. It's still based on . We will get to the point where we can have later. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/pgtable-2level_types.h | 1 + arch/x86/include/asm/pgtable-3level_types.h | 1 +

[PATCHv3 04/33] arch, mm: convert all architectures to use 5level-fixup.h

If an architecture uses 4level-fixup.h we don't need to do anything as it includes 5level-fixup.h. If an architecture uses pgtable-nop*d.h, define __ARCH_USE_5LEVEL_HACK before inclusion of the header. It makes asm-generic code to use 5level-fixup.h. If an architecture has 4-level paging or

[PATCHv3 03/33] asm-generic: introduce __ARCH_USE_5LEVEL_HACK

We are going to introduce to provide abstraction for properly (in opposite to 5level-fixup.h hack) folded p4d level. The new header will be included from pgtable-nopud.h. If an architecture uses , we cannot use 5level-fixup.h directly to quickly convert the architecture to 5-level paging as it

[PATCHv3 03/33] asm-generic: introduce __ARCH_USE_5LEVEL_HACK

We are going to introduce to provide abstraction for properly (in opposite to 5level-fixup.h hack) folded p4d level. The new header will be included from pgtable-nopud.h. If an architecture uses , we cannot use 5level-fixup.h directly to quickly convert the architecture to 5-level paging as it

[PATCHv3 11/33] x86/ident_map: add 5-level paging support

Nothing special: just handle one more level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/ident_map.c | 47 --- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/x86/mm/ident_map.c

[PATCHv3 11/33] x86/ident_map: add 5-level paging support

Nothing special: just handle one more level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/ident_map.c | 47 --- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/arch/x86/mm/ident_map.c b/arch/x86/mm/ident_map.c index

[PATCHv3 07/33] mm: introduce __p4d_alloc()

For full 5-level paging we need a helper to allocate p4d page table. Signed-off-by: Kirill A. Shutemov --- mm/memory.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/mm/memory.c b/mm/memory.c index e4a37c340a56..c1e3706dc597 100644

[PATCHv3 07/33] mm: introduce __p4d_alloc()

For full 5-level paging we need a helper to allocate p4d page table. Signed-off-by: Kirill A. Shutemov --- mm/memory.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/mm/memory.c b/mm/memory.c index e4a37c340a56..c1e3706dc597 100644 --- a/mm/memory.c +++

[PATCHv3 13/33] x86/power: support p4d_t in hibernate code

set_up_temporary_text_mapping() and relocate_restore_code() require trivial adjustments to handle additional page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/power/hibernate_64.c | 49 ++- 1 file changed,

[PATCHv3 13/33] x86/power: support p4d_t in hibernate code

set_up_temporary_text_mapping() and relocate_restore_code() require trivial adjustments to handle additional page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/power/hibernate_64.c | 49 ++- 1 file changed, 35 insertions(+), 14 deletions(-)

[PATCHv3 01/33] x86/cpufeature: Add 5-level paging detection

Look for 'la57' in /proc/cpuinfo to see if your machine supports 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/cpufeatures.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h

[PATCHv3 01/33] x86/cpufeature: Add 5-level paging detection

Look for 'la57' in /proc/cpuinfo to see if your machine supports 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/cpufeatures.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h

[PATCHv3 23/33] x86/paravirt: make paravirt code support 5-level paging

Add operations to allocate/release p4ds. TODO: cover XEN. Not-yet-Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/paravirt.h | 44 +++ arch/x86/include/asm/paravirt_types.h | 7 +-

[PATCHv3 23/33] x86/paravirt: make paravirt code support 5-level paging

Add operations to allocate/release p4ds. TODO: cover XEN. Not-yet-Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/paravirt.h | 44 +++ arch/x86/include/asm/paravirt_types.h | 7 +- arch/x86/include/asm/pgalloc.h| 2 ++

[PATCHv3 28/33] x86/mm: add support of additional page table level during early boot

This patch adds support for 5-level paging during early boot. It generalizes boot for 4- and 5-level paging on 64-bit systems with compile-time switch between them. Signed-off-by: Kirill A. Shutemov --- arch/x86/boot/compressed/head_64.S | 23

[PATCHv3 28/33] x86/mm: add support of additional page table level during early boot

This patch adds support for 5-level paging during early boot. It generalizes boot for 4- and 5-level paging on 64-bit systems with compile-time switch between them. Signed-off-by: Kirill A. Shutemov --- arch/x86/boot/compressed/head_64.S | 23 +-- arch/x86/include/asm/pgtable.h

[PATCHv3 27/33] x86/espfix: support 5-level paging

We don't need extra virtual address space for ESPFIX, so it stays within one PUD page table for both 4- and 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/espfix_64.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff

[PATCHv3 27/33] x86/espfix: support 5-level paging

We don't need extra virtual address space for ESPFIX, so it stays within one PUD page table for both 4- and 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/espfix_64.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git

[PATCHv3 16/33] x86/mm/pat: handle additional page table

Straight-forward extension of existing code to support additional page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/pageattr.c | 56 -- 1 file changed, 41 insertions(+), 15 deletions(-) diff

Re: [PATCH 2/2] x86/xen: use capabilities instead of fake cpuid values

On 17/02/17 15:05, Boris Ostrovsky wrote: > > > On 02/17/2017 02:36 AM, Juergen Gross wrote: >> When running as pv domain xen_cpuid() is being used instead of >> native_cpuid(). In xen_cpuid() the aperf/mperf feature is indicated >> as not being present by special casing the related cpuid leaf.

[PATCHv3 16/33] x86/mm/pat: handle additional page table

Straight-forward extension of existing code to support additional page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/pageattr.c | 56 -- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/arch/x86/mm/pageattr.c

Re: [PATCH 2/2] x86/xen: use capabilities instead of fake cpuid values

On 17/02/17 15:05, Boris Ostrovsky wrote: > > > On 02/17/2017 02:36 AM, Juergen Gross wrote: >> When running as pv domain xen_cpuid() is being used instead of >> native_cpuid(). In xen_cpuid() the aperf/mperf feature is indicated >> as not being present by special casing the related cpuid leaf.

Re: [PATCH 2/2] x86/mm/numa: remove the numa_nodemask_from_meminfo()

Hi, Willing to hear from all of you :-) On Mon, Feb 6, 2017 at 11:35 PM, Wei Yang wrote: > numa_nodemask_from_meminfo() is called to set bit according to > numa_meminfo. While the only two places for this call is used to set proper > bit to a copy of numa_nodes_parsed

Re: [PATCH 2/2] x86/mm/numa: remove the numa_nodemask_from_meminfo()

Hi, Willing to hear from all of you :-) On Mon, Feb 6, 2017 at 11:35 PM, Wei Yang wrote: > numa_nodemask_from_meminfo() is called to set bit according to > numa_meminfo. While the only two places for this call is used to set proper > bit to a copy of numa_nodes_parsed from numa_meminfo. With

[PATCHv3 33/33] mm, x86: introduce PR_SET_MAX_VADDR and PR_GET_MAX_VADDR

This patch introduces two new prctl(2) handles to manage maximum virtual address available to userspace to map. On x86, 5-level paging enables 56-bit userspace virtual address space. Not all user space is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits

[PATCHv3 32/33] x86: enable 5-level paging support

Most of things are in place and we can enable support of 5-level paging. Enabling XEN with 5-level paging requires more work. The patch makes XEN dependent on !X86_5LEVEL. Signed-off-by: Kirill A. Shutemov --- arch/x86/Kconfig | 5 +

[PATCHv3 32/33] x86: enable 5-level paging support

Most of things are in place and we can enable support of 5-level paging. Enabling XEN with 5-level paging requires more work. The patch makes XEN dependent on !X86_5LEVEL. Signed-off-by: Kirill A. Shutemov --- arch/x86/Kconfig | 5 + arch/x86/xen/Kconfig | 1 + 2 files changed, 6

[PATCHv3 33/33] mm, x86: introduce PR_SET_MAX_VADDR and PR_GET_MAX_VADDR

This patch introduces two new prctl(2) handles to manage maximum virtual address available to userspace to map. On x86, 5-level paging enables 56-bit userspace virtual address space. Not all user space is ready to handle wide addresses. It's known that at least some JIT compilers use higher bits

[PATCHv3 31/33] x86/mm: add support for 5-level paging for KASLR

With 5-level paging randomization happens on P4D level instead of PUD. Maximum amount of physical memory also bumped to 52-bits for 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/kaslr.c | 82

[PATCHv3 31/33] x86/mm: add support for 5-level paging for KASLR

With 5-level paging randomization happens on P4D level instead of PUD. Maximum amount of physical memory also bumped to 52-bits for 5-level paging. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/kaslr.c | 82 - 1 file changed, 63

Re: [PATCH v4 23/36] media: imx: Add MIPI CSI-2 Receiver subdev driver

On Fri, 2017-02-17 at 11:47 +0100, Philipp Zabel wrote: > On Wed, 2017-02-15 at 18:19 -0800, Steve Longerbeam wrote: > > Adds MIPI CSI-2 Receiver subdev driver. This subdev is required > > for sensors with a MIPI CSI2 interface. > > > > Signed-off-by: Steve Longerbeam

Re: [PATCH v4 23/36] media: imx: Add MIPI CSI-2 Receiver subdev driver

On Fri, 2017-02-17 at 11:47 +0100, Philipp Zabel wrote: > On Wed, 2017-02-15 at 18:19 -0800, Steve Longerbeam wrote: > > Adds MIPI CSI-2 Receiver subdev driver. This subdev is required > > for sensors with a MIPI CSI2 interface. > > > > Signed-off-by: Steve Longerbeam > > --- > >

[PATCHv3 24/33] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL

Extends pagetable headers to support new paging mode. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/pgtable_64.h | 11 +++ arch/x86/include/asm/pgtable_64_types.h | 20 +++ arch/x86/include/asm/pgtable_types.h| 10

[PATCHv3 24/33] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL

Extends pagetable headers to support new paging mode. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/pgtable_64.h | 11 +++ arch/x86/include/asm/pgtable_64_types.h | 20 +++ arch/x86/include/asm/pgtable_types.h| 10 +- arch/x86/mm/pgtable.c

[PATCHv3 06/33] mm: convert generic code to 5-level paging

Convert all non-architecture-specific code to 5-level paging. It's mostly mechanical adding handling one more page table level in places where we deal with pud_t. Signed-off-by: Kirill A. Shutemov --- drivers/misc/sgi-gru/grufault.c | 9 +- fs/userfaultfd.c

[PATCHv3 06/33] mm: convert generic code to 5-level paging

Convert all non-architecture-specific code to 5-level paging. It's mostly mechanical adding handling one more page table level in places where we deal with pud_t. Signed-off-by: Kirill A. Shutemov --- drivers/misc/sgi-gru/grufault.c | 9 +- fs/userfaultfd.c| 6 +-

[PATCHv3 14/33] x86/kexec: support p4d_t

Handle additional page table level in kexec code. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/kexec.h | 1 + arch/x86/kernel/machine_kexec_32.c | 4 +++- arch/x86/kernel/machine_kexec_64.c | 14 -- 3 files changed, 16

[PATCHv3 25/33] x86/dump_pagetables: support 5-level paging

Simple extension to support one more page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/dump_pagetables.c | 49 --- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git

[PATCHv3 09/33] x86: trivial portion of 5-level paging conversion

This patch covers simple cases only. Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/tboot.c| 6 +- arch/x86/kernel/vm86_32.c | 6 +- arch/x86/mm/fault.c| 39 +-- arch/x86/mm/init_32.c

[PATCHv3 14/33] x86/kexec: support p4d_t

Handle additional page table level in kexec code. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/kexec.h | 1 + arch/x86/kernel/machine_kexec_32.c | 4 +++- arch/x86/kernel/machine_kexec_64.c | 14 -- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git

[PATCHv3 25/33] x86/dump_pagetables: support 5-level paging

Simple extension to support one more page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/dump_pagetables.c | 49 --- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/arch/x86/mm/dump_pagetables.c

[PATCHv3 09/33] x86: trivial portion of 5-level paging conversion

This patch covers simple cases only. Signed-off-by: Kirill A. Shutemov --- arch/x86/kernel/tboot.c| 6 +- arch/x86/kernel/vm86_32.c | 6 +- arch/x86/mm/fault.c| 39 +-- arch/x86/mm/init_32.c | 22

[PATCHv3 29/33] x86/mm: add sync_global_pgds() for configuration with 5-level paging

This basically restores slightly modified version of original sync_global_pgds() which we had before foldedl p4d was introduced. The only modification is protection against 'address' overflow. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/init_64.c | 37

[PATCHv3 29/33] x86/mm: add sync_global_pgds() for configuration with 5-level paging

This basically restores slightly modified version of original sync_global_pgds() which we had before foldedl p4d was introduced. The only modification is protection against 'address' overflow. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/init_64.c | 37

[PATCHv3 12/33] x86/mm: add support of p4d_t in vmalloc_fault()

With 4-level paging copying happens on p4d level, as we have pgd_none() always false when p4d_t folded. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/fault.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git

[PATCHv3 12/33] x86/mm: add support of p4d_t in vmalloc_fault()

With 4-level paging copying happens on p4d level, as we have pgd_none() always false when p4d_t folded. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/fault.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c

[PATCHv3 20/33] x86: detect 5-level paging support

5-level paging support is required from hardware when compiled with CONFIG_X86_5LEVEL=y. We may implement runtime switch support later. Signed-off-by: Kirill A. Shutemov --- arch/x86/boot/cpucheck.c | 9 + arch/x86/boot/cpuflags.c

[PATCHv3 20/33] x86: detect 5-level paging support

5-level paging support is required from hardware when compiled with CONFIG_X86_5LEVEL=y. We may implement runtime switch support later. Signed-off-by: Kirill A. Shutemov --- arch/x86/boot/cpucheck.c | 9 + arch/x86/boot/cpuflags.c | 12 ++--

[PATCHv3 05/33] asm-generic: introduce

Like with pgtable-nopud.h for 4-level paging, this new header is base for converting an architectures to properly folded p4d_t level. Signed-off-by: Kirill A. Shutemov --- include/asm-generic/pgtable-nop4d.h | 56 +

[PATCHv3 05/33] asm-generic: introduce

Like with pgtable-nopud.h for 4-level paging, this new header is base for converting an architectures to properly folded p4d_t level. Signed-off-by: Kirill A. Shutemov --- include/asm-generic/pgtable-nop4d.h | 56 + include/asm-generic/pgtable-nopud.h | 43

[PATCHv3 22/33] x86/mm: define virtual memory map for 5-level paging

The first part of memory map (up to %esp fixup) simply scales existing map for 4-level paging by factor of 9 -- number of bits addressed by additional page table level. The rest of the map is uncahnged. Signed-off-by: Kirill A. Shutemov ---

[PATCHv3 22/33] x86/mm: define virtual memory map for 5-level paging

The first part of memory map (up to %esp fixup) simply scales existing map for 4-level paging by factor of 9 -- number of bits addressed by additional page table level. The rest of the map is uncahnged. Signed-off-by: Kirill A. Shutemov --- Documentation/x86/x86_64/mm.txt | 33

[PATCHv3 30/33] x86/mm: make kernel_physical_mapping_init() support 5-level paging

Properly populate addition pagetable level if CONFIG_X86_5LEVEL is enabled. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/init_64.c | 71 --- 1 file changed, 62 insertions(+), 9 deletions(-) diff --git

[PATCHv3 02/33] asm-generic: introduce 5level-fixup.h

We are going to switch core MM to 5-level paging abstraction. This is preparation step which adds As with 4level-fixup.h, the new header allows quickly make all architectures compatible with 5-level paging in core MM. In long run we would like to switch architectures to properly folded p4d

[PATCHv3 15/33] x86/efi: handle p4d in EFI pagetables

Allocate additional page table level and change efi_sync_low_kernel_mappings() to make syncing logic work with additional page table level. Signed-off-by: Kirill A. Shutemov Cc: Matt Fleming --- arch/x86/platform/efi/efi_64.c | 33

[PATCHv3 02/33] asm-generic: introduce 5level-fixup.h

We are going to switch core MM to 5-level paging abstraction. This is preparation step which adds As with 4level-fixup.h, the new header allows quickly make all architectures compatible with 5-level paging in core MM. In long run we would like to switch architectures to properly folded p4d

[PATCHv3 15/33] x86/efi: handle p4d in EFI pagetables

Allocate additional page table level and change efi_sync_low_kernel_mappings() to make syncing logic work with additional page table level. Signed-off-by: Kirill A. Shutemov Cc: Matt Fleming --- arch/x86/platform/efi/efi_64.c | 33 +++-- 1 file changed, 23

[PATCHv3 30/33] x86/mm: make kernel_physical_mapping_init() support 5-level paging

Properly populate addition pagetable level if CONFIG_X86_5LEVEL is enabled. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/init_64.c | 71 --- 1 file changed, 62 insertions(+), 9 deletions(-) diff --git a/arch/x86/mm/init_64.c

[PATCHv3 26/33] x86/kasan: extend to support 5-level paging

This patch bring support for non-folded additional page table level. Signed-off-by: Kirill A. Shutemov Cc: Dmitry Vyukov

[PATCHv3 00/33] 5-level paging

Here is v3 of 5-level paging patchset. Please review and consider applying. == Overview == x86-64 is currently limited to 256 TiB of virtual address space and 64 TiB of physical address space. We are already bumping into this limit: some vendors offers servers with 64 TiB of memory today. To

[PATCHv3 17/33] x86/kasan: prepare clear_pgds() to switch to

With folded p4d, pgd_clear() is nop. Change clear_pgds() to use p4d_clear() instead. Signed-off-by: Kirill A. Shutemov Cc: Dmitry Vyukov --- arch/x86/mm/kasan_init_64.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff

[PATCHv3 26/33] x86/kasan: extend to support 5-level paging

This patch bring support for non-folded additional page table level. Signed-off-by: Kirill A. Shutemov Cc: Dmitry Vyukov = 5 && i < PTRS_PER_P4D; i++) + kasan_zero_p4d[i] = __p4d(p4d_val); + kasan_map_early_shadow(early_level4_pgt);

[PATCHv3 00/33] 5-level paging

Here is v3 of 5-level paging patchset. Please review and consider applying. == Overview == x86-64 is currently limited to 256 TiB of virtual address space and 64 TiB of physical address space. We are already bumping into this limit: some vendors offers servers with 64 TiB of memory today. To

[PATCHv3 17/33] x86/kasan: prepare clear_pgds() to switch to

With folded p4d, pgd_clear() is nop. Change clear_pgds() to use p4d_clear() instead. Signed-off-by: Kirill A. Shutemov Cc: Dmitry Vyukov --- arch/x86/mm/kasan_init_64.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/kasan_init_64.c

[PATCHv3 10/33] x86/gup: add 5-level paging support

It's simply extension for one more page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/gup.c | 33 +++-- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index

[PATCHv3 10/33] x86/gup: add 5-level paging support

It's simply extension for one more page table level. Signed-off-by: Kirill A. Shutemov --- arch/x86/mm/gup.c | 33 +++-- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index 0d4fb3ebbbac..27b92430a8cd 100644 ---

RE: [PATCH 2/2] [2/2] mmc: sdhci-cadence: Update PHY delay configuration

> -Original Message- > From: Ulf Hansson [mailto:ulf.hans...@linaro.org] > Sent: 16 February, 2017 4:10 PM > Subject: Re: [PATCH 2/2] [2/2] mmc: sdhci-cadence: Update PHY delay > configuration > > On 16 February 2017 at 14:06, Piotr Sroka wrote: > > DTS properties are

RE: [PATCH 2/2] [2/2] mmc: sdhci-cadence: Update PHY delay configuration

> -Original Message- > From: Ulf Hansson [mailto:ulf.hans...@linaro.org] > Sent: 16 February, 2017 4:10 PM > Subject: Re: [PATCH 2/2] [2/2] mmc: sdhci-cadence: Update PHY delay > configuration > > On 16 February 2017 at 14:06, Piotr Sroka wrote: > > DTS properties are used instead of

Re: [RFC PATCH 2/2] mm/sparse: add last_section_nr in sparse_init() to reduce some iteration cycle

On Mon, Feb 13, 2017 at 9:03 PM, Wei Yang wrote: > On Sat, Feb 11, 2017 at 10:24 AM, Tejun Heo wrote: >> >> Hello, >> > > Hi, Tejun > > Sorry for the delay, my gmail client seems to facing some problem. > I can't see latest mails. So I have to use the

Re: [RFC PATCH 2/2] mm/sparse: add last_section_nr in sparse_init() to reduce some iteration cycle

On Mon, Feb 13, 2017 at 9:03 PM, Wei Yang wrote: > On Sat, Feb 11, 2017 at 10:24 AM, Tejun Heo wrote: >> >> Hello, >> > > Hi, Tejun > > Sorry for the delay, my gmail client seems to facing some problem. > I can't see latest mails. So I have to use the web client and reply. > >> On Sat, Feb 11,

Re: [PATCH 07/10] perf: Directly pass PERF_AUX_* flags to perf_aux_output_end

Will Deacon writes: > On Fri, Feb 17, 2017 at 03:40:23PM +0200, Alexander Shishkin wrote: >> Will Deacon writes: >> >> > @@ -485,7 +485,8 @@ int intel_bts_interrupt(void) >> >return handled; >> > >> >perf_aux_output_end(>handle,

Re: [PATCH 07/10] perf: Directly pass PERF_AUX_* flags to perf_aux_output_end

Will Deacon writes: > On Fri, Feb 17, 2017 at 03:40:23PM +0200, Alexander Shishkin wrote: >> Will Deacon writes: >> >> > @@ -485,7 +485,8 @@ int intel_bts_interrupt(void) >> >return handled; >> > >> >perf_aux_output_end(>handle, local_xchg(>data_size, 0), >> > -

Re: [PATCH 26/35] drivers/oprofile: Convert remaining uses of pr_warning to pr_warn

On 16.02.17 23:11:39, Joe Perches wrote: > To enable eventual removal of pr_warning > > This makes pr_warn use consistent for drivers/oprofile > > Prior to this patch, there were 2 uses of pr_warning and > 0 uses of pr_warn in drivers/oprofile > > Signed-off-by: Joe Perches

Re: [PATCH 26/35] drivers/oprofile: Convert remaining uses of pr_warning to pr_warn

On 16.02.17 23:11:39, Joe Perches wrote: > To enable eventual removal of pr_warning > > This makes pr_warn use consistent for drivers/oprofile > > Prior to this patch, there were 2 uses of pr_warning and > 0 uses of pr_warn in drivers/oprofile > > Signed-off-by: Joe Perches Acked-by: Robert

Re: [PATCH 09/35] x86: Convert remaining uses of pr_warning to pr_warn

On 16.02.17 23:11:22, Joe Perches wrote: > To enable eventual removal of pr_warning > > This makes pr_warn use consistent for arch/x86 > > Prior to this patch, there were 46 uses of pr_warning and > 122 uses of pr_warn in arch/x86 > > Miscellanea: > > o Coalesce a few formats and realign

Re: [PATCH 09/35] x86: Convert remaining uses of pr_warning to pr_warn

On 16.02.17 23:11:22, Joe Perches wrote: > To enable eventual removal of pr_warning > > This makes pr_warn use consistent for arch/x86 > > Prior to this patch, there were 46 uses of pr_warning and > 122 uses of pr_warn in arch/x86 > > Miscellanea: > > o Coalesce a few formats and realign

Re: [PREVIEW 10/10] linkage: add .cfi_{start/end}proc to ENTRY/ENDPROC

On Fri, Feb 17, 2017 at 02:36:15PM +0100, Jiri Slaby wrote: > On 02/17/2017, 02:16 PM, Josh Poimboeuf wrote: > > On Fri, Feb 17, 2017 at 11:47:57AM +0100, Jiri Slaby wrote: > >> This is just a preview, not to merged now, only later with DWARF > >> unwinder series. This is what the series will

Re: [PREVIEW 10/10] linkage: add .cfi_{start/end}proc to ENTRY/ENDPROC

On Fri, Feb 17, 2017 at 02:36:15PM +0100, Jiri Slaby wrote: > On 02/17/2017, 02:16 PM, Josh Poimboeuf wrote: > > On Fri, Feb 17, 2017 at 11:47:57AM +0100, Jiri Slaby wrote: > >> This is just a preview, not to merged now, only later with DWARF > >> unwinder series. This is what the series will

Re: [PATCH 2/2] x86/xen: use capabilities instead of fake cpuid values

On 02/17/2017 02:36 AM, Juergen Gross wrote: When running as pv domain xen_cpuid() is being used instead of native_cpuid(). In xen_cpuid() the aperf/mperf feature is indicated as not being present by special casing the related cpuid leaf. Instead of delivering fake cpuid values clear the cpu

Re: [PATCH 2/2] x86/xen: use capabilities instead of fake cpuid values

On 02/17/2017 02:36 AM, Juergen Gross wrote: When running as pv domain xen_cpuid() is being used instead of native_cpuid(). In xen_cpuid() the aperf/mperf feature is indicated as not being present by special casing the related cpuid leaf. Instead of delivering fake cpuid values clear the cpu

Re: v4.10-rc8 (-rc6) boot regression on Intel desktop, does not boot after cold boots, boots after reboot

On Thu, Feb 16, 2017 at 08:34:45PM +0100, Thomas Gleixner wrote: > On Thu, 16 Feb 2017, Frederic Weisbecker wrote: > > On Thu, Feb 16, 2017 at 10:20:14AM -0800, Linus Torvalds wrote: > > > On Thu, Feb 16, 2017 at 10:13 AM, Frederic Weisbecker > > > wrote: > > > > > > > > I

Re: v4.10-rc8 (-rc6) boot regression on Intel desktop, does not boot after cold boots, boots after reboot

On Thu, Feb 16, 2017 at 08:34:45PM +0100, Thomas Gleixner wrote: > On Thu, 16 Feb 2017, Frederic Weisbecker wrote: > > On Thu, Feb 16, 2017 at 10:20:14AM -0800, Linus Torvalds wrote: > > > On Thu, Feb 16, 2017 at 10:13 AM, Frederic Weisbecker > > > wrote: > > > > > > > > I haven't followed the

Re: [PATCH V3 1/4] mm: Define coherent device memory (CDM) node

Hi Anshuman, I have a few questions about coherent device memory. On Wed, Feb 15, 2017 at 8:07 PM, Anshuman Khandual wrote: > There are certain devices like specialized accelerator, GPU cards, network > cards, FPGA cards etc which might contain onboard memory which

Re: [PATCH V3 1/4] mm: Define coherent device memory (CDM) node

Hi Anshuman, I have a few questions about coherent device memory. On Wed, Feb 15, 2017 at 8:07 PM, Anshuman Khandual wrote: > There are certain devices like specialized accelerator, GPU cards, network > cards, FPGA cards etc which might contain onboard memory which is coherent > along with the

[PATCH 4/5] perf stat: Add -a as a default target

Boris asked for default -a option in case we monitor only uncore events. While implementing that I thought it might be actually useful to make it overall default. # perf stat Warning: No target specified, setting system-wide collection (-a). ... Requested-by: Borislav Petkov

[PATCH 4/5] perf stat: Add -a as a default target

Boris asked for default -a option in case we monitor only uncore events. While implementing that I thought it might be actually useful to make it overall default. # perf stat Warning: No target specified, setting system-wide collection (-a). ... Requested-by: Borislav Petkov

[PATCH 5/5] perf record: Add -a as a default target

Adding system wide (-a) option as a default target if non is specified. # perf record Warning: No target specified, setting system-wide collection (-a). ... Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Namhyung Kim Cc: Peter

[PATCH 3/5] perf tools: Fail on using multiple bits long terms without value

Currently we allow not to specify value for numeric terms and we set them to value 1. This was originaly meant just for single bit terms to allow user to type: $ perf record -e 'cpu/cpu-cycles,any' instead of: $ perf record -e 'cpu/cpu-cycles,any=1' However it works also for multi bits

[PATCH 3/5] perf tools: Fail on using multiple bits long terms without value

Currently we allow not to specify value for numeric terms and we set them to value 1. This was originaly meant just for single bit terms to allow user to type: $ perf record -e 'cpu/cpu-cycles,any' instead of: $ perf record -e 'cpu/cpu-cycles,any=1' However it works also for multi bits

[PATCH 5/5] perf record: Add -a as a default target

Adding system wide (-a) option as a default target if non is specified. # perf record Warning: No target specified, setting system-wide collection (-a). ... Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Namhyung Kim Cc: Peter Zijlstra Link:

[PATCH 2/5] perf tools: Move new_term arguments into struct parse_events_term template

We need to add yet another parameter to new_term function in following patch, so it's better to move first all the current params into template struct parse_events_term and use it as a single argument. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Namhyung

[PATCH 2/5] perf tools: Move new_term arguments into struct parse_events_term template

We need to add yet another parameter to new_term function in following patch, so it's better to move first all the current params into template struct parse_events_term and use it as a single argument. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Namhyung Kim Cc: Peter Zijlstra Link:

[PATCH 0/5] perf tools: Few fixes

hi, sending some assorted fixes. Available also here: git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git perf/fixes thanks, jirka --- Jiri Olsa (5): perf build: Add special fixdep cleaning rule perf tools: Move new_term arguments into struct parse_events_term template

[PATCH 0/5] perf tools: Few fixes

hi, sending some assorted fixes. Available also here: git://git.kernel.org/pub/scm/linux/kernel/git/jolsa/perf.git perf/fixes thanks, jirka --- Jiri Olsa (5): perf build: Add special fixdep cleaning rule perf tools: Move new_term arguments into struct parse_events_term template

[PATCH 1/5] perf build: Add special fixdep cleaning rule

From: Jiri Olsa Ingo reported following build failure: On Sat, Feb 11, 2017 at 12:12:34PM +0100, Ingo Molnar wrote: > > So I had this oldish 32-bit 15.10 Ubuntu installation around (fully updated), > and > trying to build perf gave me: > > deimos:~/tip/tools/perf> make >

[PATCH 1/5] perf build: Add special fixdep cleaning rule

From: Jiri Olsa Ingo reported following build failure: On Sat, Feb 11, 2017 at 12:12:34PM +0100, Ingo Molnar wrote: > > So I had this oldish 32-bit 15.10 Ubuntu installation around (fully updated), > and > trying to build perf gave me: > > deimos:~/tip/tools/perf> make > BUILD: Doing 'make

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