[PATCH v2 4/6] irqchip: irq-mvebu-icu: new driver for Marvell ICU

The Marvell ICU unit is found in the CP110 block of the Marvell Armada 7K and 8K SoCs. It collects the wired interrupts of the devices located in the CP110 and turns them into SPI interrupts in the GIC located in the AP806 side of the SoC, by using a memory transaction. Until now, the ICU was

[PATCH v2 4/6] irqchip: irq-mvebu-icu: new driver for Marvell ICU

The Marvell ICU unit is found in the CP110 block of the Marvell Armada 7K and 8K SoCs. It collects the wired interrupts of the devices located in the CP110 and turns them into SPI interrupts in the GIC located in the AP806 side of the SoC, by using a memory transaction. Until now, the ICU was

Re: [PATCH] rpmsg: Release rpmsg devices in backends

The rpmsg devices are allocated in the backends and as such must be freed there as well. Signed-off-by: Bjorn Andersson --- drivers/rpmsg/qcom_smd.c | 11 +++ drivers/rpmsg/virtio_rpmsg_bus.c | 9 + 2 files changed, 20 insertions(+) diff

RE: [PATCH v4 3/3] USB3/DWC3: Enable undefined length INCR burst type

Hi, Jerry Huang writes: >> Jerry Huang writes: >> >> >> -- >> >> >> 1.7.9.5 >> >> > Hi, Balbi and all guys, >> >> > Any comment for these patches? Can they be accepted? >> >> >> >> Rob had comments which you didn't reply yet. I cannot take this >> >>

RE: [PATCH v4 3/3] USB3/DWC3: Enable undefined length INCR burst type

Hi, Jerry Huang writes: >> Jerry Huang writes: >> >> >> -- >> >> >> 1.7.9.5 >> >> > Hi, Balbi and all guys, >> >> > Any comment for these patches? Can they be accepted? >> >> >> >> Rob had comments which you didn't reply yet. I cannot take this >> >> patchset yet ;-) >> >> >> > Balbi, >> > >>

Re: [PATCH] rpmsg: Release rpmsg devices in backends

The rpmsg devices are allocated in the backends and as such must be freed there as well. Signed-off-by: Bjorn Andersson --- drivers/rpmsg/qcom_smd.c | 11 +++ drivers/rpmsg/virtio_rpmsg_bus.c | 9 + 2 files changed, 20 insertions(+) diff --git

Re: [PATCH v5 00/17] fs: introduce new writeback error reporting and convert ext2 and ext4 to use it

On Thu, 2017-06-01 at 23:25 -0600, Ross Zwisler wrote: > On Wed, May 31, 2017 at 08:45:23AM -0400, Jeff Layton wrote: > > v5: don't retrofit old API over the new infrastructure > > add fstype flag to indicate how wb errors are tracked within that fs > > add more function variants that take

Re: [PATCH v5 00/17] fs: introduce new writeback error reporting and convert ext2 and ext4 to use it

On Thu, 2017-06-01 at 23:25 -0600, Ross Zwisler wrote: > On Wed, May 31, 2017 at 08:45:23AM -0400, Jeff Layton wrote: > > v5: don't retrofit old API over the new infrastructure > > add fstype flag to indicate how wb errors are tracked within that fs > > add more function variants that take

[PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC

[PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC

[PATCH v2 0/6] Add support for the ICU unit in Marvell Armada 7K/8K

Hello, The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which contains the CPU cores) and the CP (which contains most peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs, doubling the number of available peripherals. In terms of interrupt handling, all devices

[PATCH v2 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K

This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files to describe the ICU and GICP units, and use ICU interrupts for all devices in the CP110 blocks. Signed-off-by: Thomas Petazzoni --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi |

[PATCH v2 0/6] Add support for the ICU unit in Marvell Armada 7K/8K

Hello, The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which contains the CPU cores) and the CP (which contains most peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs, doubling the number of available peripherals. In terms of interrupt handling, all devices

[PATCH v2 6/6] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K

This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files to describe the ICU and GICP units, and use ICU interrupts for all devices in the CP110 blocks. Signed-off-by: Thomas Petazzoni --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 6 +++

Re: [PATCH] irqchip: aspeed: Add AST2500 compatible string

On 16/05/17 08:57, Andrew Jeffery wrote: > In addition to introducing the new compatible string the bindings > description is reworked to be more generic. > > Signed-off-by: Andrew Jeffery Queued for 4.13. Thanks, M. -- Jazz is not dead. It just smells funny...

Re: [PATCH] irqchip: aspeed: Add AST2500 compatible string

On 16/05/17 08:57, Andrew Jeffery wrote: > In addition to introducing the new compatible string the bindings > description is reworked to be more generic. > > Signed-off-by: Andrew Jeffery Queued for 4.13. Thanks, M. -- Jazz is not dead. It just smells funny...

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 02/06/2017 11:39, Sudeep Holla wrote: > > > On 02/06/17 10:25, Daniel Lezcano wrote: >> On 02/06/2017 11:20, Sudeep Holla wrote: >>> >>> >>> On 01/06/17 12:39, Daniel Lezcano wrote: Some hardware have clusters with different idle states. The current code does not support this

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 02/06/2017 11:39, Sudeep Holla wrote: > > > On 02/06/17 10:25, Daniel Lezcano wrote: >> On 02/06/2017 11:20, Sudeep Holla wrote: >>> >>> >>> On 01/06/17 12:39, Daniel Lezcano wrote: Some hardware have clusters with different idle states. The current code does not support this

Re: [PATCH 0/7] irqchip: constify irq_domain_ops

On 02/06/17 09:20, Tobias Klauser wrote: > Constify all remaining non-const instances of irq_domain_ops in the irqchip > drivers. These can be made const as they are never modified. > > Tobias Klauser (7): > irqchip/aspeed-vic: constify irq_domain_ops > irqchip/i8259: constify irq_domain_ops

Re: [PATCH v2 1/1] tty: add TIOCGPTPEER ioctl

On Fri, Jun 2, 2017 at 10:48 AM, Aleksa Sarai wrote: > When opening the slave end of a PTY, it is not possible for userspace to > safely ensure that /dev/pts/$num is actually a slave (in cases where the > mount namespace in which devpts was mounted is controlled by an > untrusted

Re: [PATCH 0/7] irqchip: constify irq_domain_ops

On 02/06/17 09:20, Tobias Klauser wrote: > Constify all remaining non-const instances of irq_domain_ops in the irqchip > drivers. These can be made const as they are never modified. > > Tobias Klauser (7): > irqchip/aspeed-vic: constify irq_domain_ops > irqchip/i8259: constify irq_domain_ops

Re: [PATCH v2 1/1] tty: add TIOCGPTPEER ioctl

On Fri, Jun 2, 2017 at 10:48 AM, Aleksa Sarai wrote: > When opening the slave end of a PTY, it is not possible for userspace to > safely ensure that /dev/pts/$num is actually a slave (in cases where the > mount namespace in which devpts was mounted is controlled by an > untrusted process). In

Re: [PATCH] perf: fix perf test case 14 result reporting

On 06/01/2017 11:04 PM, Jiri Olsa wrote: > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote: >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu: >>> Command perf test -v 14 (Setup struct perf_event_attr test) >>> always reports success even if the test

Re: [PATCH] perf: fix perf test case 14 result reporting

On 06/01/2017 11:04 PM, Jiri Olsa wrote: > On Thu, Jun 01, 2017 at 10:20:38AM -0300, Arnaldo Carvalho de Melo wrote: >> Em Thu, Jun 01, 2017 at 02:34:41PM +0200, Thomas Richter escreveu: >>> Command perf test -v 14 (Setup struct perf_event_attr test) >>> always reports success even if the test

Re: [PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

On 02/06/17 09:46, Brendan Higgins wrote: > The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 > separate I2C busses. This adds a dummy irqchip which maps the single > hardware interrupt to software interrupts for each of the busses. > > Signed-off-by: Brendan Higgins

Re: [PATCH v9 2/5] irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed

On 02/06/17 09:46, Brendan Higgins wrote: > The Aspeed 24XX/25XX chips share a single hardware interrupt across 14 > separate I2C busses. This adds a dummy irqchip which maps the single > hardware interrupt to software interrupts for each of the busses. > > Signed-off-by: Brendan Higgins > --- >

[PATCH v3 4/8] nvmet: add uuid field to nvme_ns and populate via configfs

Add the UUID field from the NVMe Namespace Identification Descriptor to the nvmet_ns structure and allow it's population via configfs. Signed-off-by: Johannes Thumshirn --- drivers/nvme/target/configfs.c | 31 +++ 1 file changed, 31 insertions(+)

[PATCH v3 4/8] nvmet: add uuid field to nvme_ns and populate via configfs

Add the UUID field from the NVMe Namespace Identification Descriptor to the nvmet_ns structure and allow it's population via configfs. Signed-off-by: Johannes Thumshirn --- drivers/nvme/target/configfs.c | 31 +++ 1 file changed, 31 insertions(+) diff --git

[PATCH v3 3/8] nvmet: implement namespace identify descriptor list

A NVMe Identify NS command with a CNS value of '3' is expecting a list of Namespace Identification Descriptor structures to be returned to the host for the namespace requested in the namespace identify command. This Namespace Identification Descriptor structure consists of the type of the

[PATCH v3 0/8] Implement NVMe Namespace Descriptor Identification

This patchset implemets NVMe Namespace Descriptor Identification as of NVMe 1.3. The Namespace Descriptor Identification allows a NVMe host to query several Namespace Identification mechanisms, such as EUI-64, NGUID and UUID from the target. If more than one value is set by the target, it can

[PATCH v3 3/8] nvmet: implement namespace identify descriptor list

A NVMe Identify NS command with a CNS value of '3' is expecting a list of Namespace Identification Descriptor structures to be returned to the host for the namespace requested in the namespace identify command. This Namespace Identification Descriptor structure consists of the type of the

[PATCH v3 0/8] Implement NVMe Namespace Descriptor Identification

This patchset implemets NVMe Namespace Descriptor Identification as of NVMe 1.3. The Namespace Descriptor Identification allows a NVMe host to query several Namespace Identification mechanisms, such as EUI-64, NGUID and UUID from the target. If more than one value is set by the target, it can

[PATCH v3 7/8] nvmet: allow overriding the NVMe VS via configfs

Allow overriding the announced NVMe Version of a via configfs. This is particularly helpful when debugging new features for the host or target side without bumping the hard coded version (as the target might not be fully compliant to the announced version yet). Signed-off-by: Johannes Thumshirn

[PATCH v3 7/8] nvmet: allow overriding the NVMe VS via configfs

Allow overriding the announced NVMe Version of a via configfs. This is particularly helpful when debugging new features for the host or target side without bumping the hard coded version (as the target might not be fully compliant to the announced version yet). Signed-off-by: Johannes Thumshirn

[PATCH v3 6/8] nvme: provide UUID value to userspace

Now that we have a way for getting the UUID from a target, provide it to userspace as well. Unfortunately there is already a sysfs attribute called UUID which is a misnomer as it holds the NGUID value. So instead of creating yet another wrong name, create a new 'nguid' sysfs attribute for the

Re: [PATCH RFC 0/2] KVM: s390: avoid having to enable vm.alloc_pgste

On Fri, 2 Jun 2017 09:02:10 +0200 Heiko Carstens wrote: > On Thu, Jun 01, 2017 at 12:46:51PM +0200, Martin Schwidefsky wrote: > > > Unfortunately, converting all page tables to 4k pgste page tables is > > > not possible without provoking various race conditions. > >

[PATCH v3 6/8] nvme: provide UUID value to userspace

Now that we have a way for getting the UUID from a target, provide it to userspace as well. Unfortunately there is already a sysfs attribute called UUID which is a misnomer as it holds the NGUID value. So instead of creating yet another wrong name, create a new 'nguid' sysfs attribute for the

Re: [PATCH RFC 0/2] KVM: s390: avoid having to enable vm.alloc_pgste

On Fri, 2 Jun 2017 09:02:10 +0200 Heiko Carstens wrote: > On Thu, Jun 01, 2017 at 12:46:51PM +0200, Martin Schwidefsky wrote: > > > Unfortunately, converting all page tables to 4k pgste page tables is > > > not possible without provoking various race conditions. > > > > That is one approach

[PATCH v3 1/8] nvme: introduce NVMe Namespace Identification Descriptor structures

Signed-off-by: Johannes Thumshirn Reviewed-by: Max Gurtovoy --- include/linux/nvme.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/nvme.h b/include/linux/nvme.h index b625bacf37ef..afa6ef484e50 100644 ---

Re: [PATCH 04/12] fs: ceph: CURRENT_TIME with ktime_get_real_ts()

On Fri, Jun 2, 2017 at 4:09 AM, Yan, Zheng wrote: > On Fri, Jun 2, 2017 at 8:57 AM, Deepa Dinamani wrote: >> On Thu, Jun 1, 2017 at 5:36 PM, John Stultz wrote: >>> On Thu, Jun 1, 2017 at 5:26 PM, Yan, Zheng

[PATCH v3 8/8] nvmet: use NVME_IDENTIFY_DATA_SIZE

Use NVME_IDENTIFY_DATA_SIZE define instead of hard coding the magic 4096 value. Signed-off-by: Johannes Thumshirn --- drivers/nvme/target/admin-cmd.c | 4 ++-- drivers/nvme/target/discovery.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH v3 5/8] nvme: get list of namespace descriptors

If a target identifies itself as NVMe 1.3 compliant, try to get the list of Namespace Identification Descriptors and populate the UUID, NGUID and EUI64 fileds in the NVMe namespace structure with these values. Signed-off-by: Johannes Thumshirn --- drivers/nvme/host/core.c |

[PATCH v3 1/8] nvme: introduce NVMe Namespace Identification Descriptor structures

Signed-off-by: Johannes Thumshirn Reviewed-by: Max Gurtovoy --- include/linux/nvme.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/linux/nvme.h b/include/linux/nvme.h index b625bacf37ef..afa6ef484e50 100644 --- a/include/linux/nvme.h +++ b/include/linux/nvme.h

Re: [PATCH 04/12] fs: ceph: CURRENT_TIME with ktime_get_real_ts()

On Fri, Jun 2, 2017 at 4:09 AM, Yan, Zheng wrote: > On Fri, Jun 2, 2017 at 8:57 AM, Deepa Dinamani wrote: >> On Thu, Jun 1, 2017 at 5:36 PM, John Stultz wrote: >>> On Thu, Jun 1, 2017 at 5:26 PM, Yan, Zheng wrote: On Thu, Jun 1, 2017 at 6:22 PM, Arnd Bergmann wrote: > On Thu, Jun 1,

[PATCH v3 8/8] nvmet: use NVME_IDENTIFY_DATA_SIZE

Use NVME_IDENTIFY_DATA_SIZE define instead of hard coding the magic 4096 value. Signed-off-by: Johannes Thumshirn --- drivers/nvme/target/admin-cmd.c | 4 ++-- drivers/nvme/target/discovery.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/nvme/target/admin-cmd.c

[PATCH v3 5/8] nvme: get list of namespace descriptors

If a target identifies itself as NVMe 1.3 compliant, try to get the list of Namespace Identification Descriptors and populate the UUID, NGUID and EUI64 fileds in the NVMe namespace structure with these values. Signed-off-by: Johannes Thumshirn --- drivers/nvme/host/core.c | 87

[PATCH v3 2/8] nvme: rename uuid to nguid in nvme_ns

The uuid field in the nvme_ns structure represents the nguid field from the identify namespace command. And as NVMe 1.3 introduced an UUID in the NVMe Namespace Identification Descriptor this will collide. So rename the uuid to nguid to prevent any further confusion. Unfortunately we export the

[PATCH v3 2/8] nvme: rename uuid to nguid in nvme_ns

The uuid field in the nvme_ns structure represents the nguid field from the identify namespace command. And as NVMe 1.3 introduced an UUID in the NVMe Namespace Identification Descriptor this will collide. So rename the uuid to nguid to prevent any further confusion. Unfortunately we export the

Re: [PATCH v4 0/3] USB Audio Gadget refactoring

Hi, Ruslan Bilovol writes: > I came to this patch series when wanted to do two things: > - use UAC1 as virtual ALSA sound card on gadget side, >just like UAC2 is used so it's possible to do rate >resampling > - have both playback/capture support in UAC1 > >

Re: [PATCH v4 0/3] USB Audio Gadget refactoring

Hi, Ruslan Bilovol writes: > I came to this patch series when wanted to do two things: > - use UAC1 as virtual ALSA sound card on gadget side, >just like UAC2 is used so it's possible to do rate >resampling > - have both playback/capture support in UAC1 > > Since I wanted to have same

[PATCH] net-procfs: Use vsnprintf extension %phN

Save a bit of code by using the kernel extension. $ size net/core/net-procfs.o* textdata bss dec hex filename 3701 120 03821 eed net/core/net-procfs.o.new 3764 120 03884 f2c net/core/net-procfs.o.old Signed-off-by: Joe Perches

[PATCH] net-procfs: Use vsnprintf extension %phN

Save a bit of code by using the kernel extension. $ size net/core/net-procfs.o* textdata bss dec hex filename 3701 120 03821 eed net/core/net-procfs.o.new 3764 120 03884 f2c net/core/net-procfs.o.old Signed-off-by: Joe Perches ---

Re: [PATCH 2/5] powerpc/mm: split store_updates_sp() in two parts in do_page_fault()

Le 02/06/2017 à 11:26, Michael Ellerman a écrit : Christophe Leroy writes: Only the get_user() in store_updates_sp() has to be done outside the mm semaphore. All the comparison can be done within the semaphore, so only when really needed. As we got a DSI exception,

Re: [PATCH 2/5] powerpc/mm: split store_updates_sp() in two parts in do_page_fault()

Le 02/06/2017 à 11:26, Michael Ellerman a écrit : Christophe Leroy writes: Only the get_user() in store_updates_sp() has to be done outside the mm semaphore. All the comparison can be done within the semaphore, so only when really needed. As we got a DSI exception, the address pointed by

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 02/06/17 10:25, Daniel Lezcano wrote: > On 02/06/2017 11:20, Sudeep Holla wrote: >> >> >> On 01/06/17 12:39, Daniel Lezcano wrote: >>> Some hardware have clusters with different idle states. The current code >>> does >>> not support this and fails as it expects all the idle states to be >>>

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 02/06/17 10:25, Daniel Lezcano wrote: > On 02/06/2017 11:20, Sudeep Holla wrote: >> >> >> On 01/06/17 12:39, Daniel Lezcano wrote: >>> Some hardware have clusters with different idle states. The current code >>> does >>> not support this and fails as it expects all the idle states to be >>>

Re: [PATCH 3/6] mfd: hi6421v530: add support for HiSilicon Hi6421v530

On Tue, May 30, 2017 at 3:36 PM, Lee Jones wrote: > On Fri, 26 May 2017, Guodong Xu wrote: > >> Add support for HiSilicon Hi6421v530 PMIC. Hi6421v530 communicates with >> main SoC via memory-mapped I/O. >> >> Hi6421v530 and Hi6421 are PMIC chips from the same vendor,

Re: [PATCH v5 09/10] drm/atmel-hlcdc: Use crtc->mode_valid() callback

On Thu, 25 May 2017 15:19:21 +0100 Jose Abreu wrote: > Now that we have a callback to check if crtc supports a given mode > we can use it in atmel-hlcdc so that we restrict the number of probbed > modes to the ones we can actually display. > > Also, remove the

Re: [PATCH v5 09/10] drm/atmel-hlcdc: Use crtc->mode_valid() callback

On Thu, 25 May 2017 15:19:21 +0100 Jose Abreu wrote: > Now that we have a callback to check if crtc supports a given mode > we can use it in atmel-hlcdc so that we restrict the number of probbed > modes to the ones we can actually display. > > Also, remove the mode_fixup() callback as this is

Re: [PATCH 3/6] mfd: hi6421v530: add support for HiSilicon Hi6421v530

On Tue, May 30, 2017 at 3:36 PM, Lee Jones wrote: > On Fri, 26 May 2017, Guodong Xu wrote: > >> Add support for HiSilicon Hi6421v530 PMIC. Hi6421v530 communicates with >> main SoC via memory-mapped I/O. >> >> Hi6421v530 and Hi6421 are PMIC chips from the same vendor, HiSilicon, but >> at

Re: [PATCH v4 2/3] usb: gadget: f_uac2: split out audio core

Hi, Ruslan Bilovol writes: > Abstract the peripheral side ALSA sound card code from > the f_uac2 function into a component that can be called > by various functions, so the various flavors can be split > apart and selectively reused. > > Visible changes: > - add

Re: [PATCH v4 2/3] usb: gadget: f_uac2: split out audio core

Hi, Ruslan Bilovol writes: > Abstract the peripheral side ALSA sound card code from > the f_uac2 function into a component that can be called > by various functions, so the various flavors can be split > apart and selectively reused. > > Visible changes: > - add uac_params structure to pass

Re: [PATCH] virtio_net: lower limit on buffer size

Hello! On 6/2/2017 2:56 AM, Michael S. Tsirkin wrote: commit d85b758f72b0 "virtio_net: fix support for small rings" Commit d85b758f72b0 ("virtio_net: fix support for small rings") was supposed to increase the buffer size for small rings but had an unintentional side effect of decreasing

Re: [PATCH] virtio_net: lower limit on buffer size

Hello! On 6/2/2017 2:56 AM, Michael S. Tsirkin wrote: commit d85b758f72b0 "virtio_net: fix support for small rings" Commit d85b758f72b0 ("virtio_net: fix support for small rings") was supposed to increase the buffer size for small rings but had an unintentional side effect of decreasing

Re: [PATCH v2 2/6] Documentation: devicetree: add bindings to support ARM MHU doorbells

On 02/06/17 06:45, Jassi Brar wrote: > Hi Rob, > > On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote: >> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote: >>> > .../devicetree/bindings/mailbox/arm-mhu.txt| 46 > -- > 1

Re: [PATCH v2 2/6] Documentation: devicetree: add bindings to support ARM MHU doorbells

On 02/06/17 06:45, Jassi Brar wrote: > Hi Rob, > > On Wed, May 31, 2017 at 10:38 PM, Rob Herring wrote: >> On Thu, May 25, 2017 at 02:23:44PM +0100, Sudeep Holla wrote: >>> > .../devicetree/bindings/mailbox/arm-mhu.txt| 46 > -- > 1 file changed, 43

RE: [PATCH v6 6/6] drm/i915/gvt: Adding interface so user space can get the dma-buf

>-Original Message- >From: Alex Williamson [mailto:alex.william...@redhat.com] >Sent: Friday, June 02, 2017 11:35 AM >To: Chen, Xiaoguang >Cc: kra...@redhat.com; ch...@chris-wilson.co.uk; intel- >g...@lists.freedesktop.org; linux-kernel@vger.kernel.org;

RE: [PATCH v6 6/6] drm/i915/gvt: Adding interface so user space can get the dma-buf

>-Original Message- >From: Alex Williamson [mailto:alex.william...@redhat.com] >Sent: Friday, June 02, 2017 11:35 AM >To: Chen, Xiaoguang >Cc: kra...@redhat.com; ch...@chris-wilson.co.uk; intel- >g...@lists.freedesktop.org; linux-kernel@vger.kernel.org; >zhen...@linux.intel.com; Lv,

Re: [PATCH v8 4/5] i2c: aspeed: added driver for Aspeed I2C

I addressed all of your comments in my next revision except the one below. >> + time_left = wait_for_completion_timeout(>cmd_complete, >> + bus->adap.timeout); >> + >> + spin_lock_irqsave(>lock, flags); >> + bus->msgs = NULL; >> + if

Re: [PATCH v8 4/5] i2c: aspeed: added driver for Aspeed I2C

I addressed all of your comments in my next revision except the one below. >> + time_left = wait_for_completion_timeout(>cmd_complete, >> + bus->adap.timeout); >> + >> + spin_lock_irqsave(>lock, flags); >> + bus->msgs = NULL; >> + if

Re: [PATCH 2/5] powerpc/mm: split store_updates_sp() in two parts in do_page_fault()

Christophe Leroy writes: > Only the get_user() in store_updates_sp() has to be done outside > the mm semaphore. All the comparison can be done within the semaphore, > so only when really needed. > > As we got a DSI exception, the address pointed by regs->nip is >

Re: [PATCH 2/5] powerpc/mm: split store_updates_sp() in two parts in do_page_fault()

Christophe Leroy writes: > Only the get_user() in store_updates_sp() has to be done outside > the mm semaphore. All the comparison can be done within the semaphore, > so only when really needed. > > As we got a DSI exception, the address pointed by regs->nip is > obviously valid, otherwise we

[PATCH v2] ARM: dts: AM43XX: Remove min and max voltage values for dcdc3

dcdc3 supplies to DDR on AM43x series. When we set both min and max values to the same value. The regulator framework sets that particular voltage. This is bad as we are changing the ddr voltage when executing from ddr. Hence remove the min and max values. The ddr supply voltage shall be set from

[PATCH v2] ARM: dts: AM43XX: Remove min and max voltage values for dcdc3

dcdc3 supplies to DDR on AM43x series. When we set both min and max values to the same value. The regulator framework sets that particular voltage. This is bad as we are changing the ddr voltage when executing from ddr. Hence remove the min and max values. The ddr supply voltage shall be set from

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 02/06/2017 11:20, Sudeep Holla wrote: > > > On 01/06/17 12:39, Daniel Lezcano wrote: >> Some hardware have clusters with different idle states. The current code does >> not support this and fails as it expects all the idle states to be identical. >> >> Because of this, the Mediatek mtk8173

Re: [PATCH v5 0/3] drm/mali-dp: Add support for memory writeback engine

On Fri, Jun 02, 2017 at 10:34:26AM +0200, Boris Brezillon wrote: > On Mon, 15 May 2017 18:23:59 +0100 > Liviu Dudau wrote: > > > Hi, > > > > This series introduces support for Mali DP's memory writeback engine > > using the generic writeback connector support introduced in

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 02/06/2017 11:20, Sudeep Holla wrote: > > > On 01/06/17 12:39, Daniel Lezcano wrote: >> Some hardware have clusters with different idle states. The current code does >> not support this and fails as it expects all the idle states to be identical. >> >> Because of this, the Mediatek mtk8173

Re: [PATCH v5 0/3] drm/mali-dp: Add support for memory writeback engine

On Fri, Jun 02, 2017 at 10:34:26AM +0200, Boris Brezillon wrote: > On Mon, 15 May 2017 18:23:59 +0100 > Liviu Dudau wrote: > > > Hi, > > > > This series introduces support for Mali DP's memory writeback engine > > using the generic writeback connector support introduced in the > > "[PATCH v5

Re: [PATCH] gpio: mvebu: change compatible string for PWM support

Hi Ralph, On jeu., juin 01 2017, Ralph Sennhauser wrote: > As it turns out more than just Armada 370 and XP support using GPIO > lines as PWM lines. For example the Armada 38x family has the same > hardware support. As such "marvell,armada-370-xp-gpio" for the >

Re: [PATCH v4 2/3] dt-bindings: add bindings for rk3128 clock controller

Am Freitag, 2. Juni 2017, 09:47:24 CEST schrieb Elaine Zhang: > Add devicetree bindings for Rockchip cru which found on > Rockchip SoCs. > > Signed-off-by: Elaine Zhang the binding + binding header did receive an Acked-by: Rob Herring in v1

Re: [PATCH] gpio: mvebu: change compatible string for PWM support

Hi Ralph, On jeu., juin 01 2017, Ralph Sennhauser wrote: > As it turns out more than just Armada 370 and XP support using GPIO > lines as PWM lines. For example the Armada 38x family has the same > hardware support. As such "marvell,armada-370-xp-gpio" for the > compatible string is a

Re: [PATCH v4 2/3] dt-bindings: add bindings for rk3128 clock controller

Am Freitag, 2. Juni 2017, 09:47:24 CEST schrieb Elaine Zhang: > Add devicetree bindings for Rockchip cru which found on > Rockchip SoCs. > > Signed-off-by: Elaine Zhang the binding + binding header did receive an Acked-by: Rob Herring in v1 already. Please carry these over when

Re: [PATCH] ARM: dts: Remove min and max voltage values for dcdc3

On Friday 02 June 2017 02:51 PM, Keerthy wrote: > dcdc3 supplies to DDR on AM43x series. When we set both > min and max values to the same value. The regulator framework > sets that particular voltage. This is bad as we are changing > the ddr voltage when executing from ddr. Hence remove the min

Re: [PATCH] ARM: dts: Remove min and max voltage values for dcdc3

On Friday 02 June 2017 02:51 PM, Keerthy wrote: > dcdc3 supplies to DDR on AM43x series. When we set both > min and max values to the same value. The regulator framework > sets that particular voltage. This is bad as we are changing > the ddr voltage when executing from ddr. Hence remove the min

[PATCH] ARM: dts: Remove min and max voltage values for dcdc3

dcdc3 supplies to DDR on AM43x series. When we set both min and max values to the same value. The regulator framework sets that particular voltage. This is bad as we are changing the ddr voltage when executing from ddr. Hence remove the min and max values. The ddr supply voltage shall be set from

[PATCH] ARM: dts: Remove min and max voltage values for dcdc3

dcdc3 supplies to DDR on AM43x series. When we set both min and max values to the same value. The regulator framework sets that particular voltage. This is bad as we are changing the ddr voltage when executing from ddr. Hence remove the min and max values. The ddr supply voltage shall be set from

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 01/06/17 12:39, Daniel Lezcano wrote: > Some hardware have clusters with different idle states. The current code does > not support this and fails as it expects all the idle states to be identical. > > Because of this, the Mediatek mtk8173 had to create the same idle state for a > big.Little

Re: [PATCH V2] ARM: cpuidle: Support asymmetric idle definition

On 01/06/17 12:39, Daniel Lezcano wrote: > Some hardware have clusters with different idle states. The current code does > not support this and fails as it expects all the idle states to be identical. > > Because of this, the Mediatek mtk8173 had to create the same idle state for a > big.Little

Re: sparc gcc 7.1 compile issue

On Wed, May 31, 2017 at 05:10:08PM -0400, David Miller wrote: > A fix for this is in Linus's tree and was submitted to -stable last > night: What remains to be fixed though is that the gcc-7 testsuite *reproducibly* kills the kernel on sparc64 when building with more than around 20 jobs:

Re: sparc gcc 7.1 compile issue

On Wed, May 31, 2017 at 05:10:08PM -0400, David Miller wrote: > A fix for this is in Linus's tree and was submitted to -stable last > night: What remains to be fixed though is that the gcc-7 testsuite *reproducibly* kills the kernel on sparc64 when building with more than around 20 jobs:

Re: [PATCH v2] um: Avoid longjmp/setjmp symbol clashes with libpthread.a

Am Freitag, den 02.06.2017, 10:30 +0200 schrieb Richard Weinberger: > Thomas, > > Am 02.06.2017 um 10:04 schrieb Thomas Meyer: > > Am Donnerstag, den 01.06.2017, 22:49 -0700 schrieb Florian > > Fainelli: > > I see this in the kernel log: > > > > [0.00] [ cut here

Re: [PATCH v2] um: Avoid longjmp/setjmp symbol clashes with libpthread.a

Am Freitag, den 02.06.2017, 10:30 +0200 schrieb Richard Weinberger: > Thomas, > > Am 02.06.2017 um 10:04 schrieb Thomas Meyer: > > Am Donnerstag, den 01.06.2017, 22:49 -0700 schrieb Florian > > Fainelli: > > I see this in the kernel log: > > > > [0.00] [ cut here

[PATCH 3/4 DONOTMERGE] ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi BPI-M3

From: Chen-Yu Tsai The BPI-M3 is an Allwinner A83T based SBC in the Bananapi/Bpi family. It is roughly the same form factor as the BPI-M1+, with roughly the same peripherals and connectors: - 2GB LPDDR3 DRAM - 8GB eMMC - Micro-SD card slot - HDMI output - Headset

[PATCH 3/4 DONOTMERGE] ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi BPI-M3

From: Chen-Yu Tsai The BPI-M3 is an Allwinner A83T based SBC in the Bananapi/Bpi family. It is roughly the same form factor as the BPI-M1+, with roughly the same peripherals and connectors: - 2GB LPDDR3 DRAM - 8GB eMMC - Micro-SD card slot - HDMI output - Headset (stereo + mic) jack

[PATCH 4/4DONOTMERGE] ARM: sun8i: bananapi-m3: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the bananapi m3 It uses an external PHY rtl8211e via RGMII. This patch create the needed emac and phy nodes. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 17 + 1 file changed,

[PATCH 4/4DONOTMERGE] ARM: sun8i: bananapi-m3: Enable dwmac-sun8i

The dwmac-sun8i hardware is present on the bananapi m3 It uses an external PHY rtl8211e via RGMII. This patch create the needed emac and phy nodes. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 17 + 1 file changed, 17 insertions(+) diff

[PATCH 2/4] ARM: dts: sun8i-a83t: add dwmac-sun8i ethernet driver

The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on the Allwinner a83t SoC Device-tree. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 28 1 file changed,

[PATCH 2/4] ARM: dts: sun8i-a83t: add dwmac-sun8i ethernet driver

The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed. This patch enable the dwmac-sun8i on the Allwinner a83t SoC Device-tree. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 28 1 file changed, 28 insertions(+) diff

[PATCH 1/4] ARM: dts: sun8i-a83t: Add dt node for the syscon control module

This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi

[PATCH 1/4] ARM: dts: sun8i-a83t: Add dt node for the syscon control module

This patch add the dt node for the syscon register present on the Allwinner A83T Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index

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