Add skeleton driver for v3 hw in hisi_sas_v3_hw.c
File hisi_sas_v3_hw.c will serve 2 purposes:
- probing and initialisation of the controller based on pci device
- hw layer for v3-based controllers
The controller design is quite similar to v2 hw in hip07.
However key differences include:
-All
From: Xiang Chen
Relocate get_ata_protocol() to a common location, as future
hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 7
From: Xiang Chen
There is a change for abort dev for v3 hw: add registers to configure
unaborted iptt for a device, and then inform this to logic.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
From: Xiang Chen
There is a change for abort dev for v3 hw: add registers to configure
unaborted iptt for a device, and then inform this to logic.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 2 ++
drivers/scsi/hisi_sas/hisi_sas_main.c |
On Wed, Jun 07, 2017 at 02:06:12PM +0530, Kishon Vijay Abraham I wrote:
> Document deprecation of "vmmc_aux" for io regulator and use of generic
> mmc binding "vqmmc" in omap-hsmmc.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
>
On Wed, Jun 07, 2017 at 02:06:12PM +0530, Kishon Vijay Abraham I wrote:
> Document deprecation of "vmmc_aux" for io regulator and use of generic
> mmc binding "vqmmc" in omap-hsmmc.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt | 2 +-
From: Xiang Chen
Add code for interface get_wideport_bitmap.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 +
1 file changed, 13 insertions(+)
diff
From: Xiang Chen
Add code for interface get_wideport_bitmap.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
On Thu, 25 May 2017 14:59:34 -0700
"Paul E. McKenney" wrote:
> Hello!
>
> This rather long series mostly removes unused features, shrinks the
> include/linux/rcupdate.h file's .i intermediate-output size, updates
> rcutorture testing, and supplies miscellaneous
On Thu, 25 May 2017 14:59:34 -0700
"Paul E. McKenney" wrote:
> Hello!
>
> This rather long series mostly removes unused features, shrinks the
> include/linux/rcupdate.h file's .i intermediate-output size, updates
> rcutorture testing, and supplies miscellaneous fixes. Branching proved
>
From: Xiang Chen
Add code to prepare internal abort command.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++
1 file changed, 38
From: Xiang Chen
Add code to prepare internal abort command.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
On Wed, Jun 07, 2017 at 02:32:47PM +0800, Yuantian Tang wrote:
> Signed-off-by: Tang Yuantian
> ---
> Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Rob Herring
On Wed, Jun 07, 2017 at 02:32:47PM +0800, Yuantian Tang wrote:
> Signed-off-by: Tang Yuantian
> ---
> Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Rob Herring
From: Xiang Chen
Add code to prepare SMP frame.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++
1 file changed, 74
From: Xiang Chen
Add code to prepare SMP frame.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
On 09/06/17 14:41, YT Shen wrote:
> On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
>> On 31/05/17 12:39, YT Shen wrote:
>>> This adds basic chip support for Mediatek 2712
>>>
>>> Signed-off-by: YT Shen
>>> ---
>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
On 09/06/17 14:41, YT Shen wrote:
> On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
>> On 31/05/17 12:39, YT Shen wrote:
>>> This adds basic chip support for Mediatek 2712
>>>
>>> Signed-off-by: YT Shen
>>> ---
>>> arch/arm64/boot/dts/mediatek/Makefile | 1 +
>>>
From: Xiang Chen
Add code to prepare SSP frame and deliver it to hardware.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 208 +
1
From: Xiang Chen
Add code to prepare SSP frame and deliver it to hardware.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 208 +
1 file changed, 208 insertions(+)
diff --git
From: Xiang Chen
Add code to initialise v3 hardware.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 277 +
1 file changed, 277
From: Xiang Chen
Add v3 cq interrupt handler slot_complete_v3_hw().
Note: The slot error handling needs to be further
refined in the future to examine all fields
in the error record, and handle appropriately,
instead of current solution - just report
From: Xiang Chen
Add code to initialise v3 hardware.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 277 +
1 file changed, 277 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
From: Xiang Chen
Add v3 cq interrupt handler slot_complete_v3_hw().
Note: The slot error handling needs to be further
refined in the future to examine all fields
in the error record, and handle appropriately,
instead of current solution - just report
SAS_OPEN_REJECT.
From: Xiang Chen
Add code to itct setup and free for v3 hw.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 114 +
1 file changed, 114
From: Xiang Chen
Add code to itct setup and free for v3 hw.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 114 +
1 file changed, 114 insertions(+)
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
On Tue, Jun 06, 2017 at 11:06:43AM -0700, Andrey Smirnov wrote:
> Add a driver for RAVE Supervisory Processor, an MCU implementing
> varoius bits of housekeeping functionality (watchdoging, backlight
> control, LED control, etc) on RAVE family of products by Zodiac
> Inflight Innovations.
>
>
This patchset adds support for the HiSilicon SAS controller
in the hip08 chipset.
The key difference compared to earlier chipsets is that the
controller is an integrated PCI endpoint in hip08.
As such, the controller is a pci device (not a platform device,
like v2 hw in hip07).
The driver is
On Tue, Jun 06, 2017 at 11:06:43AM -0700, Andrey Smirnov wrote:
> Add a driver for RAVE Supervisory Processor, an MCU implementing
> varoius bits of housekeeping functionality (watchdoging, backlight
> control, LED control, etc) on RAVE family of products by Zodiac
> Inflight Innovations.
>
>
This patchset adds support for the HiSilicon SAS controller
in the hip08 chipset.
The key difference compared to earlier chipsets is that the
controller is an integrated PCI endpoint in hip08.
As such, the controller is a pci device (not a platform device,
like v2 hw in hip07).
The driver is
Add the code to initialise the controller which is based on pci
device in hisi_sas_v3_hw.c
The core controller routines are still in hisi_sas_main.c; some
common initialisation functions are also exported from
hisi_sas_main.c
For pci-based controller, the device properties, like
phy count and
From: Xiang Chen
Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate,
and phy enable/disable.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39
Add the code to initialise the controller which is based on pci
device in hisi_sas_v3_hw.c
The core controller routines are still in hisi_sas_main.c; some
common initialisation functions are also exported from
hisi_sas_main.c
For pci-based controller, the device properties, like
phy count and
From: Xiang Chen
Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate,
and phy enable/disable.
Signed-off-by: John Garry
Signed-off-by: Xiang Chen
---
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++
1 file changed, 39 insertions(+)
diff
From: Xiang Chen
Currently hisi_hba.lock is locked to deliver and receive a
command to/from any hw queue. This causes much
contention at high data-rates.
To boost performance, lock on a per queue basis for
sending and receiving commands to/from hw.
Certain critical
From: Xiang Chen
Relocate get_ncq_tag_v2_hw() to a common location, as
future hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
From: Xiang Chen
Currently hisi_hba.lock is locked to deliver and receive a
command to/from any hw queue. This causes much
contention at high data-rates.
To boost performance, lock on a per queue basis for
sending and receiving commands to/from hw.
Certain critical regions still need to be
From: Xiang Chen
Relocate get_ncq_tag_v2_hw() to a common location, as
future hw versions will require it.
Also rename with "hisi_sas_" prefix for consistency.
Signed-off-by: Xiang Chen
Signed-off-by: John Garry
---
drivers/scsi/hisi_sas/hisi_sas.h | 1 +
On Wed, Jun 07, 2017 at 11:52:10AM +0100, Marc Zyngier wrote:
> On 07/06/17 00:00, Palmer Dabbelt wrote:
> > +static void plic_disable(struct plic_data *data, int i, int hwirq)
> > +{
> > + struct plic_enable_context *enable = plic_enable_context(data, i);
> > +
> > + atomic_and(~(1 << (hwirq
On Wed, Jun 07, 2017 at 11:52:10AM +0100, Marc Zyngier wrote:
> On 07/06/17 00:00, Palmer Dabbelt wrote:
> > +static void plic_disable(struct plic_data *data, int i, int hwirq)
> > +{
> > + struct plic_enable_context *enable = plic_enable_context(data, i);
> > +
> > + atomic_and(~(1 << (hwirq
On Thu, Jun 8, 2017 at 7:32 PM, Soren Brinkmann
wrote:
> The one quirk used in the zynq GPIO driver was called FOO which is not
> very descriptive. Rename the quirk to IS_ZYNQ as it indicates whether
> the HW is a zynq or zynqmp device to allow handling of
On Thu, Jun 8, 2017 at 7:32 PM, Soren Brinkmann
wrote:
> The one quirk used in the zynq GPIO driver was called FOO which is not
> very descriptive. Rename the quirk to IS_ZYNQ as it indicates whether
> the HW is a zynq or zynqmp device to allow handling of device-specific
> differences of the
On Thu, Jun 8, 2017 at 10:53 PM, Stephen Rothwell wrote:
> Hi Rob,
>
> Today's linux-next merge of the devicetree tree got a conflict in:
>
> Documentation/devicetree/bindings/vendor-prefixes.txt
>
> between commit:
>
> d795f15618b8 ("of: Add vendor prefix for iWave
On Thu, Jun 8, 2017 at 10:53 PM, Stephen Rothwell wrote:
> Hi Rob,
>
> Today's linux-next merge of the devicetree tree got a conflict in:
>
> Documentation/devicetree/bindings/vendor-prefixes.txt
>
> between commit:
>
> d795f15618b8 ("of: Add vendor prefix for iWave Systems Technologies Pvt.
On Fri, 2017-06-09 at 09:18 -0400, Matt Brown wrote:
> On 6/9/17 9:16 AM, Mimi Zohar wrote:
> > On Fri, 2017-06-09 at 05:55 -0700, Kees Cook wrote:
> >> On Fri, Jun 9, 2017 at 3:18 AM, Mimi Zohar
> >> wrote:
> >>> On Thu, 2017-06-08 at 23:50 -0400, Matt Brown wrote:
>
On Fri, 2017-06-09 at 09:18 -0400, Matt Brown wrote:
> On 6/9/17 9:16 AM, Mimi Zohar wrote:
> > On Fri, 2017-06-09 at 05:55 -0700, Kees Cook wrote:
> >> On Fri, Jun 9, 2017 at 3:18 AM, Mimi Zohar
> >> wrote:
> >>> On Thu, 2017-06-08 at 23:50 -0400, Matt Brown wrote:
> >>
> >> * Issues:
On Tue, Jun 06, 2017 at 09:03:13PM +0800, Baolin Wang wrote:
> This patch adds the binding documentation for Spreadtrum SC9860 pin
> controller device.
For the subject: "dt-bindings: pinctrl: Add Spreadtrum SC9860 pin
controller"
>
> Signed-off-by: Baolin Wang
>
> When CONFIG_QED_SRIOV is disabled, we get a build error:
>
> drivers/net/ethernet/qlogic/qed/qed_int.c: In function 'qed_int_sb_init':
> drivers/net/ethernet/qlogic/qed/qed_int.c:1499:4: error: implicit declaration
> of function 'qed_vf_set_sb_info'; did you mean 'qed_mcp_get_resc_info'? [-
>
On Tue, Jun 06, 2017 at 09:03:13PM +0800, Baolin Wang wrote:
> This patch adds the binding documentation for Spreadtrum SC9860 pin
> controller device.
For the subject: "dt-bindings: pinctrl: Add Spreadtrum SC9860 pin
controller"
>
> Signed-off-by: Baolin Wang
> ---
> Changes since v2:
> -
> When CONFIG_QED_SRIOV is disabled, we get a build error:
>
> drivers/net/ethernet/qlogic/qed/qed_int.c: In function 'qed_int_sb_init':
> drivers/net/ethernet/qlogic/qed/qed_int.c:1499:4: error: implicit declaration
> of function 'qed_vf_set_sb_info'; did you mean 'qed_mcp_get_resc_info'? [-
>
On Tue, Jun 6, 2017 at 11:41 AM, Arnd Bergmann wrote:
> On Mon, Jun 5, 2017 at 10:59 AM, Joel Stanley wrote:
>> On Mon, Jun 5, 2017 at 5:18 PM, Andrew Jeffery wrote:
>>> The merging of a number of clocksource drivers into fttmr010 means we
>>>
On Tue, Jun 6, 2017 at 11:41 AM, Arnd Bergmann wrote:
> On Mon, Jun 5, 2017 at 10:59 AM, Joel Stanley wrote:
>> On Mon, Jun 5, 2017 at 5:18 PM, Andrew Jeffery wrote:
>>> The merging of a number of clocksource drivers into fttmr010 means we
>>> require clock-names to be specified in the Aspeed
On 2017-06-09 at 11:49:02 +0200, Greg Kroah-Hartman
wrote:
> On Mon, Jun 05, 2017 at 02:07:34PM -0500, Alan Tull wrote:
> > From: Tobias Klauser
> >
> > Add COMPILE_TEST to the Kconfig entry for the Altera SoCFPGA FPGA
> > Bridge. The Altera
On 2017-06-09 at 11:49:02 +0200, Greg Kroah-Hartman
wrote:
> On Mon, Jun 05, 2017 at 02:07:34PM -0500, Alan Tull wrote:
> > From: Tobias Klauser
> >
> > Add COMPILE_TEST to the Kconfig entry for the Altera SoCFPGA FPGA
> > Bridge. The Altera FPGA Freeze Bridge can also be used on Altera PEIe
>
On 08/06/17 14:48, Andy Shevchenko wrote:
Use %pt instead of open coded variant to print content of
struct rtc_time in human readable format.
Cc: Jason Wessel
Cc: Ingo Molnar
Signed-off-by: Andy Shevchenko
On 08/06/17 14:48, Andy Shevchenko wrote:
Use %pt instead of open coded variant to print content of
struct rtc_time in human readable format.
Cc: Jason Wessel
Cc: Ingo Molnar
Signed-off-by: Andy Shevchenko
Reviewed-by: Daniel Thompson
---
kernel/debug/kdb/kdb_main.c | 7 +--
1
On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
> On 31/05/17 12:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> >
> > Signed-off-by: YT Shen
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> >
On Wed, 2017-05-31 at 13:38 +0100, Marc Zyngier wrote:
> On 31/05/17 12:39, YT Shen wrote:
> > This adds basic chip support for Mediatek 2712
> >
> > Signed-off-by: YT Shen
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 39
Hi,
On 09/06/17 13:40, Jagan Teki wrote:
> From: Jagan Teki
>
> Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi
I think this is an artefact of the sun8i-dwmac merging, where both David
and Maxime merged the DT patches in their trees (compare
Hi,
On 09/06/17 13:40, Jagan Teki wrote:
> From: Jagan Teki
>
> Remove duplicate ethernet@1c3 from allwinner/sun50i-a64.dtsi
I think this is an artefact of the sun8i-dwmac merging, where both David
and Maxime merged the DT patches in their trees (compare e53f67e9 and
103aefa0). I think
On Tue, Jun 06, 2017 at 11:45:38AM +0200, Neil Armstrong wrote:
> Add bindings for the SoC information register of the Amlogic SoCs.
>
> Signed-off-by: Neil Armstrong
> ---
> Documentation/devicetree/bindings/arm/amlogic.txt | 32
> +++
> 1 file
On Tue, Jun 06, 2017 at 11:45:38AM +0200, Neil Armstrong wrote:
> Add bindings for the SoC information register of the Amlogic SoCs.
>
> Signed-off-by: Neil Armstrong
> ---
> Documentation/devicetree/bindings/arm/amlogic.txt | 32
> +++
> 1 file changed, 32 insertions(+)
>
On Tue, Jun 06, 2017 at 09:31:44AM +0200, Oleksij Rempel wrote:
> Document the new optional "fsl,pmic_stby_poweroff" property.
Needs updating...
>
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/devicetree/bindings/regulator/pfuze100.txt | 7 +++
> 1 file
On Tue, Jun 06, 2017 at 09:31:44AM +0200, Oleksij Rempel wrote:
> Document the new optional "fsl,pmic_stby_poweroff" property.
Needs updating...
>
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/devicetree/bindings/regulator/pfuze100.txt | 7 +++
> 1 file changed, 7 insertions(+)
>
We need to pass only 8 bytes of input for HvSignalEvent which makes it a
perfect fit for fast hypercall. hv_input_signal_event_buffer is not needed
any more and hv_input_signal_event is converted to union for convenience.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy
We need to pass only 8 bytes of input for HvSignalEvent which makes it a
perfect fit for fast hypercall. hv_input_signal_event_buffer is not needed
any more and hv_input_signal_event is converted to union for convenience.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
---
On Tue, Jun 06, 2017 at 09:31:41AM +0200, Oleksij Rempel wrote:
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/devicetree/bindings/clock/imx6q-clock.txt | 8
> 1 file changed, 8 insertions(+)
Acked-by: Rob Herring
To support implementing remote TLB flushing on Hyper-V with a hypercall
we need to make vp_index available outside of vmbus module. Rename and
globalize.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
---
arch/x86/hyperv/hv_init.c
On Tue, Jun 06, 2017 at 09:31:41AM +0200, Oleksij Rempel wrote:
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/devicetree/bindings/clock/imx6q-clock.txt | 8
> 1 file changed, 8 insertions(+)
Acked-by: Rob Herring
To support implementing remote TLB flushing on Hyper-V with a hypercall
we need to make vp_index available outside of vmbus module. Rename and
globalize.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
---
arch/x86/hyperv/hv_init.c | 34 +-
Hyper-V host can suggest us to use hypercall for doing remote TLB flush,
this is supposed to work faster than IPIs.
Implementation details: to do HvFlushVirtualAddress{Space,List} hypercalls
we need to put the input somewhere in memory and we don't really want to
have memory allocation on each
Hyper-V host can suggest us to use hypercall for doing remote TLB flush,
this is supposed to work faster than IPIs.
Implementation details: to do HvFlushVirtualAddress{Space,List} hypercalls
we need to put the input somewhere in memory and we don't really want to
have memory allocation on each
On Thursday, June 08, 2017 08:24:01 PM Greg KH wrote:
> On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote:
> > ---
> > arch/x86/kernel/Makefile| 1 +
> > arch/x86/kernel/cpuinfo_sysfs.c | 166
> > drivers/base/cpuinfo.c |
Add Hyper-V tracing subsystem and trace hyperv_mmu_flush_tlb_others().
Tracing is done the same way we do xen_mmu_flush_tlb_others().
Signed-off-by: Vitaly Kuznetsov
---
MAINTAINERS | 1 +
arch/x86/hyperv/mmu.c | 7 +++
On Thursday, June 08, 2017 08:24:01 PM Greg KH wrote:
> On Thu, Jun 08, 2017 at 06:56:14PM +0200, Felix Schnizlein wrote:
> > ---
> > arch/x86/kernel/Makefile| 1 +
> > arch/x86/kernel/cpuinfo_sysfs.c | 166
> > drivers/base/cpuinfo.c |
Add Hyper-V tracing subsystem and trace hyperv_mmu_flush_tlb_others().
Tracing is done the same way we do xen_mmu_flush_tlb_others().
Signed-off-by: Vitaly Kuznetsov
---
MAINTAINERS | 1 +
arch/x86/hyperv/mmu.c | 7 +++
Hyper-V hosts may support more than 64 vCPUs, we need to use
HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX/LIST_EX hypercalls in this
case.
Signed-off-by: Vitaly Kuznetsov
---
Changes since v7:
- Drop explicit casting from virt_to_phys() [Andy Shevchenko]
- Re-format max_gvas
Hyper-V hosts may support more than 64 vCPUs, we need to use
HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX/LIST_EX hypercalls in this
case.
Signed-off-by: Vitaly Kuznetsov
---
Changes since v7:
- Drop explicit casting from virt_to_phys() [Andy Shevchenko]
- Re-format max_gvas calculus [Andy Shevchenko]
Hyper-V supports 'fast' hypercalls when all parameters are passed through
registers. Implement an inline version of a simpliest of these calls:
hypercall with one 8-byte input and no output.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
Rep hypercalls are normal hypercalls which perform multiple actions at
once. Hyper-V guarantees to return exectution to the caller in not more
than 50us and the caller needs to use hypercall continuation. Touch NMI
watchdog between hypercall invocations.
This is going to be used for
Rep hypercalls are normal hypercalls which perform multiple actions at
once. Hyper-V guarantees to return exectution to the caller in not more
than 50us and the caller needs to use hypercall continuation. Touch NMI
watchdog between hypercall invocations.
This is going to be used for
Hyper-V supports 'fast' hypercalls when all parameters are passed through
registers. Implement an inline version of a simpliest of these calls:
hypercall with one 8-byte input and no output.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
---
arch/x86/include/asm/mshyperv.h | 34
We have only three call sites for hv_do_hypercall() and we're going to
change HVCALL_SIGNAL_EVENT to doing fast hypercall so we can inline this
function for optimization.
Hyper-V top level functional specification states that r9-r11 registers
and flags may be clobbered by the hypervisor during
We have only three call sites for hv_do_hypercall() and we're going to
change HVCALL_SIGNAL_EVENT to doing fast hypercall so we can inline this
function for optimization.
Hyper-V top level functional specification states that r9-r11 registers
and flags may be clobbered by the hypervisor during
Max virtual processor will be needed for 'extended' hypercalls supporting
more than 64 vCPUs. While on it, unify on 'Hyper-V' in mshyperv.c as we
currently have a mix, report acquired misc features as well.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
Max virtual processor will be needed for 'extended' hypercalls supporting
more than 64 vCPUs. While on it, unify on 'Hyper-V' in mshyperv.c as we
currently have a mix, report acquired misc features as well.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
---
Code is arch/x86/hyperv/ is only needed when CONFIG_HYPERV is set, the
'basic' support and detection lives in arch/x86/kernel/cpu/mshyperv.c
which is included when CONFIG_HYPERVISOR_GUEST is set.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
Code is arch/x86/hyperv/ is only needed when CONFIG_HYPERV is set, the
'basic' support and detection lives in arch/x86/kernel/cpu/mshyperv.c
which is included when CONFIG_HYPERVISOR_GUEST is set.
Signed-off-by: Vitaly Kuznetsov
Reviewed-by: Andy Shevchenko
---
arch/x86/Kbuild |
Changes since v7:
- Minor code style fixes (drop explicit casting, reformat code a bit)
in PATCH3 and PATCH9 [Andy Shevchenko]
Original description:
Hyper-V supports hypercalls for doing local and remote TLB flushing and
gives its guests hints when using hypercall is preferred. While doing
Changes since v7:
- Minor code style fixes (drop explicit casting, reformat code a bit)
in PATCH3 and PATCH9 [Andy Shevchenko]
Original description:
Hyper-V supports hypercalls for doing local and remote TLB flushing and
gives its guests hints when using hypercall is preferred. While doing
On Mon, May 22, 2017 at 08:48:37PM +0800, Shaokun Zhang wrote:
> 1. Add support to count MN hardware events.
> 2. Mn events are listed in sysfs at /sys/devices/hisi_mn_2/events/
>The events can be selected as shown in perf list
>e.g.: For MN_READ_REQUEST event for Super CPU cluster 2 the
>
On Mon, May 22, 2017 at 08:48:37PM +0800, Shaokun Zhang wrote:
> 1. Add support to count MN hardware events.
> 2. Mn events are listed in sysfs at /sys/devices/hisi_mn_2/events/
>The events can be selected as shown in perf list
>e.g.: For MN_READ_REQUEST event for Super CPU cluster 2 the
>
On 06/08/2017 06:45 PM, Alexei Starovoitov wrote:
[...]
I think Daniel will be happy to test your next rev of the patches.
I'll test them as well.
At least 'insn_processed' from C code in tools/testing/selftests/bpf/
is a good estimate of how these changes affect pruning.
Without having looked
On 06/08/2017 06:45 PM, Alexei Starovoitov wrote:
[...]
I think Daniel will be happy to test your next rev of the patches.
I'll test them as well.
At least 'insn_processed' from C code in tools/testing/selftests/bpf/
is a good estimate of how these changes affect pruning.
Without having looked
On Fri, Jun 9, 2017 at 2:32 PM, Viresh Kumar wrote:
> On 9 June 2017 at 17:54, Rafael J. Wysocki wrote:
>> Hi,
>>
>> On Fri, Jun 9, 2017 at 12:15 PM, Viresh Kumar
>> wrote:
>>> Hi Rafael,
>>>
>>> I have identified some
On Tue, Jun 06, 2017 at 01:59:27PM +0800, Chen-Yu Tsai wrote:
> The A31 and later have an R_INTC block which handles the NMI interrupt
> pin on the SoC. This interrupt pin is used by the external PMIC to
> signal interrupts to the SoC.
>
> While this hardware block is undocumented, the interrupt
On Fri, Jun 9, 2017 at 2:32 PM, Viresh Kumar wrote:
> On 9 June 2017 at 17:54, Rafael J. Wysocki wrote:
>> Hi,
>>
>> On Fri, Jun 9, 2017 at 12:15 PM, Viresh Kumar
>> wrote:
>>> Hi Rafael,
>>>
>>> I have identified some regressions with the schedutil governor which
>>> happen due to one of your
On Tue, Jun 06, 2017 at 01:59:27PM +0800, Chen-Yu Tsai wrote:
> The A31 and later have an R_INTC block which handles the NMI interrupt
> pin on the SoC. This interrupt pin is used by the external PMIC to
> signal interrupts to the SoC.
>
> While this hardware block is undocumented, the interrupt
Hi,
On Mon, May 22, 2017 at 08:48:35PM +0800, Shaokun Zhang wrote:
> +/*
> + * ARMv8 HiSilicon Hardware counter Index.
> + */
> +enum hisi_l3c_pmu_counters {
> + HISI_IDX_L3C_COUNTER0 = 0x0,
> + HISI_IDX_L3C_COUNTER_MAX= 0x8,
Just to check, there are 8 counters,
Hi,
On Mon, May 22, 2017 at 08:48:35PM +0800, Shaokun Zhang wrote:
> +/*
> + * ARMv8 HiSilicon Hardware counter Index.
> + */
> +enum hisi_l3c_pmu_counters {
> + HISI_IDX_L3C_COUNTER0 = 0x0,
> + HISI_IDX_L3C_COUNTER_MAX= 0x8,
Just to check, there are 8 counters,
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