[PATCH 1/3] ACPI: EC: Fix an EC event IRQ storming issue

The EC event IRQ (SCI_EVT) can only be handled by submitting QR_EC. As the EC driver handles SCI_EVT in a workqueue, after SCI_EVT is flagged and before QR_EC is submitted, there is a period risking IRQ storming. EC IRQ must be masked for this period but linux EC driver never does so. No end user

[PATCH 1/3] ACPI: EC: Fix an EC event IRQ storming issue

The EC event IRQ (SCI_EVT) can only be handled by submitting QR_EC. As the EC driver handles SCI_EVT in a workqueue, after SCI_EVT is flagged and before QR_EC is submitted, there is a period risking IRQ storming. EC IRQ must be masked for this period but linux EC driver never does so. No end user

[PATCH 02/18] spi: qup: Setup DMA mode correctly

To operate in DMA mode, the buffer should be aligned and the size of the transfer should be a multiple of block size (for v1). And the no. of words being transferred should be programmed in the count registers appropriately. Signed-off-by: Andy Gross Signed-off-by:

[PATCH 03/18] spi: qup: Add completion timeout for dma mode

Use different 'completion' structures to track the completion of DMA Tx/Rx and PIO. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 41 - 1 file changed, 24

[PATCH 00/18] spi: qup: Fixes and add support for >64k transfers

v1: This series fixes some existing issues in the code for both interrupt and dma mode. Patches 1 - 11 are the fixes. Random failures/timeout are observed without these fixes. Also, the current driver does not support block transfers > 64K and the driver

[PATCH 02/18] spi: qup: Setup DMA mode correctly

To operate in DMA mode, the buffer should be aligned and the size of the transfer should be a multiple of block size (for v1). And the no. of words being transferred should be programmed in the count registers appropriately. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan ---

[PATCH 03/18] spi: qup: Add completion timeout for dma mode

Use different 'completion' structures to track the completion of DMA Tx/Rx and PIO. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 41 - 1 file changed, 24 insertions(+), 17 deletions(-) diff --git

[PATCH 00/18] spi: qup: Fixes and add support for >64k transfers

v1: This series fixes some existing issues in the code for both interrupt and dma mode. Patches 1 - 11 are the fixes. Random failures/timeout are observed without these fixes. Also, the current driver does not support block transfers > 64K and the driver

[PATCH 07/18] spi: qup: Fix transaction done signaling

Wait to signal done until we get all of the interrupts we are expecting to get for a transaction. If we don't wait for the input done flag, we can be inbetween transactions when the done flag comes in and this can mess up the next transaction. Signed-off-by: Andy Gross

[PATCH 07/18] spi: qup: Fix transaction done signaling

Wait to signal done until we get all of the interrupts we are expecting to get for a transaction. If we don't wait for the input done flag, we can be inbetween transactions when the done flag comes in and this can mess up the next transaction. Signed-off-by: Andy Gross Signed-off-by:

[PATCH 11/18] spi: qup: properly detect extra interrupts

It's possible for a SPI transaction to complete and get another interrupt and have it processed on the same spi_transfer before the transfer_one can set it to NULL. This masks unexpected interrupts, so let's set the spi_transfer to NULL in the interrupt once the transaction is done. So we can

[PATCH 11/18] spi: qup: properly detect extra interrupts

It's possible for a SPI transaction to complete and get another interrupt and have it processed on the same spi_transfer before the transfer_one can set it to NULL. This masks unexpected interrupts, so let's set the spi_transfer to NULL in the interrupt once the transaction is done. So we can

Re: [Merge tag 'pci-v4.12-changes' of git] 857f864014: BUG: unable to handle kernel NULL pointer dereference at 00000000000000a8

On 13/06/17 11:00 PM, Greg Kroah-Hartman wrote: > No, don't modify any drivers, do this in the core chardev code. Ok, well then maybe I misunderstood what you originally asked for because I don't see how you can change a fixed allocation to a dynamic one without touching the driver code which

[PATCH 12/18] spi: qup: refactor spi_qup_io_config into two functions

This is in preparation for handling transactions larger than 64K-1 bytes in block mode, which is currently unsupported and quietly fails. We need to break these into two functions 1) prep is called once per spi_message and 2) io_config is called once per spi-qup bus transaction This is just

Re: [PATCH] powerpc: dts: use #include "..." to include local DT

Hi. 2017-06-13 19:21 GMT+09:00 Michael Ellerman : > Masahiro Yamada writes: > >> Hi >> >> (+Anatolij Gustschin ) >> >> >> Ping. >> I am not 100% sure who is responsible for this, >> but somebody, could take a look at this patch,

Re: [Merge tag 'pci-v4.12-changes' of git] 857f864014: BUG: unable to handle kernel NULL pointer dereference at 00000000000000a8

On 13/06/17 11:00 PM, Greg Kroah-Hartman wrote: > No, don't modify any drivers, do this in the core chardev code. Ok, well then maybe I misunderstood what you originally asked for because I don't see how you can change a fixed allocation to a dynamic one without touching the driver code which

[PATCH 12/18] spi: qup: refactor spi_qup_io_config into two functions

This is in preparation for handling transactions larger than 64K-1 bytes in block mode, which is currently unsupported and quietly fails. We need to break these into two functions 1) prep is called once per spi_message and 2) io_config is called once per spi-qup bus transaction This is just

Re: [PATCH] powerpc: dts: use #include "..." to include local DT

Hi. 2017-06-13 19:21 GMT+09:00 Michael Ellerman : > Masahiro Yamada writes: > >> Hi >> >> (+Anatolij Gustschin ) >> >> >> Ping. >> I am not 100% sure who is responsible for this, >> but somebody, could take a look at this patch, please? > > Have you tested it actually works? > > It sounds

[PATCH 17/18] spi: qup: Ensure done detection

This patch fixes an issue where a SPI transaction has completed, but the done condition is missed. This occurs because at the time of interrupt the MAX_INPUT_DONE_FLAG is not asserted. However, in the process of reading blocks of data from the FIFO, the last portion of data comes in. The

[PATCH 17/18] spi: qup: Ensure done detection

This patch fixes an issue where a SPI transaction has completed, but the done condition is missed. This occurs because at the time of interrupt the MAX_INPUT_DONE_FLAG is not asserted. However, in the process of reading blocks of data from the FIFO, the last portion of data comes in. The

[PATCH 13/18] spi: qup: call io_config in mode specific function

DMA transactions should only only need to call io_config only once, but block mode might call it several times to setup several transactions so it can handle reads/writes larger than the max size per transaction, so we move the call to the do_ functions. This is just refactoring, there should be

[PATCH 13/18] spi: qup: call io_config in mode specific function

DMA transactions should only only need to call io_config only once, but block mode might call it several times to setup several transactions so it can handle reads/writes larger than the max size per transaction, so we move the call to the do_ functions. This is just refactoring, there should be

[PATCH 14/18] spi: qup: allow block mode to generate multiple transactions

This let's you write more to the SPI bus than 64K-1 which is important if the block size of a SPI device is >= 64K or some other device wants to do something larger. This has the benefit of completely removing spi_message from the spi-qup transactions Signed-off-by: Matthew McClintock

[PATCH 16/18] spi: qup: allow multiple DMA transactions per spi xfer

Much like the block mode changes, we are breaking up DMA transactions into 64K chunks so we can reset the QUP engine. Signed-off-by: Matthew McClintock Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 105

[PATCH 14/18] spi: qup: allow block mode to generate multiple transactions

This let's you write more to the SPI bus than 64K-1 which is important if the block size of a SPI device is >= 64K or some other device wants to do something larger. This has the benefit of completely removing spi_message from the spi-qup transactions Signed-off-by: Matthew McClintock

[PATCH 16/18] spi: qup: allow multiple DMA transactions per spi xfer

Much like the block mode changes, we are breaking up DMA transactions into 64K chunks so we can reset the QUP engine. Signed-off-by: Matthew McClintock Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 105 -- 1 file changed, 77

[PATCH 18/18] spi: qup: support for qup v1 dma

Currently the QUP Version v1 does not work with DMA so added the support for the same. 1. It uses ADM DMA which requires TX and RX CRCI 2. DMA channel initialization need to be done after setting block size for having valid values in maxburst 3. QUP mode should be DMOV instead of BAM.

[PATCH 15/18] spi: qup: refactor spi_qup_prep_sg

Take specific sgl and nent to be prepared. This is in preparation for splitting DMA into multiple transacations, this contains no code changes just refactoring. Signed-off-by: Matthew McClintock Signed-off-by: Varadarajan Narayanan ---

[PATCH 18/18] spi: qup: support for qup v1 dma

Currently the QUP Version v1 does not work with DMA so added the support for the same. 1. It uses ADM DMA which requires TX and RX CRCI 2. DMA channel initialization need to be done after setting block size for having valid values in maxburst 3. QUP mode should be DMOV instead of BAM.

[PATCH 15/18] spi: qup: refactor spi_qup_prep_sg

Take specific sgl and nent to be prepared. This is in preparation for splitting DMA into multiple transacations, this contains no code changes just refactoring. Signed-off-by: Matthew McClintock Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 25 ++--- 1

[PATCH 09/18] spi: qup: Do block sized read/write in block mode

This patch corrects the behavior of the BLOCK transactions. During block transactions, the controller must be read/written to in block size transactions. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c |

[PATCH 09/18] spi: qup: Do block sized read/write in block mode

This patch corrects the behavior of the BLOCK transactions. During block transactions, the controller must be read/written to in block size transactions. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 151

[PATCH 10/18] spi: qup: Fix DMA mode interrupt handling

This is needed for v1, where the i/o completion is not handled in the dma driver. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff

[PATCH 10/18] spi: qup: Fix DMA mode interrupt handling

This is needed for v1, where the i/o completion is not handled in the dma driver. Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c

[PATCH 08/18] spi: qup: Handle v1 dma completion differently

Do not assign i/o completion callbacks while running on v1 of QUP. Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 7c22ee4..0f6a4c7

[PATCH 06/18] spi: qup: Fix error handling in spi_qup_prep_sg

Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 363bd43..2124815 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@

[PATCH 05/18] spi: qup: Place the QUP in run mode before DMA transactions

Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index d3ccf53..363bd43 100644 --- a/drivers/spi/spi-qup.c +++

[PATCH 08/18] spi: qup: Handle v1 dma completion differently

Do not assign i/o completion callbacks while running on v1 of QUP. Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 7c22ee4..0f6a4c7 100644 ---

[PATCH 06/18] spi: qup: Fix error handling in spi_qup_prep_sg

Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 363bd43..2124815 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -310,8 +310,8 @@ static

[PATCH 05/18] spi: qup: Place the QUP in run mode before DMA transactions

Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index d3ccf53..363bd43 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -336,6

[PATCH 04/18] spi: qup: Add completion timeout for fifo/block mode

Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 272e48e..d3ccf53 100644

[PATCH 01/18] spi: qup: Enable chip select support

Enable chip select support for QUP versions later than v1 Signed-off-by: Sham Muthayyan Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 21 + 1 file changed, 21 insertions(+) diff --git

[PATCH 04/18] spi: qup: Add completion timeout for fifo/block mode

Signed-off-by: Andy Gross Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 272e48e..d3ccf53 100644 --- a/drivers/spi/spi-qup.c +++

[PATCH 01/18] spi: qup: Enable chip select support

Enable chip select support for QUP versions later than v1 Signed-off-by: Sham Muthayyan Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 21 + 1 file changed, 21 insertions(+) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 1bfa889..c0d4def

Re: [PATCH v2 1/1] PCI: imx6: Add pcie compliance test option

On Tuesday, June 13, 2017 8:58:47 AM CEST Bjorn Helgaas wrote: > On Tue, Jun 13, 2017 at 05:43:14AM +, Schöfegger Stefan wrote: > > On Monday, June 12, 2017 6:49:24 PM CEST Bjorn Helgaas wrote: > > > On Wed, Jun 07, 2017 at 01:36:11PM +0200, Stefan Schoefegger wrote: > > > > Link speed must

Re: [PATCH v2 1/1] PCI: imx6: Add pcie compliance test option

On Tuesday, June 13, 2017 8:58:47 AM CEST Bjorn Helgaas wrote: > On Tue, Jun 13, 2017 at 05:43:14AM +, Schöfegger Stefan wrote: > > On Monday, June 12, 2017 6:49:24 PM CEST Bjorn Helgaas wrote: > > > On Wed, Jun 07, 2017 at 01:36:11PM +0200, Stefan Schoefegger wrote: > > > > Link speed must

Re: [PATCH] kernel/kprobes: Add test to validate pt_regs

On Wed, 14 Jun 2017 11:40:08 +0900 Masami Hiramatsu wrote: > On Fri, 9 Jun 2017 00:53:08 +0530 > "Naveen N. Rao" wrote: > > > Add a test to verify that the registers passed in pt_regs on kprobe > > (trap), optprobe (jump) and

Re: [PATCH] kernel/kprobes: Add test to validate pt_regs

On Wed, 14 Jun 2017 11:40:08 +0900 Masami Hiramatsu wrote: > On Fri, 9 Jun 2017 00:53:08 +0530 > "Naveen N. Rao" wrote: > > > Add a test to verify that the registers passed in pt_regs on kprobe > > (trap), optprobe (jump) and kprobe_on_ftrace (ftrace_caller) are > > accurate. The tests are

Re: [PATCHv2] ARM: OMAP: PM: stop early on systems without twl

* Sebastian Reichel [170613 02:50]: > From: Sebastian Reichel > diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c > index 63027e60cc20..92e335decc61 100644 > --- a/arch/arm/mach-omap2/pm.c > +++ b/arch/arm/mach-omap2/pm.c > @@

Re: [PATCHv2] ARM: OMAP: PM: stop early on systems without twl

* Sebastian Reichel [170613 02:50]: > From: Sebastian Reichel > diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c > index 63027e60cc20..92e335decc61 100644 > --- a/arch/arm/mach-omap2/pm.c > +++ b/arch/arm/mach-omap2/pm.c > @@ -240,6 +240,10 @@

[RESEND PATCH] base/memory: pass the base_section in add_memory_block

Based on Greg's comment, cc it to mm list. The original thread could be found https://lkml.org/lkml/2017/6/7/202 The second parameter of init_memory_block() is used to calculate the start_section_nr of this block, which means any section in the same block would get the same start_section_nr.

[RESEND PATCH] base/memory: pass the base_section in add_memory_block

Based on Greg's comment, cc it to mm list. The original thread could be found https://lkml.org/lkml/2017/6/7/202 The second parameter of init_memory_block() is used to calculate the start_section_nr of this block, which means any section in the same block would get the same start_section_nr.

Re: [PATCH 1/2] perf evsel: Fix probing of precise_ip level for default cycles event

* Arnaldo Carvalho de Melo wrote: > tools/perf/tests/task-exit.c | 2 +- > tools/perf/util/evsel.c | 5 + > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/tools/perf/tests/task-exit.c b/tools/perf/tests/task-exit.c > index 32873ec91a4e..cf00ebad2ef5

Re: [PATCH 1/2] perf evsel: Fix probing of precise_ip level for default cycles event

* Arnaldo Carvalho de Melo wrote: > tools/perf/tests/task-exit.c | 2 +- > tools/perf/util/evsel.c | 5 + > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/tools/perf/tests/task-exit.c b/tools/perf/tests/task-exit.c > index 32873ec91a4e..cf00ebad2ef5 100644 > ---

Re: [RFC/RFT PATCH 4/4] [debug] ARM: am335x: illustrate hwstamp

* Grygorii Strashko [170613 16:20]: > This patch allows to test CPTS HW_TS_PUSH functionality on am335x boards > > below sequence of commands will enable Timer7 to trigger 1sec > periodic pulses on CPTS HW4_TS_PUSH input pin: > > # echo 10 >

Re: [RFC/RFT PATCH 4/4] [debug] ARM: am335x: illustrate hwstamp

* Grygorii Strashko [170613 16:20]: > This patch allows to test CPTS HW_TS_PUSH functionality on am335x boards > > below sequence of commands will enable Timer7 to trigger 1sec > periodic pulses on CPTS HW4_TS_PUSH input pin: > > # echo 10 > /sys/class/pwm/pwmchip0/pwm0/period > #

Re: [GIT PULL 0/2] perf/urgent fixes for 4.12

Merge tag 'perf-urgent-for-mingo-4.12-20170608' of > git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent > (2017-06-09 00:41:33 +0200) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git > ta

Re: [GIT PULL 0/2] perf/urgent fixes for 4.12

rf-urgent-for-mingo-4.12-20170608' of > git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent > (2017-06-09 00:41:33 +0200) > > are available in the git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git > tags/perf-urgent-fo

Re: [PATCH v2 09/10] x86/mm: Enable CR4.PCIDE on supported systems

On 14/06/17 06:56, Andy Lutomirski wrote: > We can use PCID if the CPU has PCID and PGE and we're not on Xen. > > By itself, this has no effect. The next patch will start using > PCID. > > Cc: Juergen Gross > Cc: Boris Ostrovsky > Signed-off-by:

Re: [PATCH v2 09/10] x86/mm: Enable CR4.PCIDE on supported systems

On 14/06/17 06:56, Andy Lutomirski wrote: > We can use PCID if the CPU has PCID and PGE and we're not on Xen. > > By itself, this has no effect. The next patch will start using > PCID. > > Cc: Juergen Gross > Cc: Boris Ostrovsky > Signed-off-by: Andy Lutomirski Reviewed-by: Juergen Gross

RE: [PATCH v8 4/6] vfio: Define vfio based vgpu's dma-buf operations

>-Original Message- >From: Alex Williamson [mailto:alex.william...@redhat.com] >Sent: Wednesday, June 14, 2017 11:46 AM >To: Chen, Xiaoguang >Cc: Tian, Kevin ; intel-...@lists.freedesktop.org; linux- >ker...@vger.kernel.org;

RE: [PATCH v8 4/6] vfio: Define vfio based vgpu's dma-buf operations

>-Original Message- >From: Alex Williamson [mailto:alex.william...@redhat.com] >Sent: Wednesday, June 14, 2017 11:46 AM >To: Chen, Xiaoguang >Cc: Tian, Kevin ; intel-...@lists.freedesktop.org; linux- >ker...@vger.kernel.org; zhen...@linux.intel.com; ch...@chris-wilson.co.uk; Lv,

Re: [PATCH] ip6_tunnel: Correct tos value in collect_md mode

On Wed, 14 Jun 2017 10:54:31 +0800 严海双 wrote: > > Changes since v2: > > * mask key->tos with RT_TOS() suggested by Daniel Can you help me understand the rationale for this change? Is there are bug introduced by dsfield = ip6_tclass(key->label); ? The

Re: [PATCH] ip6_tunnel: Correct tos value in collect_md mode

On Wed, 14 Jun 2017 10:54:31 +0800 严海双 wrote: > > Changes since v2: > > * mask key->tos with RT_TOS() suggested by Daniel Can you help me understand the rationale for this change? Is there are bug introduced by dsfield = ip6_tclass(key->label); ? The RT_TOS masks out 4bits of the 8bit tos

Re: [RESEND PATCH 1/2] arm:omap2+: put omap_uart_phys/virt/lsr in .text section when ZIMAGE is true

Hi, * Hoeun Ryu [170612 18:18]: > --- a/arch/arm/include/debug/omap2plus.S > +++ b/arch/arm/include/debug/omap2plus.S > @@ -58,11 +58,22 @@ > > #define UART_OFFSET(addr)((addr) & 0x00ff) > > +/* > + * Definition of ZIMAGE is in arch/arm/boot/compressed/Makefile.

Re: [RESEND PATCH 1/2] arm:omap2+: put omap_uart_phys/virt/lsr in .text section when ZIMAGE is true

Hi, * Hoeun Ryu [170612 18:18]: > --- a/arch/arm/include/debug/omap2plus.S > +++ b/arch/arm/include/debug/omap2plus.S > @@ -58,11 +58,22 @@ > > #define UART_OFFSET(addr)((addr) & 0x00ff) > > +/* > + * Definition of ZIMAGE is in arch/arm/boot/compressed/Makefile. > + * Place the

Re: RESEND Re: [Patch 2/2]: powerpc/hotplug/mm: Fix hot-add memory node assoc

On Wed, Jun 14, 2017 at 3:25 PM, Balbir Singh wrote: > > > On Wed, Jun 14, 2017 at 8:21 AM, Michael Bringmann > wrote: >> >> On a related note, we are discussing the addition of 2 new device-tree >> properties >> with Pete Heyrman and his fellows

Re: RESEND Re: [Patch 2/2]: powerpc/hotplug/mm: Fix hot-add memory node assoc

On Wed, Jun 14, 2017 at 3:25 PM, Balbir Singh wrote: > > > On Wed, Jun 14, 2017 at 8:21 AM, Michael Bringmann > wrote: >> >> On a related note, we are discussing the addition of 2 new device-tree >> properties >> with Pete Heyrman and his fellows that should simplify the determination >> of the

Re: [PATCH v2] HID: Replace semaphore driver_lock with mutex

Hi, On 14 June 2017 at 01:55, Arnd Bergmann wrote: >> The mutex code clearly states mutex_trylock() must not be used in >> interrupt context (see kernel/locking/mutex.c), hence we used a >> semaphore here. Unless the mutex code is changed to allow this, we >> cannot switch away

Re: [PATCH v2] HID: Replace semaphore driver_lock with mutex

Hi, On 14 June 2017 at 01:55, Arnd Bergmann wrote: >> The mutex code clearly states mutex_trylock() must not be used in >> interrupt context (see kernel/locking/mutex.c), hence we used a >> semaphore here. Unless the mutex code is changed to allow this, we >> cannot switch away from semaphores.

Re: [PATCH] Staging: vc04_services: bcm2835-audio: bcm2835-ctl.c: Fixed alignment to match open parenthesis.

On Wed, Jun 14, 2017 at 03:15:11AM +0530, srishti sharma wrote: > On Tue, Jun 13, 2017 at 8:17 PM, Dan Carpenter > wrote: > > On Tue, Jun 13, 2017 at 08:07:14PM +0530, srishti sharma wrote: > >> On Tue, Jun 13, 2017 at 6:30 PM, Greg KH > >>

Re: [PATCH] Staging: vc04_services: bcm2835-audio: bcm2835-ctl.c: Fixed alignment to match open parenthesis.

On Wed, Jun 14, 2017 at 03:15:11AM +0530, srishti sharma wrote: > On Tue, Jun 13, 2017 at 8:17 PM, Dan Carpenter > wrote: > > On Tue, Jun 13, 2017 at 08:07:14PM +0530, srishti sharma wrote: > >> On Tue, Jun 13, 2017 at 6:30 PM, Greg KH > >> wrote: > >> > On Sat, Jun 10, 2017 at 02:37:22AM

Re: [PATCH] staging: android: uapi: drop definitions of removed ION_IOC_{FREE,SHARE} ioctls

On Tue, Jun 13, 2017 at 09:17:05PM +0300, Gleb Fotengauer-Malinovskiy wrote: > On Tue, May 30, 2017 at 04:33:57PM -0700, Laura Abbott wrote: > > On 05/30/2017 07:11 AM, Gleb Fotengauer-Malinovskiy wrote: > > > This problem was found by strace ioctl list generator. > > > > > > Fixes: 15c6098cfec5

Re: [PATCH] staging: android: uapi: drop definitions of removed ION_IOC_{FREE,SHARE} ioctls

On Tue, Jun 13, 2017 at 09:17:05PM +0300, Gleb Fotengauer-Malinovskiy wrote: > On Tue, May 30, 2017 at 04:33:57PM -0700, Laura Abbott wrote: > > On 05/30/2017 07:11 AM, Gleb Fotengauer-Malinovskiy wrote: > > > This problem was found by strace ioctl list generator. > > > > > > Fixes: 15c6098cfec5

Re: [PATCH 1/1] uio: Fix uio_device memory leak

On Tue, Jun 13, 2017 at 07:35:51PM -0500, Mike Christie wrote: > On 06/13/2017 07:16 PM, Mike Christie wrote: > > On 06/13/2017 09:01 AM, Greg KH wrote: > >> > On Wed, Jun 07, 2017 at 03:06:44PM -0500, Mike Christie wrote: > >>> >> It looks like there might be 2 issues with the uio_device

Re: [PATCH 1/1] uio: Fix uio_device memory leak

On Tue, Jun 13, 2017 at 07:35:51PM -0500, Mike Christie wrote: > On 06/13/2017 07:16 PM, Mike Christie wrote: > > On 06/13/2017 09:01 AM, Greg KH wrote: > >> > On Wed, Jun 07, 2017 at 03:06:44PM -0500, Mike Christie wrote: > >>> >> It looks like there might be 2 issues with the uio_device

Re: [Merge tag 'pci-v4.12-changes' of git] 857f864014: BUG: unable to handle kernel NULL pointer dereference at 00000000000000a8

On Tue, Jun 13, 2017 at 09:13:32PM +0200, Sven-Haegar Koch wrote: > On Tue, 13 Jun 2017, Greg Kroah-Hartman wrote: > > > On Tue, Jun 13, 2017 at 10:25:40AM -0600, Logan Gunthorpe wrote: > > > > > > On 12/06/17 10:35 PM, Greg Kroah-Hartman wrote: > > > > Or better yet, just turn all char major

Re: [Merge tag 'pci-v4.12-changes' of git] 857f864014: BUG: unable to handle kernel NULL pointer dereference at 00000000000000a8

On Tue, Jun 13, 2017 at 09:13:32PM +0200, Sven-Haegar Koch wrote: > On Tue, 13 Jun 2017, Greg Kroah-Hartman wrote: > > > On Tue, Jun 13, 2017 at 10:25:40AM -0600, Logan Gunthorpe wrote: > > > > > > On 12/06/17 10:35 PM, Greg Kroah-Hartman wrote: > > > > Or better yet, just turn all char major

Re: [Merge tag 'pci-v4.12-changes' of git] 857f864014: BUG: unable to handle kernel NULL pointer dereference at 00000000000000a8

On Tue, Jun 13, 2017 at 11:47:30AM -0600, Logan Gunthorpe wrote: > > > On 13/06/17 10:35 AM, Greg Kroah-Hartman wrote: > > For char devices, I doubt it, but we can't take the chance, which is why > > you make it an option. Then, it's enabled for 'allmodconfig' builds, > > which helps testers

Re: [Merge tag 'pci-v4.12-changes' of git] 857f864014: BUG: unable to handle kernel NULL pointer dereference at 00000000000000a8

On Tue, Jun 13, 2017 at 11:47:30AM -0600, Logan Gunthorpe wrote: > > > On 13/06/17 10:35 AM, Greg Kroah-Hartman wrote: > > For char devices, I doubt it, but we can't take the chance, which is why > > you make it an option. Then, it's enabled for 'allmodconfig' builds, > > which helps testers

[PATCH v2 01/10] x86/ldt: Simplify LDT switching logic

Originally, Linux reloaded the LDT whenever the prev mm or the next mm had an LDT. It was changed in 0bbed3beb4f2 ("[PATCH] Thread-Local Storage (TLS) support") (from the historical tree) like this: - /* load_LDT, if either the previous or next thread -* has a

[PATCH v2 01/10] x86/ldt: Simplify LDT switching logic

Originally, Linux reloaded the LDT whenever the prev mm or the next mm had an LDT. It was changed in 0bbed3beb4f2 ("[PATCH] Thread-Local Storage (TLS) support") (from the historical tree) like this: - /* load_LDT, if either the previous or next thread -* has a

[PATCH v2 00/10] PCID and improved laziness

There are three performance benefits here: 1. TLB flushing is slow. (I.e. the flush itself takes a while.) This avoids many of them when switching tasks by using PCID. In a stupid little benchmark I did, it saves about 100ns on my laptop per context switch. I'll try to improve that

[PATCH v2 00/10] PCID and improved laziness

There are three performance benefits here: 1. TLB flushing is slow. (I.e. the flush itself takes a while.) This avoids many of them when switching tasks by using PCID. In a stupid little benchmark I did, it saves about 100ns on my laptop per context switch. I'll try to improve that

[PATCH v2 03/10] x86/mm: Give each mm TLB flush generation a unique ID

This adds two new variables to mmu_context_t: ctx_id and tlb_gen. ctx_id uniquely identifies the mm_struct and will never be reused. For a given mm_struct (and hence ctx_id), tlb_gen is a monotonic count of the number of times that a TLB flush has been requested. The pair (ctx_id, tlb_gen) can be

[PATCH v2 03/10] x86/mm: Give each mm TLB flush generation a unique ID

This adds two new variables to mmu_context_t: ctx_id and tlb_gen. ctx_id uniquely identifies the mm_struct and will never be reused. For a given mm_struct (and hence ctx_id), tlb_gen is a monotonic count of the number of times that a TLB flush has been requested. The pair (ctx_id, tlb_gen) can be

[PATCH v2 04/10] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm

There are two kernel features that would benefit from tracking how up-to-date each CPU's TLB is in the case where IPIs aren't keeping it up to date in real time: - Lazy mm switching currently works by switching to init_mm when it would otherwise flush. This is wasteful: there isn't

[PATCH v2 05/10] x86/mm: Rework lazy TLB mode and TLB freshness tracking

x86's lazy TLB mode used to be fairly weak -- it would switch to init_mm the first time it tried to flush a lazy TLB. This meant an unnecessary CR3 write and, if the flush was remote, an unnecessary IPI. Rewrite it entirely. When we enter lazy mode, we simply remove the cpu from mm_cpumask.

[PATCH v2 02/10] x86/mm: Remove reset_lazy_tlbstate()

The only call site also calls idle_task_exit(), and idle_task_exit() puts us into a clean state by explicitly switching to init_mm. Signed-off-by: Andy Lutomirski --- arch/x86/include/asm/tlbflush.h | 8 arch/x86/kernel/smpboot.c | 1 - 2 files changed, 9

[PATCH v2 07/10] x86/mm: Disable PCID on 32-bit kernels

32-bit kernels on new hardware will see PCID in CPUID, but PCID can only be used in 64-bit mode. Rather than making all PCID code conditional, just disable the feature on 32-bit builds. Signed-off-by: Andy Lutomirski --- arch/x86/include/asm/disabled-features.h | 4 +++-

[PATCH v2 04/10] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm

There are two kernel features that would benefit from tracking how up-to-date each CPU's TLB is in the case where IPIs aren't keeping it up to date in real time: - Lazy mm switching currently works by switching to init_mm when it would otherwise flush. This is wasteful: there isn't

[PATCH v2 05/10] x86/mm: Rework lazy TLB mode and TLB freshness tracking

x86's lazy TLB mode used to be fairly weak -- it would switch to init_mm the first time it tried to flush a lazy TLB. This meant an unnecessary CR3 write and, if the flush was remote, an unnecessary IPI. Rewrite it entirely. When we enter lazy mode, we simply remove the cpu from mm_cpumask.

[PATCH v2 02/10] x86/mm: Remove reset_lazy_tlbstate()

The only call site also calls idle_task_exit(), and idle_task_exit() puts us into a clean state by explicitly switching to init_mm. Signed-off-by: Andy Lutomirski --- arch/x86/include/asm/tlbflush.h | 8 arch/x86/kernel/smpboot.c | 1 - 2 files changed, 9 deletions(-) diff --git

[PATCH v2 07/10] x86/mm: Disable PCID on 32-bit kernels

32-bit kernels on new hardware will see PCID in CPUID, but PCID can only be used in 64-bit mode. Rather than making all PCID code conditional, just disable the feature on 32-bit builds. Signed-off-by: Andy Lutomirski --- arch/x86/include/asm/disabled-features.h | 4 +++-

Re: [PATCH] pci: iov: use device lock to protect IOV sysfs accesses

On Tue, 30 May 2017 16:34:29 -0700, Jakub Kicinski wrote: > On Tue, 30 May 2017 18:07:18 -0500, Bjorn Helgaas wrote: > > On Fri, May 26, 2017 at 04:58:20PM -0700, Jakub Kicinski wrote: > > > On Fri, 26 May 2017 18:47:26 -0500, Bjorn Helgaas wrote: > > > > On Mon, May 22, 2017 at 03:50:23PM

Re: [PATCH] pci: iov: use device lock to protect IOV sysfs accesses

On Tue, 30 May 2017 16:34:29 -0700, Jakub Kicinski wrote: > On Tue, 30 May 2017 18:07:18 -0500, Bjorn Helgaas wrote: > > On Fri, May 26, 2017 at 04:58:20PM -0700, Jakub Kicinski wrote: > > > On Fri, 26 May 2017 18:47:26 -0500, Bjorn Helgaas wrote: > > > > On Mon, May 22, 2017 at 03:50:23PM

[PATCH v2 06/10] x86/mm: Stop calling leave_mm() in idle code

Now that lazy TLB suppresses all flush IPIs (as opposed to all but the first), there's no need to leave_mm() when going idle. This means we can get rid of the rcuidle hack in switch_mm_irqs_off() and we can unexport leave_mm(). This also removes acpi_unlazy_tlb() from the x86 and ia64 headers,

[PATCH v2 10/10] x86/mm: Try to preserve old TLB entries using PCID

PCID is a "process context ID" -- it's what other architectures call an address space ID. Every non-global TLB entry is tagged with a PCID, only TLB entries that match the currently selected PCID are used, and we can switch PGDs without flushing the TLB. x86's PCID is 12 bits. This is an

[PATCH v2 08/10] x86/mm: Add nopcid to turn off PCID

The parameter is only present on x86_64 systems to save a few bytes, as PCID is always disabled on x86_32. Signed-off-by: Andy Lutomirski --- Documentation/admin-guide/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/common.c| 18 ++ 2

[PATCH v2 06/10] x86/mm: Stop calling leave_mm() in idle code

Now that lazy TLB suppresses all flush IPIs (as opposed to all but the first), there's no need to leave_mm() when going idle. This means we can get rid of the rcuidle hack in switch_mm_irqs_off() and we can unexport leave_mm(). This also removes acpi_unlazy_tlb() from the x86 and ia64 headers,

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