Thanks to the nested inlining, all drivers correctly calling
dma_mapping_error() after a mapping a page or single buffer generate two
calls to get_arch_dma_ops() per callsite, which all adds up to a fair
old chunk of useless code, e.g. ~3KB for an arm64 defconfig plus extras:
textdata
Thanks to the nested inlining, all drivers correctly calling
dma_mapping_error() after a mapping a page or single buffer generate two
calls to get_arch_dma_ops() per callsite, which all adds up to a fair
old chunk of useless code, e.g. ~3KB for an arm64 defconfig plus extras:
textdata
On Mon, Jul 24, 2017 at 6:09 PM, Andrey Smirnov
wrote:
> Add a driver for RAVE Supervisory Processor, an MCU implementing
> varoius bits of housekeeping functionality (watchdoging, backlight
> control, LED control, etc) on RAVE family of products by Zodiac
> Inflight
On Mon, Jul 24, 2017 at 6:09 PM, Andrey Smirnov
wrote:
> Add a driver for RAVE Supervisory Processor, an MCU implementing
> varoius bits of housekeeping functionality (watchdoging, backlight
> control, LED control, etc) on RAVE family of products by Zodiac
> Inflight Innovations.
>
> This driver
Hi Nick,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Nick-Terrell/Add-xxhash-and-zstd-modules
Hi Nick,
[auto build test WARNING on linus/master]
[also build test WARNING on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Nick-Terrell/Add-xxhash-and-zstd-modules
On Mon, Jul 24, 2017 at 4:50 AM, André Przywara wrote:
> On 02/07/17 06:55, Jassi Brar wrote:
>
>>> + mbox_chan_received_data(link, (void *)res.a0);
>>> +
>> Or you can update the 'data' with value from 'a0' ?
>
> Mmh, I am a bit puzzled by this. Why would this be
On Mon, Jul 24, 2017 at 4:50 AM, André Przywara wrote:
> On 02/07/17 06:55, Jassi Brar wrote:
>
>>> + mbox_chan_received_data(link, (void *)res.a0);
>>> +
>> Or you can update the 'data' with value from 'a0' ?
>
> Mmh, I am a bit puzzled by this. Why would this be needed or useful?
>
I
On Thu, 20 Jul 2017 10:02:33 +0530
Anup Patel wrote:
> Not allowing No-IOMMU mode for devices already having
> iommu_ops on their bus is very conservative.
>
> We now have IOMMU (such as ARM SMMU) which can bypass
> transcations when IOMMU is not configured for a given
On Thu, 20 Jul 2017 10:02:33 +0530
Anup Patel wrote:
> Not allowing No-IOMMU mode for devices already having
> iommu_ops on their bus is very conservative.
>
> We now have IOMMU (such as ARM SMMU) which can bypass
> transcations when IOMMU is not configured for a given
> device. In addition, it
On 24/07/17 18:16, Alex Williamson wrote:
> On Thu, 20 Jul 2017 12:17:12 +0100
> Robin Murphy wrote:
>
>> On 20/07/17 10:10, Will Deacon wrote:
>>> On Thu, Jul 20, 2017 at 09:32:00AM +0530, Anup Patel wrote:
On Wed, Jul 19, 2017 at 5:23 PM, Will Deacon
On 24/07/17 18:16, Alex Williamson wrote:
> On Thu, 20 Jul 2017 12:17:12 +0100
> Robin Murphy wrote:
>
>> On 20/07/17 10:10, Will Deacon wrote:
>>> On Thu, Jul 20, 2017 at 09:32:00AM +0530, Anup Patel wrote:
On Wed, Jul 19, 2017 at 5:23 PM, Will Deacon wrote:
> There are two things
On Mon, Jul 24, 2017 at 9:51 PM, Sudeep Holla wrote:
> On 24/07/17 16:41, Jassi Brar wrote:
>> SCMI calls
>> mbox_send_message(struct mbox_chan *chan, struct scmi_xfer *xfer);
>>
>> whereas the API expects
>> mbox_send_message(struct mbox_chan *chan, struct
On Mon, Jul 24, 2017 at 9:51 PM, Sudeep Holla wrote:
> On 24/07/17 16:41, Jassi Brar wrote:
>> SCMI calls
>> mbox_send_message(struct mbox_chan *chan, struct scmi_xfer *xfer);
>>
>> whereas the API expects
>> mbox_send_message(struct mbox_chan *chan, struct controller_specific
>>
Commit ff86bf0c65f1 ("alarmtimer: Rate limit periodic intervals") sets a
minimum bound on the alarm timer interval. This minimum bound shouldn't
be applied if the interval is 0. Otherwise, one-shot timers will be
converted into periodic ones.
This patch is against 4.9.39, and is only needed in
Commit ff86bf0c65f1 ("alarmtimer: Rate limit periodic intervals") sets a
minimum bound on the alarm timer interval. This minimum bound shouldn't
be applied if the interval is 0. Otherwise, one-shot timers will be
converted into periodic ones.
This patch is against 4.9.39, and is only needed in
Add missing line breaks between the last two tests.
Signed-off-by: Shuah Khan
---
tools/testing/selftests/breakpoints/breakpoint_test.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/breakpoints/breakpoint_test.c
Add missing line breaks between the last two tests.
Signed-off-by: Shuah Khan
---
tools/testing/selftests/breakpoints/breakpoint_test.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/breakpoints/breakpoint_test.c
On Thu, 20 Jul 2017 12:17:12 +0100
Robin Murphy wrote:
> On 20/07/17 10:10, Will Deacon wrote:
> > On Thu, Jul 20, 2017 at 09:32:00AM +0530, Anup Patel wrote:
> >> On Wed, Jul 19, 2017 at 5:23 PM, Will Deacon wrote:
> >>> There are two things here:
On Thu, 20 Jul 2017 12:17:12 +0100
Robin Murphy wrote:
> On 20/07/17 10:10, Will Deacon wrote:
> > On Thu, Jul 20, 2017 at 09:32:00AM +0530, Anup Patel wrote:
> >> On Wed, Jul 19, 2017 at 5:23 PM, Will Deacon wrote:
> >>> There are two things here:
> >>>
> >>> 1. iommu_present() is pretty
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> This series adds support for ARM Coresight SoC-600 IP, which implements
> Coresight V3 architecture. It also does some clean up of the replicator
> driver namings used in the driver to prevent confusions to the user.
>
>
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> This series adds support for ARM Coresight SoC-600 IP, which implements
> Coresight V3 architecture. It also does some clean up of the replicator
> driver namings used in the driver to prevent confusions to the user.
>
> The SoC-600 comes with
On Mon, 24 Jul 2017, Johan Hovold wrote:
> On Mon, Jul 24, 2017 at 10:38:41AM -0400, Alan Stern wrote:
> > On Mon, 24 Jul 2017, Johan Hovold wrote:
> >
> > > Make sure that the controller is runtime resumed when system suspending
> > > to avoid an external abort when accessing the interrupt
On Mon, 24 Jul 2017, Johan Hovold wrote:
> On Mon, Jul 24, 2017 at 10:38:41AM -0400, Alan Stern wrote:
> > On Mon, 24 Jul 2017, Johan Hovold wrote:
> >
> > > Make sure that the controller is runtime resumed when system suspending
> > > to avoid an external abort when accessing the interrupt
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> The coresight SoC 600 supports ETR save-restore which allows us
> to restore a trace session by retaining the RRP/RWP/STS.Full values
> when the TMC leaves the Disabled state. However, the TMC doesn't
> have a
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> The coresight SoC 600 supports ETR save-restore which allows us
> to restore a trace session by retaining the RRP/RWP/STS.Full values
> when the TMC leaves the Disabled state. However, the TMC doesn't
> have a scatter-gather unit in built.
>
>
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> Coresight TMC splits 64bit registers into a pair of 32bit registers
> (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K
On 20 July 2017 at 04:17, Suzuki K Poulose wrote:
> Coresight TMC splits 64bit registers into a pair of 32bit registers
> (e.g DBA, RRP, RWP). Provide helpers to read/write to these registers.
>
> Cc: Mathieu Poirier
> Signed-off-by: Suzuki K Poulose
> ---
>
To be able to use the common 4k zero page in DAX we need to have our PTE
fault path look more like our PMD fault path where a PTE entry can be
marked as dirty and writeable as it is first inserted rather than waiting
for a follow-up dax_pfn_mkwrite() => finish_mkwrite_fault() call.
Right now we
To be able to use the common 4k zero page in DAX we need to have our PTE
fault path look more like our PMD fault path where a PTE entry can be
marked as dirty and writeable as it is first inserted rather than waiting
for a follow-up dax_pfn_mkwrite() => finish_mkwrite_fault() call.
Right now we
On Wed, Jul 19, 2017 at 10:58 AM, Thomas Garnier wrote:
> The work pending loop can call set_fs after addr_limit_user_check
> removed the _TIF_FSCHECK flag. To prevent the infinite loop, move
> the addr_limit_user_check call at the beginning of the loop.
>
> Fixes:
On Wed, Jul 19, 2017 at 10:58 AM, Thomas Garnier wrote:
> The work pending loop can call set_fs after addr_limit_user_check
> removed the _TIF_FSCHECK flag. To prevent the infinite loop, move
> the addr_limit_user_check call at the beginning of the loop.
>
> Fixes: 73ac5d6a2b6a ("arm/syscalls:
Now that we no longer insert struct page pointers in DAX radix trees the
page cache code no longer needs to know anything about DAX exceptional
entries. Move all the DAX exceptional entry definitions from dax.h to
fs/dax.c.
Signed-off-by: Ross Zwisler
Suggested-by:
Now that we no longer insert struct page pointers in DAX radix trees the
page cache code no longer needs to know anything about DAX exceptional
entries. Move all the DAX exceptional entry definitions from dax.h to
fs/dax.c.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
Reviewed-by: Jan
dax_load_hole() will soon need to call dax_insert_mapping_entry(), so it
needs to be moved lower in dax.c so the definition exists.
dax_wake_mapping_entry_waiter() will soon be removed from dax.h and be made
static to dax.c, so we need to move its definition above all its callers.
Signed-off-by:
dax_load_hole() will soon need to call dax_insert_mapping_entry(), so it
needs to be moved lower in dax.c so the definition exists.
dax_wake_mapping_entry_waiter() will soon be removed from dax.h and be made
static to dax.c, so we need to move its definition above all its callers.
Signed-off-by:
Now that we no longer insert struct page pointers in DAX radix trees we can
remove the special casing for DAX in page_cache_tree_insert(). This also
allows us to make dax_wake_mapping_entry_waiter() local to fs/dax.c,
removing it from dax.h.
Signed-off-by: Ross Zwisler
When servicing mmap() reads from file holes the current DAX code allocates
a page cache page of all zeroes and places the struct page pointer in the
mapping->page_tree radix tree. This has three major drawbacks:
1) It consumes memory unnecessarily. For every 4k page that is read via a
DAX
Now that we no longer insert struct page pointers in DAX radix trees we can
remove the special casing for DAX in page_cache_tree_insert(). This also
allows us to make dax_wake_mapping_entry_waiter() local to fs/dax.c,
removing it from dax.h.
Signed-off-by: Ross Zwisler
Suggested-by: Jan Kara
When servicing mmap() reads from file holes the current DAX code allocates
a page cache page of all zeroes and places the struct page pointer in the
mapping->page_tree radix tree. This has three major drawbacks:
1) It consumes memory unnecessarily. For every 4k page that is read via a
DAX
Changes since v4:
- Added static __vm_insert_mixed() to mm/memory.c that holds the common
code for both vm_insert_mixed() and vm_insert_mixed_mkwrite() so we
don't have duplicate code and we don't have to pass boolean flags
around. (Dan & Jan)
- Added a comment for the PFN sanity
Changes since v4:
- Added static __vm_insert_mixed() to mm/memory.c that holds the common
code for both vm_insert_mixed() and vm_insert_mixed_mkwrite() so we
don't have duplicate code and we don't have to pass boolean flags
around. (Dan & Jan)
- Added a comment for the PFN sanity
This reverts the change of commit f85c758dbee54cc3612a6e873ef7cecdb66ebee5,
as the behavior it modified was intended.
The VM is running in 32-bit PAE mode, and Table 4-7 of the Intel manual
says:
Table 4-7. Use of CR3 with PAE Paging
Bit Position(s) Contents
4:0 Ignored
31:5
This reverts the change of commit f85c758dbee54cc3612a6e873ef7cecdb66ebee5,
as the behavior it modified was intended.
The VM is running in 32-bit PAE mode, and Table 4-7 of the Intel manual
says:
Table 4-7. Use of CR3 with PAE Paging
Bit Position(s) Contents
4:0 Ignored
31:5
On Mon, Jul 17, 2017 at 03:39:55PM +0200, Sebastian Reichel wrote:
> From: Milo Kim
>
> Add DT binding for ti-lmu devices.
>
> Signed-off-by: Milo Kim
> Signed-off-by: Sebastian Reichel
> ---
>
On Mon, Jul 17, 2017 at 03:39:55PM +0200, Sebastian Reichel wrote:
> From: Milo Kim
>
> Add DT binding for ti-lmu devices.
>
> Signed-off-by: Milo Kim
> Signed-off-by: Sebastian Reichel
> ---
> .../bindings/leds/backlight/ti-lmu-backlight.txt | 66
> ++
> 1 file
On 07/20/2017 06:57 AM, Egil Hjelmeland wrote:
> Workaround for dsa_switch_mdb_add adding CPU port to group,
> but forgetting to remove it:
>
> Remove port 0 if only port 0 is only port left.
>
> Signed-off-by: Egil Hjelmeland
> ---
> drivers/net/dsa/lan9303-core.c
On 07/20/2017 06:57 AM, Egil Hjelmeland wrote:
> Workaround for dsa_switch_mdb_add adding CPU port to group,
> but forgetting to remove it:
>
> Remove port 0 if only port 0 is only port left.
>
> Signed-off-by: Egil Hjelmeland
> ---
> drivers/net/dsa/lan9303-core.c | 11 +++
> 1 file
Hi Jeffy,
> Currently we are calling usb_submit_urb directly to submit deferred tx
> urbs after unanchor them.
>
> So the usb_giveback_urb_bh would failed to unref it in usb_unanchor_urb
> and cause memory leak:
> unreferenced object 0xffc0ce0fa400 (size 256):
> ...
> backtrace:
>[]
Hi Jeffy,
> Currently we are calling usb_submit_urb directly to submit deferred tx
> urbs after unanchor them.
>
> So the usb_giveback_urb_bh would failed to unref it in usb_unanchor_urb
> and cause memory leak:
> unreferenced object 0xffc0ce0fa400 (size 256):
> ...
> backtrace:
>[]
On 07/20/2017 06:42 AM, Egil Hjelmeland wrote:
> Must be set to 1 by user space when STP is used on the lan9303.
> If bridging without local STP, leave at 0, so external STP BPDUs
> are forwarded.
>
> Hopefully the kernel can be improved so the driver can handle this
> without user intervention,
On 07/20/2017 06:42 AM, Egil Hjelmeland wrote:
> Must be set to 1 by user space when STP is used on the lan9303.
> If bridging without local STP, leave at 0, so external STP BPDUs
> are forwarded.
>
> Hopefully the kernel can be improved so the driver can handle this
> without user intervention,
On 07/23/2017 07:15 PM, Huang, Ying wrote:
> Hi, Tim,
>
> Tim Chen writes:
>
>> We will only reach the lock initialization code
>> in alloc_swap_slot_cache when the cpu's swap_slots_cache's slots
>> have not been allocated and swap_slots_cache has not been
On 07/23/2017 07:15 PM, Huang, Ying wrote:
> Hi, Tim,
>
> Tim Chen writes:
>
>> We will only reach the lock initialization code
>> in alloc_swap_slot_cache when the cpu's swap_slots_cache's slots
>> have not been allocated and swap_slots_cache has not been initialized
>> previously. So the
Hi,
On 07/24/2017 07:47 AM, Egil Hjelmeland wrote:
> This series extends the LAN9303 3 port switch DSA driver. Highlights:
> - Make the MDIO interface work
> - Bridging: Unicast offload
> - Bridging: Added fdb/mdb handling
> - Bridging: STP support
> - Documentation
>
> The last three
Hi,
On 07/24/2017 07:47 AM, Egil Hjelmeland wrote:
> This series extends the LAN9303 3 port switch DSA driver. Highlights:
> - Make the MDIO interface work
> - Bridging: Unicast offload
> - Bridging: Added fdb/mdb handling
> - Bridging: STP support
> - Documentation
>
> The last three
On 07/20/2017 03:35 AM, Egil Hjelmeland wrote:
> Saving 2628 bytes.
>
> Signed-off-by: Egil Hjelmeland
Reviewed-by: Florian Fainelli
--
Florian
On 07/20/2017 03:35 AM, Egil Hjelmeland wrote:
> Saving 2628 bytes.
>
> Signed-off-by: Egil Hjelmeland
Reviewed-by: Florian Fainelli
--
Florian
On 07/20/2017 01:49 AM, Egil Hjelmeland wrote:
> Added read only file /sys/class/net//lan9303/alr_dump,
> that output 168 first ALR entires.
>
> Currently "bridge fdb show" does not include the CPU port, while
> "alr_dump" list all three ports per entry.
Agreed, and this is a limitation we would
On 07/20/2017 01:49 AM, Egil Hjelmeland wrote:
> Added read only file /sys/class/net//lan9303/alr_dump,
> that output 168 first ALR entires.
>
> Currently "bridge fdb show" does not include the CPU port, while
> "alr_dump" list all three ports per entry.
Agreed, and this is a limitation we would
On Mon, Jul 24, 2017 at 01:04:13PM -0300, Mauro Carvalho Chehab wrote:
> If the Kernel force those users to use ghes_edac by default,
> they they won't see the error counts anymore, but, instead,
> hardware reports that the memories need to be replaced.
This is exactly why I'm trying to load
On Mon, Jul 24, 2017 at 01:04:13PM -0300, Mauro Carvalho Chehab wrote:
> If the Kernel force those users to use ghes_edac by default,
> they they won't see the error counts anymore, but, instead,
> hardware reports that the memories need to be replaced.
This is exactly why I'm trying to load
On Wed, Jul 19, 2017 at 12:16:24PM +0100, Juri Lelli wrote:
> On 19/07/17 13:00, Peter Zijlstra wrote:
> > On Wed, Jul 19, 2017 at 10:20:29AM +0100, Juri Lelli wrote:
> > > On 19/07/17 09:21, Peter Zijlstra wrote:
> > > > On Wed, Jul 05, 2017 at 09:59:05AM +0100, Juri Lelli wrote:
> > > > > @@
On Wed, Jul 19, 2017 at 12:16:24PM +0100, Juri Lelli wrote:
> On 19/07/17 13:00, Peter Zijlstra wrote:
> > On Wed, Jul 19, 2017 at 10:20:29AM +0100, Juri Lelli wrote:
> > > On 19/07/17 09:21, Peter Zijlstra wrote:
> > > > On Wed, Jul 05, 2017 at 09:59:05AM +0100, Juri Lelli wrote:
> > > > > @@
On Mon, Jul 17, 2017 at 01:33:30PM +0300, Todor Tomov wrote:
> Add DT binding document for Qualcomm Camera subsystem driver.
>
> CC: Rob Herring
> CC: devicet...@vger.kernel.org
> Signed-off-by: Todor Tomov
> ---
>
On Mon, Jul 17, 2017 at 01:33:30PM +0300, Todor Tomov wrote:
> Add DT binding document for Qualcomm Camera subsystem driver.
>
> CC: Rob Herring
> CC: devicet...@vger.kernel.org
> Signed-off-by: Todor Tomov
> ---
> .../devicetree/bindings/media/qcom,camss.txt | 191
>
On 24/07/17 11:29, Suzuki K Poulose wrote:
> Add a helper to map a device node to a logical CPU number to avoid
> duplication. Currently this is open coded in different places (e.g
> gic-v3, coresight). The helper tries to map device node to a "possible"
> logical CPU id, which may not be online
On 24/07/17 11:29, Suzuki K Poulose wrote:
> Add a helper to map a device node to a logical CPU number to avoid
> duplication. Currently this is open coded in different places (e.g
> gic-v3, coresight). The helper tries to map device node to a "possible"
> logical CPU id, which may not be online
Hi Michal,
[auto build test ERROR on mmotm/master]
[also build test ERROR on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michal-Hocko/mm-oom-allow-oom-reaper-to-race
Hi Michal,
[auto build test ERROR on mmotm/master]
[also build test ERROR on v4.13-rc2 next-20170724]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michal-Hocko/mm-oom-allow-oom-reaper-to-race
[ Trimming CC list ]
On 19/07/2017 21:07, Doug Berger wrote:
> From: Florian Fainelli
>
> The only usage of the irq_gc_mask_disable_reg_and_ack() function
> is by the Tango irqchip driver. This usage is replaced by the
> irq_gc_mask_disable_and_ack_set() function since it
[ Trimming CC list ]
On 19/07/2017 21:07, Doug Berger wrote:
> From: Florian Fainelli
>
> The only usage of the irq_gc_mask_disable_reg_and_ack() function
> is by the Tango irqchip driver. This usage is replaced by the
> irq_gc_mask_disable_and_ack_set() function since it provides the
>
On Tue, Jul 18, 2017 at 08:58:50AM +0800, Caesar Wang wrote:
> Rob,
>
> 在 2017年07月18日 04:07, Rob Herring 写道:
> > On Mon, Jul 17, 2017 at 04:14:28PM +0800, Caesar Wang wrote:
> > > This patch adds the MALI's power-model to set the IPA model to be used
> > > for power management.
> > What's IPA?
On Tue, Jul 18, 2017 at 08:58:50AM +0800, Caesar Wang wrote:
> Rob,
>
> 在 2017年07月18日 04:07, Rob Herring 写道:
> > On Mon, Jul 17, 2017 at 04:14:28PM +0800, Caesar Wang wrote:
> > > This patch adds the MALI's power-model to set the IPA model to be used
> > > for power management.
> > What's IPA?
On Mon, Jul 24, 2017 at 03:56:27PM +, Kani, Toshimitsu wrote:
> Yes, Mauro has already pointed this out. As I replied to him, we do
> have a separate series of platforms that do not have built-in RAS, and
So this whitelist entry
+static struct acpi_oemlist oemlist[] = {
+ {"HPE ",
On Mon, Jul 24, 2017 at 03:56:27PM +, Kani, Toshimitsu wrote:
> Yes, Mauro has already pointed this out. As I replied to him, we do
> have a separate series of platforms that do not have built-in RAS, and
So this whitelist entry
+static struct acpi_oemlist oemlist[] = {
+ {"HPE ",
On 24/07/17 19:35, Thomas Gleixner wrote:
On Mon, 24 Jul 2017, Martin Peres wrote:
On 24/07/17 18:28, Thomas Gleixner wrote:
Output of 'cat /proc/interrupts' and a description what kind of 'old' Intel
platform that is.
Sorry, I should have repeated the name outside of just the subject of the
On 24/07/17 19:35, Thomas Gleixner wrote:
On Mon, 24 Jul 2017, Martin Peres wrote:
On 24/07/17 18:28, Thomas Gleixner wrote:
Output of 'cat /proc/interrupts' and a description what kind of 'old' Intel
platform that is.
Sorry, I should have repeated the name outside of just the subject of the
On 07/24/2017 08:14 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> dsa_is_cpu_port() checking ds->cpu_port_mask is not available in
> ds->ops->get_tag_protocol
>
> Since commit 14be36c2c96c ("net: dsa: Initialize all CPU and enabled
> ports masks in
On 07/24/2017 08:14 AM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> dsa_is_cpu_port() checking ds->cpu_port_mask is not available in
> ds->ops->get_tag_protocol
>
> Since commit 14be36c2c96c ("net: dsa: Initialize all CPU and enabled
> ports masks in dsa_ds_parse()") So force returning
On Mon, Jul 24, 2017 at 9:26 AM, Anup Patel wrote:
> Hi Jassi,
>
> Sorry for the delayed response...
>
> On Fri, Jul 21, 2017 at 9:16 PM, Jassi Brar wrote:
>> Hi Anup,
>>
>> On Fri, Jul 21, 2017 at 12:25 PM, Anup Patel
On Mon, Jul 24, 2017 at 9:26 AM, Anup Patel wrote:
> Hi Jassi,
>
> Sorry for the delayed response...
>
> On Fri, Jul 21, 2017 at 9:16 PM, Jassi Brar wrote:
>> Hi Anup,
>>
>> On Fri, Jul 21, 2017 at 12:25 PM, Anup Patel wrote:
>>> The Broadcom FlexRM ring (i.e. mailbox channel) can handle
>>>
On Mon, 24 Jul 2017, Martin Peres wrote:
> On 24/07/17 18:28, Thomas Gleixner wrote:
> > Output of 'cat /proc/interrupts' and a description what kind of 'old' Intel
> > platform that is.
>
> Sorry, I should have repeated the name outside of just the subject of the
> email. It is an Intel Eagle
On Mon, 24 Jul 2017, Martin Peres wrote:
> On 24/07/17 18:28, Thomas Gleixner wrote:
> > Output of 'cat /proc/interrupts' and a description what kind of 'old' Intel
> > platform that is.
>
> Sorry, I should have repeated the name outside of just the subject of the
> email. It is an Intel Eagle
On 24/07/17 17:00, Rob Herring wrote:
> On Mon, Jul 24, 2017 at 8:55 AM, Sudeep Holla wrote:
>> Instead of the callsites choosing between of_cpu_device_node_get if the
>> CPUs are registered as of_node is populated by then and of_get_cpu_node
>> when the CPUs are not yet
On 24/07/17 17:00, Rob Herring wrote:
> On Mon, Jul 24, 2017 at 8:55 AM, Sudeep Holla wrote:
>> Instead of the callsites choosing between of_cpu_device_node_get if the
>> CPUs are registered as of_node is populated by then and of_get_cpu_node
>> when the CPUs are not yet registered as CPU
On Wed, Jul 19, 2017 at 2:58 AM, Xin Long wrote:
> On Wed, Jul 19, 2017 at 3:02 AM, Alexander Potapenko
> wrote:
>> On Tue, Jul 18, 2017 at 4:55 PM, Alexander Potapenko
>> wrote:
>>> KMSAN reported use of uninitialized
On Wed, Jul 19, 2017 at 2:58 AM, Xin Long wrote:
> On Wed, Jul 19, 2017 at 3:02 AM, Alexander Potapenko
> wrote:
>> On Tue, Jul 18, 2017 at 4:55 PM, Alexander Potapenko
>> wrote:
>>> KMSAN reported use of uninitialized sctp_addr->v4.sin_addr.s_addr and
>>> sctp_addr->v6.sin6_scope_id in
On Mon, Jul 24, 2017 at 08:09:15AM -0700, Andrey Smirnov wrote:
> Cc: cphe...@gmail.com
> Cc: Lucas Stach
> Cc: Nikita Yushchenko
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc:
On Mon, Jul 24, 2017 at 08:09:15AM -0700, Andrey Smirnov wrote:
> Cc: cphe...@gmail.com
> Cc: Lucas Stach
> Cc: Nikita Yushchenko
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: devicet...@vger.kernel.org
> Acked-for-MFD-by: Lee Jones
> Signed-off-by: Andrey Smirnov
> ---
>
On 24/07/17 16:41, Jassi Brar wrote:
> On Mon, Jul 24, 2017 at 3:20 PM, Sudeep Holla wrote:
>>
>>
>> On 08/07/17 06:32, Jassi Brar wrote:
>>> Hi Roy, Matt, Nishant, Harb Abdulhamid, Loc,
>>>
>>> I have a gut feeling you guys were part of the SCMI spec committee. If
>>> so,
On 24/07/17 16:41, Jassi Brar wrote:
> On Mon, Jul 24, 2017 at 3:20 PM, Sudeep Holla wrote:
>>
>>
>> On 08/07/17 06:32, Jassi Brar wrote:
>>> Hi Roy, Matt, Nishant, Harb Abdulhamid, Loc,
>>>
>>> I have a gut feeling you guys were part of the SCMI spec committee. If
>>> so, could you please
Hi Namhyung,
On Mon, 2017-07-24 at 00:12 +0900, Namhyung Kim wrote:
> On Mon, Jun 26, 2017 at 05:49:24PM -0500, Tom Zanussi wrote:
> > Add an 'onmatch(matching.event).(param list)'
> > hist trigger action which is invoked with the set of variables or
> > event fields named in the 'param list'.
Hi Namhyung,
On Mon, 2017-07-24 at 00:12 +0900, Namhyung Kim wrote:
> On Mon, Jun 26, 2017 at 05:49:24PM -0500, Tom Zanussi wrote:
> > Add an 'onmatch(matching.event).(param list)'
> > hist trigger action which is invoked with the set of variables or
> > event fields named in the 'param list'.
On Wed, Jul 19, 2017 at 03:42:42PM +0530, Viresh Kumar wrote:
> The policy->transition_delay_us field is used only by the schedutil
> governor currently, and this field describes how fast the driver wants
> the cpufreq governor to change CPUs frequency. It should rather be a
> common thing across
On Wed, Jul 19, 2017 at 03:42:42PM +0530, Viresh Kumar wrote:
> The policy->transition_delay_us field is used only by the schedutil
> governor currently, and this field describes how fast the driver wants
> the cpufreq governor to change CPUs frequency. It should rather be a
> common thing across
On Fri, Jul 21, 2017 at 11:26:59AM +0800, Guochun Mao wrote:
> Add "mediatek,mt2712-nor" and "mediatek,mt7622-nor"
> for nor flash node's compatible.
The subject could be improved because it is exactly the same as the last
patch adding the 2701 and 7623. Also, use "dt-bindings: mtd: ..." for
On Fri, Jul 21, 2017 at 11:26:59AM +0800, Guochun Mao wrote:
> Add "mediatek,mt2712-nor" and "mediatek,mt7622-nor"
> for nor flash node's compatible.
The subject could be improved because it is exactly the same as the last
patch adding the 2701 and 7623. Also, use "dt-bindings: mtd: ..." for
STM32 ADC allows each channel to be sampled with a different sampling time,
by setting SMPR registers. Basically, value depends on local electrical
properties. Selecting correct value for sampling time highly depends on
analog source impedance. There is a manual that may help in this process:
'How
STM32 ADC allows each channel to be sampled with a different sampling time,
by setting SMPR registers. Basically, value depends on local electrical
properties. Selecting correct value for sampling time highly depends on
analog source impedance. There is a manual that may help in this process:
'How
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