On Sat, Jul 29, 2017 at 1:22 AM, Greg KH wrote:
> Ok, do some of these need to go to Linus now for 4.13-final and to the
> stable trees to match up with the 3 that are already proposed for the
> stable trees? If so, which ones?
"fix proc->tsk check" is a fix for "c4ea41ba195d ("binder: use group
On Mon 31-07-17 12:13:33, Wei Wang wrote:
> Ballooned pages will be marked as MADV_DONTNEED by the hypervisor and
> shouldn't be given to the host ksmd to scan.
Could you point me where this MADV_DONTNEED is done, please?
> Therefore, it is not
> necessary to zero ballooned pages, which is very t
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness
The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the
A sockaddr_in structure on the stack getting passed into rdma_ip2gid
triggers this warning, since we memcpy into a larger sockaddr_in6
structure:
In function 'memcpy',
inlined from 'rdma_ip2gid' at include/rdma/ib_addr.h:175:3,
inlined from 'addr_event.isra.4.constprop' at
drivers/infinib
On Fri 28-07-17 13:48:28, Mike Kravetz wrote:
> On 07/26/2017 03:50 AM, Michal Hocko wrote:
> > Hi,
> > I've just noticed that alloc_gigantic_page ignores movability of the
> > gigantic page and it uses any existing zone. Considering that
> > hugepage_migration_supported only supports 2MB and pgd l
On Sat 29-07-17 16:33:35, kbuild test robot wrote:
> Hi Michal,
>
> [auto build test ERROR on cgroup/for-next]
> [also build test ERROR on v4.13-rc2 next-20170728]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://github
Adding required device node for couple of DWC3 controllers
present on msm8996 chipset to enable High speed and Super
speed USB support.
Signed-off-by: Vivek Gautam
---
.../boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi| 24 +
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 34 +
Adding patches to enable qusb2 and qmp phy controller for PCIe and USB,
and to enable USB 2.0 and 3.0 support on msm8996 chipset.
Enabling the support for apq8096-db820c board.
Patch series dependencies:
1) Glink-rpm device tree support for 8996:
https://www.spinics.net/lists/linux-arm-msm/msg2
Adding device node for QUSB2 phy and the required infrastructure
to enable support for the same. This phy is used by dwc3 controller
present on msm8996.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 8 +
arch/arm64/boot/dts/qcom/msm8996.dtsi| 51
Add required device node for QMP phy based 3-lane PCIe phy
present on msm8996 chipset to enable support for the same.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4 ++
arch/arm64/boot/dts/qcom/msm8996.dtsi| 62
2 files chan
Adding required device node for USB3 QMP phy present on
msm8996 chipset to enable support for the same. This phy
provides super speed usb functionality for dwc3 controller
on msm8996.
Signed-off-by: Vivek Gautam
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 4
arch/arm64/boot/dts/qcom
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness
The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the
On Fri 28-07-17 15:41:47, Greg KH wrote:
> On Fri, Jul 28, 2017 at 03:53:35PM +0200, Michal Hocko wrote:
> > JFYI. We have encountered a regression after applying this patch on a
> > large ppc machine. While the patch is the right thing to do it doesn't
> > work well with the current vmalloc area s
On 26/07/17 17:02, Ludovic Desroches wrote:
> When the device is non removable, the card detect signal is often use
use -> used
> for another purpose i.e. muxed to another SoC peripheral or used as a
> GPIO. It could lead to wrong behaviors depending the defaut value of
defaut -> default
> this
On Sun, Jul 30, 2017 at 7:45 PM, Joe Perches wrote:
> By default, debug logging is disabled by CC_DEBUG not being defined.
>
> Convert SSI_LOG_DEBUG to use no_printk instead of an empty define
> to validate formats and arguments.
>
> Fix fallout.
>
> Miscellanea:
>
> o One of the conversions now u
v6:
Added 'Reviewed-by: Vivek Gautam ' and fixed
white space issues as mentioned by Vivek.
phy: qcom-qmp: Fix phy pipe clock name
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
v5:
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Renamed phy_phy cl
Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of assuming
the name of the clock, fetch it from the DT.
Revie
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 124
1 file changed, 124 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b
This patch is to implement the new ioctl VFIO_IOMMU_GET_DIRTY_BITMAP
to fulfill the requirement for vfio-mdev device live migration, which
need copy the memory that has been pinned in iommu container to the
target VM for mdev device status restore.
Signed-off-by: Yulei Zhang
---
drivers/vfio/vfi
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 133 +++-
1 file c
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff --
Hi all,
Changes since 20170728:
The rdma tree gained a build failure so I used the version from
next-20170728.
The drm tree gained a conflict against Linus' tree.
The rcu tree gained a conflict against the tip tree.
Non-merge commits (relative to Linus' tree): 3288
3279 files changed, 115355
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
The core init is the similar to the existing SoC, however the
clocks and reset lines differ.
S
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt |
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Reviewed-by: Vivek Gautam
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8
1 file changed, 8 insertions(+)
diff --git
On 07/29/2017 03:37 AM, Alexandru Gagniuc wrote:
Signed-off-by: Alexandru Gagniuc
---
arch/arc/boot/dts/adaptrum_anarion.dtsi | 107
arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 49 +
2 files changed, 156 insertions(+)
create mode 100644 arch/
On 7/30/17 12:07 AM, Mike Rapoport wrote:
On Thu, Jul 27, 2017 at 10:18:40PM -0400, Prakash Sangappa wrote:
This patch adds tests for UFFD_FEATURE_SIGBUS feature. The
tests will verify signal delivery instead of userfault events.
Also, test use of UFFDIO_COPY to allocate memory and retry
acces
This patch adds tests for UFFD_FEATURE_SIGBUS feature. The
tests will verify signal delivery instead of userfault events.
Also, test use of UFFDIO_COPY to allocate memory and retry
accessing monitored area after signal delivery.
This patch also fixes a bug in uffd_poll_thread() where 'uffd'
is lea
For LD11/LD20 SoCs (capable of per-pin input enable), iectrl bits are
located across multiple registers. So, the register offset must be
taken into account. Otherwise, wrong input-enable status is displayed.
While we here, rename the macro because it is a base address.
Fixes: aa543888ca8c ("pin
All UniPhier pinctrl drivers are built-in. Exporting the symbol
is meaningless.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
b/drivers/pinctrl/uniphier/
Add pin configuration and pinmux support for UniPhier PXs3 SoC.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/Kconfig | 4 +
drivers/pinctrl/uniphier/Makefile| 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 989 +++
Save registers lost in the sleep when suspending, and restore them
when resuming.
Signed-off-by: Masahiro Yamada
---
drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 178 +++
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 1 +
drivers/pinctrl/uniphier/pinctrl-uniphie
For LD11/20 SoCs (capable of per-pin input enable), the iectrl bit
number matches its pin number. So, this is redundant information.
Instead, we just need a flag to know if the iectrl gating exists or not.
With this refactoring, 5 bits in pin data will be saved.
Signed-off-by: Masahiro Yamada
-
This series includes:
- Clean up redundant pin data
- Add simple suspend / resume support
- Add a driver for a new SoC
Masahiro Yamada (6):
pinctrl: uniphier: remove unneeded EXPORT_SYMBOL_GPL()
pinctrl: uniphier: fix pin_config_get() for input-enable
pinctrl: uniphier: clean up GPIO
On 07/28/2017 12:02 AM, Mathieu Desnoyers wrote:
- On Jul 27, 2017, at 4:58 PM, Mathieu Desnoyers
mathieu.desnoy...@efficios.com wrote:
- On Jul 27, 2017, at 4:37 PM, Paul E. McKenney paul...@linux.vnet.ibm.com
wrote:
On Thu, Jul 27, 2017 at 11:04:13PM +0300, Avi Kivity wrote:
[..
Am 29.07.2017 um 07:59 schrieb Julia Lawall:
> The mmc_host_ops structure is only stored in the ops field of an
> mmc_host structure, which is declared as const. Thus the mmc_host_ops
> structure itself can be const.
>
> Done with the help of Coccinelle.
>
> //
> @r disable optional_qualifier@
>
Hi,
On 07/31/2017 11:09 AM, Varadarajan Narayanan wrote:
Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of
When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Fix define but not used warning
drivers/i2c/busses/i2c-uniphier.c | 40 ++-
When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Fix define but not used warning
drivers/i2c/busses/i2c-uniphier-f.c | 46 +
When resuming, set up registers that have been lost in the sleep state.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- Fix define but not used warning
drivers/bus/uniphier-system-bus.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/bus/uniphier-system-bus.c
On 07/31/2017 11:09 AM, Varadarajan Narayanan wrote:
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Signed-off-by: Varadarajan Narayanan
---
Reviewed-by: Vivek Gautam
Documentation/devicetree/bindings/phy/qcom-qmp-phy.
This patch enables noirq stage GPE polling for the EC driver.
EC is a very special driver, required to work throughout the entire
suspend/resume process. Thus this patch enables IRQ polling for EC during
noirq stages to avoid all kinds of possible issues.
If this commit is bisected to be a regres
Now as GPE poller is implemented, EC driver is able to detect EC events
during suspend/resume noirq stages, we can try to move EC event handling
earlier without being worried about post-resume event stuck.
Signed-off-by: Lv Zheng
---
drivers/acpi/ec.c | 4 +++-
1 file changed, 3 insertions(+), 1
1. Problems:
EC IRQs contain transaction IRQs (OBF/IBF) and event IRQ (SCI_EVT).
Transactions are initiated by hosts. The earliest OSPMs execution of EC
transactions is from acpi_ec_transaction(), where the common EC IRQ
handling procedure - advance_transaction() - is initiated from the task
conte
EC_FLAGS_COMMAND_STORM is actually used to mask GPE during IRQ processing.
This patch cleans it up using more readable flag/function names.
Signed-off-by: Lv Zheng
---
drivers/acpi/ec.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/acpi/ec.
There is a known issue in EC event handling. This patchset tries to handle
noirq stage EC event polling to fix this known issue.
In the very early version, the EC event polling mechanism is implemented by
a kernel thread to poll EC events. Now the mechanism is implemented by a
timer ticked in noir
Hi All,
On 2017-07-17 08:45, Christoph Hellwig wrote:
Hi all,
currently the dma-mapping code doesn't have a dedicated mailing list,
and thus posts get lots on linux-kernel. I wonder if we should add
a new separate list for it, or if it makes sense to reuse the existing
iommu list given that th
Add support for the IPQ8074 PCIe controller. IPQ8074 supports
Gen 1/2, one lane, two PCIe root complex with support for MSI and
legacy interrupts, and it conforms to PCI Express Base 2.1
specification.
The core init is the similar to the existing SoC, however the
clocks and reset lines differ.
S
IPQ8074 uses QMP phy controller that provides support to PCIe and
USB. Adding dt binding information for the same.
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/
Add definitions required to enable QMP phy support for IPQ8074.
Signed-off-by: smuthayy
Signed-off-by: Varadarajan Narayanan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 124
1 file changed, 124 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b
Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt |
v5:
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
Renamed phy_phy clock as common clock
phy: qcom-qmp: Fix phy pipe clock name
Moved the DT get into the registering function
phy: qcom-qmp: Add support for IPQ8074
Place the IPQ8074 related structs similar
Presently, the phy pipe clock's name is assumed to be either
usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the
phy lane's number). However, this will not work if an SoC has
more than one instance of the phy. Hence, instead of assuming
the name of the clock, fetch it from the DT.
Signe
The phy outputs a clock that will act as the parent for
the phy's pipe clock. Add the name of this clock to the
lane's DT node.
Acked-by: Rob Herring
Signed-off-by: Varadarajan Narayanan
---
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 3 +++
1 file changed, 3 insertions(+)
diff --
Presently, when support for a new SoC is added, the driver ops
structures and functions are versioned with plain 1, 2, 3 etc.
Instead use the block IP version number.
Signed-off-by: Varadarajan Narayanan
---
drivers/pci/dwc/pcie-qcom.c | 133 +++-
1 file c
On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
wrote:
> Driver for multiplier clock is missing a call to
> ccu_frac_helper_enable() when fractional mode is selected.
>
> Add a call to ccu_frac_helper_enable().
>
> Fixes: d77e8135b340 ("clk: sunxi-ng: multiplier: Add fractional support")
> Signed
Hi Kishon,
On Tue, Jun 20, 2017 at 11:27 AM, Vivek Gautam
wrote:
> Fixing the clk enable failure path in qcom_qmp_phy_init()
> and cleanup the reset control deassertion failure path in
> qcom_qmp_phy_com_init().
>
> Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
>
>
On 28 July 2017 at 17:26, Martijn Coenen wrote:
> Commit c4ea41ba195d ("binder: use group leader instead of open thread")'
> was incomplete and didn't update a check in binder_mmap(), causing all
> mmap() calls into the binder driver to fail.
>
Fixes Android WiFi/BT regression reported on 4.13-rc
Hi Jernej,
On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
wrote:
> During development of H3 HDMI driver, I found some issues with
> setting video clock rate. It turned out that clock driver decided
> to use fractional mode and selected right frequency, but it didn't
> enable it. Additionally, f
Hi Yong,
On Mon, Jul 31, 2017 at 09:48:06AM +0800, Yong wrote:
> On Sun, 30 Jul 2017 09:08:01 +0300
> Baruch Siach wrote:
> > On Fri, Jul 28, 2017 at 06:02:33PM +0200, Maxime Ripard wrote:
> > > On Thu, Jul 27, 2017 at 01:01:35PM +0800, Yong Deng wrote:
> > > > + regmap_write(sdev->regmap,
When resuming, set up registers that have been lost in the sleep state.
Signed-off-by: Masahiro Yamada
---
drivers/bus/uniphier-system-bus.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/bus/uniphier-system-bus.c
b/drivers/bus/uniphier-system-bus.c
index 1e6e0269e
On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
wrote:
> Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
> set before returning. Because of that, unstable clock may be used.
>
> Add a wait for lock in the helper function.
>
> Signed-off-by: Jernej Skrabec
Can you provide
Hi Greg,
After merging the staging tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/staging/media/atomisp/i2c/imx/imx.c:1087:12: warning:
'imx_vcm_power_up' defined but not used [-Wunused-function]
static int imx_vcm_power_up(struct v4l2_subdev *sd)
On Mon, 2017-07-31 at 07:54 +0530, Shilpasri G Bhat wrote:
> Adds a generic powercap framework to change the system powercap
> inband through OPAL-OCC command/response interface.
>
> Signed-off-by: Shilpasri G Bhat
> ---
> Changes from V8:
> - Use __pa() while passing pointer in opal call
> - Use
On Mon, Jul 31, 2017 at 12:41 AM, Jernej Skrabec
wrote:
> N-M factor clock driver is missing a call to ccu_frac_helper_enable()
> when fractional mode is used. Additionally, most SoCs require that M
> factor must be set to 0 when fractional mode is used.
>
> Without this patch, clock keeps the old
When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.
Signed-off-by: Masahiro Yamada
---
drivers/i2c/busses/i2c-uniphier.c | 40 ++-
1 file changed, 35 insertions(+), 5 deletions(-)
di
When resuming, set up registers that have been lost in the sleep state.
Also, add clock handling in the resume / suspend hooks.
Signed-off-by: Masahiro Yamada
---
drivers/i2c/busses/i2c-uniphier-f.c | 46 +
1 file changed, 37 insertions(+), 9 deletions(-)
di
Hello. I am getting a single error message, similar to what happens in
https://patchwork.kernel.org/patch/9460075/
EXT4-fs (sdc1): Delayed block allocation failed for inode 27155438 at logical
offset 6561 with max blocks 6 with error 121
EXT4-fs (sdc1): This should not happen!! Data will be los
Hi Eric,
Thanks for the review comments...
On Sat, Jul 29, 2017 at 6:31 PM, Auger Eric wrote:
> Hi Anup,
> On 20/07/2017 13:17, Anup Patel wrote:
>> This patch adds Broadcom FlexRM low-level reset for
>> VFIO platform.
>>
>> It will do the following:
>> 1. Disable/Deactivate each FlexRM ring
>>
On Sun, Jul 30, 2017 at 8:05 PM, Andy Lutomirski wrote:
>
> This means that, when gdb saves away a regset and reloads it using
> PTRACE_SETREGS or similar, the effect is to load gs_base and then load
> gs. If gs != 0, this will blow away gs_base. Without FSGSBASE, this
> doesn't matter so much.
knav_pool_create is an exported function. In the event of a call
before knav_queue_probe, we encounter a NULL pointer dereference
in the following line. Hence return -EPROBE_DEFER to the caller till
the kdev pointer is non-NULL.
Signed-off-by: Keerthy
---
Changes in v2:
* Fixed returning an i
On 28-07-17, 22:41, Julia Lawall wrote:
> The hc_driver structure is only passed as the first argument to
> usb_create_hcd, which is declared as const. Thus the hc_driver structure
> itself can be const.
>
> Done with the help of Coccinelle.
>
> Signed-off-by: Julia Lawall
>
> ---
> drivers/s
Ballooned pages will be marked as MADV_DONTNEED by the hypervisor and
shouldn't be given to the host ksmd to scan. Therefore, it is not
necessary to zero ballooned pages, which is very time consuming when
the page amount is large. The ongoing fast balloon tests show that the
time to balloon 7G page
On Sunday 30 July 2017 04:28 PM, Axel Lin wrote:
> This fixes missing mfd_remove_devices() call when unload the module.
Reviewed-by: Keerthy
>
> Signed-off-by: Axel Lin
> ---
> drivers/mfd/lp87565.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mfd
On 29-07-17, 10:24, Ulf Hansson wrote:
> Let's invent a new genpd flag, GENPD_FLAG_PERF_STATE!
>
> The creator of the genpd then needs to set this before calling
> pm_genpd_init(). Similar as we are dealing with GENPD_FLAG_PM_CLK.
>
> The requirement for GENPD_FLAG_PERF_STATES, is to have the
> -
On Sun, Jul 30, 2017 at 9:01 PM, Dima Zavin wrote:
> In codepaths that use the begin/retry interface for reading
> mems_allowed_seq with irqs disabled, there exists a race condition that
> stalls the patch process after only modifying a subset of the
> static_branch call sites.
>
> This problem ma
In codepaths that use the begin/retry interface for reading
mems_allowed_seq with irqs disabled, there exists a race condition that
stalls the patch process after only modifying a subset of the
static_branch call sites.
This problem manifested itself as a dead lock in the slub
allocator, inside ge
On 28-07-17, 20:43, Joel Fernandes wrote:
> On Thu, Jul 27, 2017 at 11:46 PM, Viresh Kumar
> wrote:
> > On many platforms, CPUs can do DVFS across cpufreq policies. i.e CPU
> > from policy-A can change frequency of CPUs belonging to policy-B.
> >
> > This is quite common in case of ARM platforms
On 28-07-17, 14:05, Saravana Kannan wrote:
> 1. I'm not saying that. I'm saying assuming CPUs can change the freq only on
> behalf of all the CPUs in the same policy is wrong. Again, the scheduler or
> governor shouldn't even be making any of that assumption. That's a CPUfreq
> driver problem.
>
>
On 7/28/17 4:19 PM, Suman Anna wrote:
Hi Santosh,
The following series adds the DT nodes for the DSP devices present
on the Keystone2 66AK2H/K, 66AK2L and 66AK2E SoCs. They are disabled
in the base dts files, and enabled in the corresponding board files
alongside an added common reserved CMA poo
Hi Paul,
Today's linux-next merge of the rcu tree got a conflict in:
arch/x86/mm/tlb.c
between commit:
94b1b03b519b ("x86/mm: Rework lazy TLB mode and TLB freshness tracking")
from the tip tree and commit:
d7713e8f8b23 ("membarrier: Expedited private command")
from the rcu tree.
I fix
Add sd card support for hi3660 soc
Signed-off-by: Li Wei
Signed-off-by: Chen Jun
Major changes in v3:
- solve review comments from Heiner Kallweit.
*use the GENMASK and FIELD_PREP macros replace the bit shift operation.
*use usleep_range() replace udelay() and mdelay().
Major changes in
This commit modifies dw_mci_probe(), it moves reset assertion before
drv_data->init(host)
Some driver needs to access controller registers in its .init() ops. So,
in order to make such access safe, we should do controller reset before
.init() being called.
Signed-off-by: Wei Li
Signed-off-by: Gu
Hi,
On Fri, 28 Jul 2017 18:02:33 +0200
Maxime Ripard wrote:
> Hi,
>
> Thanks for the second iteration!
>
> On Thu, Jul 27, 2017 at 01:01:35PM +0800, Yong Deng wrote:
> > Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> > and CSI1 is used for parallel interface. This is
This patch add the RGA dt config of rk3288 SoC.
Signed-off-by: Jacob Chen
Signed-off-by: Yakir Yang
---
arch/arm/boot/dts/rk3288.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 1efc2f2..cea41b7 100644
---
This patch add the RGA dt config of RK3399 SoC.
Signed-off-by: Jacob Chen
Signed-off-by: Yakir Yang
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
Add DT bindings documentation for Rockchip RGA
Signed-off-by: Jacob Chen
Signed-off-by: Yakir Yang
---
.../devicetree/bindings/media/rockchip-rga.txt | 33 ++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/rockchip-rga.txt
d
At peresent, we don't have a control for Compositing and Blend.
All drivers are just doing copies while actually many hardwares
supports more functions.
So Adding V4L2 controls for Compositing and Blend, used for for
composting streams.
The values are based on porter duff operations.
Defined in b
This patch series add a v4l2 m2m drvier for rockchip RGA direct rendering based
2d graphics acceleration module.
Before, my colleague yakir have write a drm RGA drvier and send it to the lists.
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-March/416769.html
I have been asked to find
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness
The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the
Hi all-
Chang wants to get the FSGSBASE patches in. Here's a bit on a brain
dump on what I think the relevant considerations are and why I haven't
sent out my patches.
- Background -
Setting CR4.FSGSBASE has two major advantages and one major
disadvantage. The major advantages are:
-
On Thu, 2017-07-27 at 16:39 +0200, Matthias Brugger wrote:
>
> On 05/25/2017 06:02 AM, sean.w...@mediatek.com wrote:
> > From: Sean Wang
> >
> > Add support for the Bananapi R2 (BPI-R2) development board from
> > BIPAI KEJI. Detailed hardware information for BPI-R2 which could be
> > found on ht
Adds support for clearing different sensor groups. OCC inband sensor
groups like CSM, Profiler, Job Scheduler can be cleared using this
driver. The min/max of all sensors belonging to these sensor groups
will be cleared.
Signed-off-by: Shilpasri G Bhat
---
Changes from V8:
- Use mutex_lock_interr
This patch adds support to set power-shifting-ratio which hints the
firmware how to distribute/throttle power between different entities
in a system (e.g CPU v/s GPU). This ratio is used by OCC for power
capping algorithm.
Signed-off-by: Shilpasri G Bhat
---
Changes from V8:
- Use __pa() while pa
Adds a generic powercap framework to change the system powercap
inband through OPAL-OCC command/response interface.
Signed-off-by: Shilpasri G Bhat
---
Changes from V8:
- Use __pa() while passing pointer in opal call
- Use mutex_lock_interruptible()
- Fix error codes returned to user
- Allocate a
From: Egil Hjelmeland
Date: Sun, 30 Jul 2017 19:58:52 +0200
> This series fix the MDIO interface for the lan9303 DSA driver.
> Bugs found after testing on actual HW.
>
> This series is extracted from the first patch of my first large
> series. Significant changes from that version are:
> - use
In P9, OCC (On-Chip-Controller) supports shared memory based
commad-response interface. Within the shared memory there is an OPAL
command buffer and OCC response buffer that can be used to send
inband commands to OCC. The following commands are supported:
1) Set system powercap
2) Set CPU-GPU powe
Hi Dave,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/nouveau/nv50_display.c
between commit:
4a5431af19bc ("drm/nouveau/kms/nv50: update vblank state in response to
modeset actions")
from Linus' tree and commit:
ca814b25538a ("drm/vblank: Consistent drm_c
On Mon, Jul 31, 2017 at 2:50 AM, Phillip Lougher
wrote:
> On Thu, Jul 20, 2017 at 10:27 PM, Nick Terrell wrote:
>> Add zstd compression and decompression support to SquashFS. zstd is a
>> great fit for SquashFS because it can compress at ratios approaching xz,
>> while decompressing twice as fast
Hi Herbert,
After merging the crypto tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/crypto/ccp/ccp-ops.c: In function 'ccp_run_rsa_cmd':
drivers/crypto/ccp/ccp-ops.c:1856:3: warning: 'sb_count' may be used
uninitialized in this function [-Wmaybe-uninitialized
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