4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Al Viro
commit 49d31c2f389acfe83417083e1208422b4091cd9e upstream.
take_dentry_name_snapshot() takes a safe snapshot of dentry name;
if the name is a short one, it
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Chris Brandt
commit 9c284c41c0886f09e75c323a16278b6d353b0b4a upstream.
The existing code gives an incorrect pointer value.
The buffer pointer 'buf' was of type
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Al Viro
commit 49d31c2f389acfe83417083e1208422b4091cd9e upstream.
take_dentry_name_snapshot() takes a safe snapshot of dentry name;
if the name is a short one, it gets copied into
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Chris Brandt
commit 9c284c41c0886f09e75c323a16278b6d353b0b4a upstream.
The existing code gives an incorrect pointer value.
The buffer pointer 'buf' was of type unsigned short *, and 'count'
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Ilia Mirkin
commit a90e049cacd965dade4dae7263b4d3fd550e78b6 upstream.
GP102's cursors go from chan 17..20. Increase the array size to hold
their data properly.
Fixes:
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Ilia Mirkin
commit a90e049cacd965dade4dae7263b4d3fd550e78b6 upstream.
GP102's cursors go from chan 17..20. Increase the array size to hold
their data properly.
Fixes: e50fcff15f
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Shaohua Li
commit 16d56e2fcc1fc15b981369653c3b41d7ff0b443d upstream.
After bio is submitted, we should not clone it as its bi_iter might be
invalid by driver. This is the case of
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: Shaohua Li
commit 16d56e2fcc1fc15b981369653c3b41d7ff0b443d upstream.
After bio is submitted, we should not clone it as its bi_iter might be
invalid by driver. This is the case of
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: NeilBrown
commit 442ce0499c0535f8972b68fa1fda357357a5c953 upstream.
Prior to commit ca0daa277aca ("NFS: Cache aggressively when file is open
for writing"), NFS would
4.12-stable review patch. If anyone has any objections, please let me know.
--
From: NeilBrown
commit 442ce0499c0535f8972b68fa1fda357357a5c953 upstream.
Prior to commit ca0daa277aca ("NFS: Cache aggressively when file is open
for writing"), NFS would revalidate, or
On Wed, Aug 02, 2017 at 08:42:18PM +0100, Piotr Gregor wrote:
> Add two reasons of returning 0 value to the description
> of the pci_set_power_state to include the cases when:
>
> - the transition is to D1 or D2 but D1 and D2 are not supported
> - the transition is to D3 but D3 is not supported.
On Wed, Aug 02, 2017 at 08:42:18PM +0100, Piotr Gregor wrote:
> Add two reasons of returning 0 value to the description
> of the pci_set_power_state to include the cases when:
>
> - the transition is to D1 or D2 but D1 and D2 are not supported
> - the transition is to D3 but D3 is not supported.
On Wed, 2 Aug 2017 22:46:30 -0700 Cong Wang wrote:
> We saw many list corruption warnings on shmem shrinklist:
>
> ...
>
> The problem is that shmem_unused_huge_shrink() moves entries
> from the global sbinfo->shrinklist to its local lists and then
> releases the
On Wed, 2 Aug 2017 22:46:30 -0700 Cong Wang wrote:
> We saw many list corruption warnings on shmem shrinklist:
>
> ...
>
> The problem is that shmem_unused_huge_shrink() moves entries
> from the global sbinfo->shrinklist to its local lists and then
> releases the spinlock. However, a parallel
On Wed, Aug 02, 2017 at 10:38:21AM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 31 July 2017 12:04 PM, Varadarajan Narayanan wrote:
> > v6:
> > Added 'Reviewed-by: Vivek Gautam ' and fixed
> > white space issues as mentioned by Vivek.
> > phy:
On Wed, Aug 02, 2017 at 10:38:21AM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Monday 31 July 2017 12:04 PM, Varadarajan Narayanan wrote:
> > v6:
> > Added 'Reviewed-by: Vivek Gautam ' and fixed
> > white space issues as mentioned by Vivek.
> > phy: qcom-qmp: Fix phy pipe clock name
Preserve the module names with Makefile additions.
Signed-off-by: Peter Rosin
---
drivers/mux/Makefile | 5 +
drivers/mux/{mux-adg792a.c => adg792a.c} | 0
drivers/mux/{mux-core.c => core.c} | 0
drivers/mux/{mux-gpio.c => gpio.c} | 0
Preserve the module names with Makefile additions.
Signed-off-by: Peter Rosin
---
drivers/mux/Makefile | 5 +
drivers/mux/{mux-adg792a.c => adg792a.c} | 0
drivers/mux/{mux-core.c => core.c} | 0
drivers/mux/{mux-gpio.c => gpio.c} | 0
drivers/mux/{mux-mmio.c
On Fri, Jul 28, 2017 at 06:48:12PM +0530, Vivek Gautam wrote:
> Update the binding doc for qcom pmi8994-gpio devices.
>
> Signed-off-by: Vivek Gautam
> ---
>
> - Have been testing this patch-set on db820c for extcon with
> usb controller. The usb controller uses
On Fri, Jul 28, 2017 at 06:48:12PM +0530, Vivek Gautam wrote:
> Update the binding doc for qcom pmi8994-gpio devices.
>
> Signed-off-by: Vivek Gautam
> ---
>
> - Have been testing this patch-set on db820c for extcon with
> usb controller. The usb controller uses one of these gpios
> for
On Mon, Jul 31, 2017 at 12:04:12PM +0530, Varadarajan Narayanan wrote:
> IPQ8074 uses QMP phy controller that provides support to PCIe and
> USB. Adding dt binding information for the same.
s/ph/PHY/
s/dt/DT/ (as in previous changelog)
>
> Reviewed-by: Vivek Gautam
On Mon, Jul 31, 2017 at 12:04:12PM +0530, Varadarajan Narayanan wrote:
> IPQ8074 uses QMP phy controller that provides support to PCIe and
> USB. Adding dt binding information for the same.
s/ph/PHY/
s/dt/DT/ (as in previous changelog)
>
> Reviewed-by: Vivek Gautam
> Signed-off-by: Varadarajan
On Mon, Jul 31, 2017 at 12:04:11PM +0530, Varadarajan Narayanan wrote:
> The phy outputs a clock that will act as the parent for
> the phy's pipe clock. Add the name of this clock to the
s/phy/PHY/
> lane's DT node.
>
> Acked-by: Rob Herring
> Signed-off-by: Varadarajan
On Mon, Jul 31, 2017 at 12:04:11PM +0530, Varadarajan Narayanan wrote:
> The phy outputs a clock that will act as the parent for
> the phy's pipe clock. Add the name of this clock to the
s/phy/PHY/
> lane's DT node.
>
> Acked-by: Rob Herring
> Signed-off-by: Varadarajan Narayanan
> ---
>
On Thu, Aug 03, 2017 at 10:39:11PM +0530, Arvind Yadav wrote:
> pci_device_id are not supposed to change at runtime. All functions
> working with pci_device_id provided by work with
> const pci_device_id. So mark the non-const structs as const.
>
> Arvind Yadav (5):
> [PATCH 1/5] PCI: hotplug:
On Thu, Aug 03, 2017 at 10:39:11PM +0530, Arvind Yadav wrote:
> pci_device_id are not supposed to change at runtime. All functions
> working with pci_device_id provided by work with
> const pci_device_id. So mark the non-const structs as const.
>
> Arvind Yadav (5):
> [PATCH 1/5] PCI: hotplug:
On 2017-07-14 15:54, Daniel Vetter wrote:
> On Thu, Jul 13, 2017 at 06:25:27PM +0200, Peter Rosin wrote:
>> The legacy path implements setcmap in terms of crtc .gamma_set.
>>
>> The atomic path implements setcmap by directly updating the crtc gamma_lut
>> property.
>>
>> This has a couple of
On 2017-07-14 15:54, Daniel Vetter wrote:
> On Thu, Jul 13, 2017 at 06:25:27PM +0200, Peter Rosin wrote:
>> The legacy path implements setcmap in terms of crtc .gamma_set.
>>
>> The atomic path implements setcmap by directly updating the crtc gamma_lut
>> property.
>>
>> This has a couple of
On Thu, Jul 27, 2017 at 10:58:39AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Add support for MediaTek new generation controller and update related
> properities.
>
> Signed-off-by: Ryder Lee
> Signed-off-by: Honghui Zhang
On Thu, Jul 27, 2017 at 10:58:39AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Add support for MediaTek new generation controller and update related
> properities.
>
> Signed-off-by: Ryder Lee
> Signed-off-by: Honghui Zhang
> ---
>
On Thu, Jul 27, 2017 at 10:58:38AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Add support for new Gen2 controller which has two root ports and shares
> the probing flow with legacy controller. Currently this IP block can be
> found on MT7622/MT2712.
>
On Thu, Jul 27, 2017 at 10:58:38AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Add support for new Gen2 controller which has two root ports and shares
> the probing flow with legacy controller. Currently this IP block can be
> found on MT7622/MT2712.
>
> Signed-off-by: Ryder
On 08/01/2017 03:14 PM, David Lechner wrote:
If we return here and import_attach is true, then dma_buf_end_cpu_access()
will not be called balance dma_buf_begin_cpu_access().
Fix by setting ret instead of returning.
Signed-off-by: David Lechner
---
On 08/01/2017 03:14 PM, David Lechner wrote:
If we return here and import_attach is true, then dma_buf_end_cpu_access()
will not be called balance dma_buf_begin_cpu_access().
Fix by setting ret instead of returning.
Signed-off-by: David Lechner
---
drivers/gpu/drm/tinydrm/mipi-dbi.c | 3 ++-
On Thu, Aug 3, 2017 at 5:17 AM, Dou Liyang wrote:
> movable_node is a boot-time switch to make hot-pluggable memory
> NUMA nodes to be movable. This option is based on an assumption
> that any node which the kernel resides in is defined as
> un-hotpluggable. Linux can
On Thu, Aug 3, 2017 at 5:17 AM, Dou Liyang wrote:
> movable_node is a boot-time switch to make hot-pluggable memory
> NUMA nodes to be movable. This option is based on an assumption
> that any node which the kernel resides in is defined as
> un-hotpluggable. Linux can allocates memory near the
According to the datasheet, the range of the acceleration is [-10 g, + 10 g],
so the scale factor should be 10 instead of 5.
Signed-off-by: Dragos Bogdan
---
drivers/iio/imu/adis16480.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 08/03/2017 12:48 AM, Steven Swanson wrote:
> A brief overview is in README.md.
>
See below.
> Implementation and usage details are in Documentation/filesystems/nova.txt.
>
Reviewed in a separate email.
> These two papers provide a detailed, high-level description of NOVA's design
> goals
According to the datasheet, the range of the acceleration is [-10 g, + 10 g],
so the scale factor should be 10 instead of 5.
Signed-off-by: Dragos Bogdan
---
drivers/iio/imu/adis16480.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/imu/adis16480.c
On 08/03/2017 12:48 AM, Steven Swanson wrote:
> A brief overview is in README.md.
>
See below.
> Implementation and usage details are in Documentation/filesystems/nova.txt.
>
Reviewed in a separate email.
> These two papers provide a detailed, high-level description of NOVA's design
> goals
On 07/26, Masahiro Yamada wrote:
> This SoC is too old. It is difficult to maintain any longer.
>
> Signed-off-by: Masahiro Yamada
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative
On 07/26, Masahiro Yamada wrote:
> This SoC is too old. It is difficult to maintain any longer.
>
> Signed-off-by: Masahiro Yamada
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
This removes the call to mipi_dbi_init() from mipi_dbi_spi_init() so that
drivers can have a driver-specific implementation if needed.
Suggested-by: Noralf Trønnes
Signed-off-by: David Lechner
Reviewed-by: Noralf Trønnes
---
This removes the call to mipi_dbi_init() from mipi_dbi_spi_init() so that
drivers can have a driver-specific implementation if needed.
Suggested-by: Noralf Trønnes
Signed-off-by: David Lechner
Reviewed-by: Noralf Trønnes
---
drivers/gpu/drm/tinydrm/mi0283qt.c | 8 ++--
The goal of this series is to get the built-in LCD of the LEGO MINDSTORMS EV3
working.
v2 changes:
* Wrote a new driver for ST7586 instead of combining it with existing drivers
* Don't touch MIPI DBI code (other than the patch suggested by Noralf)
* New defconfig patch
v3 changes:
* New patch to
This adds parameters for vaddr and clip to tinydrm_xrgb_to_gray8() to
make it more generic.
dma_buf_{begin,end}_cpu_access() are moved out to the repaper driver.
Signed-off-by: David Lechner
---
drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c | 35
The goal of this series is to get the built-in LCD of the LEGO MINDSTORMS EV3
working.
v2 changes:
* Wrote a new driver for ST7586 instead of combining it with existing drivers
* Don't touch MIPI DBI code (other than the patch suggested by Noralf)
* New defconfig patch
v3 changes:
* New patch to
This adds parameters for vaddr and clip to tinydrm_xrgb_to_gray8() to
make it more generic.
dma_buf_{begin,end}_cpu_access() are moved out to the repaper driver.
Signed-off-by: David Lechner
---
drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c | 35 ++
This enables the tinydrm and ST7586 panel modules used by the display
on LEGO MINDSTORMS EV3.
Signed-off-by: David Lechner
---
arch/arm/configs/davinci_all_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/davinci_all_defconfig
This enables the tinydrm and ST7586 panel modules used by the display
on LEGO MINDSTORMS EV3.
Signed-off-by: David Lechner
---
arch/arm/configs/davinci_all_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/davinci_all_defconfig
From: Aviad Krawczyk
Date: Thu, 3 Aug 2017 17:54:09 +0800
> +static int alloc_cmd_buf(struct hinic_api_cmd_chain *chain,
> + struct hinic_api_cmd_cell *cell, int cell_idx)
> +{
> + struct hinic_hwif *hwif = chain->hwif;
> + struct pci_dev
From: Aviad Krawczyk
Date: Thu, 3 Aug 2017 17:54:09 +0800
> +static int alloc_cmd_buf(struct hinic_api_cmd_chain *chain,
> + struct hinic_api_cmd_cell *cell, int cell_idx)
> +{
> + struct hinic_hwif *hwif = chain->hwif;
> + struct pci_dev *pdev = hwif->pdev;
> +
LEGO MINDSTORMS EV3 has an LCD with a ST7586 controller. This adds a new
module for the ST7586 controller with parameters for the LEGO MINDSTORMS
EV3 LCD display.
Signed-off-by: David Lechner
---
MAINTAINERS | 6 +
drivers/gpu/drm/tinydrm/Kconfig |
LEGO MINDSTORMS EV3 has an LCD with a ST7586 controller. This adds a new
module for the ST7586 controller with parameters for the LEGO MINDSTORMS
EV3 LCD display.
Signed-off-by: David Lechner
---
MAINTAINERS | 6 +
drivers/gpu/drm/tinydrm/Kconfig | 10 +
From: Aviad Krawczyk
Date: Thu, 3 Aug 2017 17:54:08 +0800
> +static int get_capability(struct hinic_hwdev *hwdev,
> + struct hinic_dev_cap *dev_cap)
> +{
> + struct hinic_hwif *hwif = hwdev->hwif;
> + struct hinic_cap *nic_cap = >nic_cap;
From: Aviad Krawczyk
Date: Thu, 3 Aug 2017 17:54:08 +0800
> +static int get_capability(struct hinic_hwdev *hwdev,
> + struct hinic_dev_cap *dev_cap)
> +{
> + struct hinic_hwif *hwif = hwdev->hwif;
> + struct hinic_cap *nic_cap = >nic_cap;
> + int num_aeqs,
This adds a new binding for Sitronix ST7586 display panels.
Using lego as the vendor prefix in the compatible string because the display
panel I am working with is an integral part of the LEGO MINDSTORMS EV3.
Signed-off-by: David Lechner
---
This adds a new binding for Sitronix ST7586 display panels.
Using lego as the vendor prefix in the compatible string because the display
panel I am working with is an integral part of the LEGO MINDSTORMS EV3.
Signed-off-by: David Lechner
---
.../bindings/display/sitronix,st7586.txt |
This adds a new node for the LEGO MINDSTORMS EV3 LCD display.
Signed-off-by: David Lechner
---
arch/arm/boot/dts/da850-lego-ev3.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts
This adds a new node for the LEGO MINDSTORMS EV3 LCD display.
Signed-off-by: David Lechner
---
arch/arm/boot/dts/da850-lego-ev3.dts | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/da850-lego-ev3.dts
b/arch/arm/boot/dts/da850-lego-ev3.dts
index
On Wed, Jul 26, 2017 at 09:59:43PM +0100, Matt Fleming wrote:
> On Wed, 26 Jul, at 07:35:51AM, Greg KH wrote:
> >
> > If it needs a backport and a simple cherry-pick does not work, yes
> > please.
>
> Oh, it turns out cherry-picking commit 96b777452d88 to 4.9-stable
> works just fine.
Great,
On Wed, Jul 26, 2017 at 09:59:43PM +0100, Matt Fleming wrote:
> On Wed, 26 Jul, at 07:35:51AM, Greg KH wrote:
> >
> > If it needs a backport and a simple cherry-pick does not work, yes
> > please.
>
> Oh, it turns out cherry-picking commit 96b777452d88 to 4.9-stable
> works just fine.
Great,
On Fri, Jul 28, 2017 at 03:17:26PM +0200, Michal Simek wrote:
> From: Nava kishore Manne
>
> This patch fixes the below warning
> --> Use #include instead of
> --> Use #include instead of
> --> please, no space before tabs
> --> Block
On Fri, Jul 28, 2017 at 03:17:26PM +0200, Michal Simek wrote:
> From: Nava kishore Manne
>
> This patch fixes the below warning
> --> Use #include instead of
> --> Use #include instead of
> --> please, no space before tabs
> --> Block comments use a trailing
Hi,
On Mon, Jul 31, 2017 at 05:59:59PM -0700, Palmer Dabbelt wrote:
> This patch adds a driver for the Platform Level Interrupt Controller
> (PLIC) specified as part of the RISC-V supervisor level ISA manual.
> The PLIC connocts global interrupt sources to the local interrupt
Hi,
On Mon, Jul 31, 2017 at 05:59:59PM -0700, Palmer Dabbelt wrote:
> This patch adds a driver for the Platform Level Interrupt Controller
> (PLIC) specified as part of the RISC-V supervisor level ISA manual.
> The PLIC connocts global interrupt sources to the local interrupt
platform_get_irq() returns an error code, but the gpio-msic driver
ignores it and always returns -EINVAL. This is not correct, and
prevents -EPROBE_DEFER from being propagated properly.
Notice that platform_get_irq() no longer returns 0 on error:
platform_get_irq() returns an error code, but the gpio-msic driver
ignores it and always returns -EINVAL. This is not correct, and
prevents -EPROBE_DEFER from being propagated properly.
Notice that platform_get_irq() no longer returns 0 on error:
On Thu, Jul 27, 2017 at 10:58:37AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> In order to accommodate other SoC generations, this patch updates filename
> to make it more generic, regroups specific properties by SoCs, and removes
> redundant
On Thu, Jul 27, 2017 at 10:58:37AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> In order to accommodate other SoC generations, this patch updates filename
> to make it more generic, regroups specific properties by SoCs, and removes
> redundant descriptions.
>
> Signed-off-by:
On Thu, Aug 3, 2017 at 3:18 PM, Arvind Yadav wrote:
> attribute_group are not supposed to change at runtime. All functions
> working with attribute_group provided by work with
> const attribute_group. So mark the non-const structs as const.
>
> Signed-off-by: Arvind
On Thu, Aug 3, 2017 at 3:18 PM, Arvind Yadav wrote:
> attribute_group are not supposed to change at runtime. All functions
> working with attribute_group provided by work with
> const attribute_group. So mark the non-const structs as const.
>
> Signed-off-by: Arvind Yadav
Somebody else sent an
On Thu, Jul 27, 2017 at 10:58:35AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Introduce a structure "mtk_pcie_soc" to abstract the differences between
> controller generations, and the .startup() hook is used to encapsulate
> some SoC-dependent related
On Thu, Jul 27, 2017 at 10:58:35AM +0800, honghui.zh...@mediatek.com wrote:
> From: Ryder Lee
>
> Introduce a structure "mtk_pcie_soc" to abstract the differences between
> controller generations, and the .startup() hook is used to encapsulate
> some SoC-dependent related setting. In doing so,
From: Romain Perier
Date: Thu, 3 Aug 2017 09:49:03 +0200
> This operation is required for handling ioctl commands like SIOCGMIIREG,
> when debugging MDIO registers from userspace.
>
> This commit adds support for this operation.
>
> Signed-off-by: Romain Perier
From: Romain Perier
Date: Thu, 3 Aug 2017 09:49:03 +0200
> This operation is required for handling ioctl commands like SIOCGMIIREG,
> when debugging MDIO registers from userspace.
>
> This commit adds support for this operation.
>
> Signed-off-by: Romain Perier
Applied, thanks.
Currently we acknowledge errors before clearing the error status.
This could cause a new error to be populated by firmware in-between
the error acknowledgment and the error status clearing which would
cause the second error's status to be cleared without being handled.
So, clear the error status
Currently we acknowledge errors before clearing the error status.
This could cause a new error to be populated by firmware in-between
the error acknowledgment and the error status clearing which would
cause the second error's status to be cleared without being handled.
So, clear the error status
From: Salil Mehta
Date: Wed, 2 Aug 2017 16:59:44 +0100
> This patch-set contains the support of the HNS3 (Hisilicon Network Subsystem
> 3)
> Ethernet driver for hip08 family of SoCs and future upcoming SoCs.
...
Series applied, thanks.
From: Salil Mehta
Date: Wed, 2 Aug 2017 16:59:44 +0100
> This patch-set contains the support of the HNS3 (Hisilicon Network Subsystem
> 3)
> Ethernet driver for hip08 family of SoCs and future upcoming SoCs.
...
Series applied, thanks.
ACPI OEM ID / OEM Table ID / Revision can be used to identify
a platform based on ACPI firmware info. acpi_blacklisted(),
intel_pstate_platform_pwr_mgmt_exists(), and some other funcs,
have been using similar check to detect a list of platforms
that require special handlings.
Move the platform
ACPI OEM ID / OEM Table ID / Revision can be used to identify
a platform based on ACPI firmware info. acpi_blacklisted(),
intel_pstate_platform_pwr_mgmt_exists(), and some other funcs,
have been using similar check to detect a list of platforms
that require special handlings.
Move the platform
ghes_edac_register() is called for each GHES platform device
instantiated per a GHES entry in ACPI HEST table. dmi_walk()
counts the number of DIMMs on the system, and there is no need
to call it multiple times.
Change ghes_edac_register() to call dmi_walk() only when
'num_dimm' is
When 'osc_sb_apei_support_acked' is set, it indicates that
the platform supports APEI, firmware-first mode, as ACPI _OSC
capability bit 4, APEI Support, was set in query. While _OSC
is an optional method, platforms with APEI support should
implement it to inform its capability to the OS properly.
ghes_edac_register() is called for each GHES platform device
instantiated per a GHES entry in ACPI HEST table. dmi_walk()
counts the number of DIMMs on the system, and there is no need
to call it multiple times.
Change ghes_edac_register() to call dmi_walk() only when
'num_dimm' is
When 'osc_sb_apei_support_acked' is set, it indicates that
the platform supports APEI, firmware-first mode, as ACPI _OSC
capability bit 4, APEI Support, was set in query. While _OSC
is an optional method, platforms with APEI support should
implement it to inform its capability to the OS properly.
Convert to use acpi_match_oemlist() for the platform check.
There is no change in functionality.
Signed-off-by: Toshi Kani
Cc: "Rafael J. Wysocki"
Cc: Srinivas Pandruvada
Cc: Len Brown
Cc: Borislav
Convert to use acpi_match_oemlist() for the platform check.
There is no change in functionality.
Signed-off-by: Toshi Kani
Cc: "Rafael J. Wysocki"
Cc: Srinivas Pandruvada
Cc: Len Brown
Cc: Borislav Petkov
---
drivers/cpufreq/intel_pstate.c | 64
1
The ghes_edac driver was introduced in 2013 [1], but it has not
been enabled by any distro yet. This driver obtains error info
from firmware interfaces, which are not properly implemented on
many platforms, as the driver always emits the messages below:
This EDAC driver relies on BIOS to
The ghes_edac driver was introduced in 2013 [1], but it has not
been enabled by any distro yet. This driver obtains error info
from firmware interfaces, which are not properly implemented on
many platforms, as the driver always emits the messages below:
This EDAC driver relies on BIOS to
Change generic x86 edac drivers, which probe CPU type with
x86_match_cpu(), to call edac_check_mc_owner() in their
module init functions. This allows them to fail their init
at the beginning when ghes_edac is enabled. Similar change
can be made to other edac drivers as necessary.
This is an
Change generic x86 edac drivers, which probe CPU type with
x86_match_cpu(), to call edac_check_mc_owner() in their
module init functions. This allows them to fail their init
at the beginning when ghes_edac is enabled. Similar change
can be made to other edac drivers as necessary.
This is an
On Mon, Jul 24, 2017 at 08:34:02PM +0300, Andy Shevchenko wrote:
> In the future we would use dynamic allocation for IRQ which brings
> non-1:1 mapping for IOAPIC domain. Thus, we need to respect return value
> of mp_map_gsi_to_irq() and assign it back to the device structure.
>
> Besides that we
On Mon, Jul 24, 2017 at 08:34:02PM +0300, Andy Shevchenko wrote:
> In the future we would use dynamic allocation for IRQ which brings
> non-1:1 mapping for IOAPIC domain. Thus, we need to respect return value
> of mp_map_gsi_to_irq() and assign it back to the device structure.
>
> Besides that we
On 08/02/2017 06:59 AM, Linus Walleij wrote:
On Thu, Jul 20, 2017 at 12:40 AM, Gustavo A. R. Silva
wrote:
Remove unnecessary static on local variables syscon_regmap.
Such variables are initialized before being used, on every
execution path throughout the functions.
On 08/02/2017 06:59 AM, Linus Walleij wrote:
On Thu, Jul 20, 2017 at 12:40 AM, Gustavo A. R. Silva
wrote:
Remove unnecessary static on local variables syscon_regmap.
Such variables are initialized before being used, on every
execution path throughout the functions. The static has no
benefit
The ghes_edac driver was introduced in 2013 [1], but it has not been
enabled by any distro yet. This is because the driver obtains error
info from firmware interfaces, which are not properly implemented on
many platforms.
To get out from this situation, add a platform check to selectively
enable
Only a single edac driver can be enabled for EDAC MC. When ghes_edac
is enabled, a regular edac driver for the CPU type / platform still
attempts to register itself and fails in edac_mc_add_mc().
Add edac_check_mc_owner() so that regular edac drivers can check
the owner of EDAC MC at the
The ghes_edac driver was introduced in 2013 [1], but it has not been
enabled by any distro yet. This is because the driver obtains error
info from firmware interfaces, which are not properly implemented on
many platforms.
To get out from this situation, add a platform check to selectively
enable
Only a single edac driver can be enabled for EDAC MC. When ghes_edac
is enabled, a regular edac driver for the CPU type / platform still
attempts to register itself and fails in edac_mc_add_mc().
Add edac_check_mc_owner() so that regular edac drivers can check
the owner of EDAC MC at the
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