There are some resets that are not associated with gates. These are
represented by a reset controller.
Signed-off-by: Joel Stanley
---
v3:
- Add named initalisers for the reset defines
- Add define for ADC
---
drivers/clk/clk-aspeed.c | 82 +++-
i
This registers a platform driver to set up all of the non-core clocks.
The clocks that have configurable rates are now registered.
Signed-off-by: Joel Stanley
--
v4:
- Add eclk div table to fix ast2500 calculation
- Add defines to document the BIT() macros
- Pass dev where we can when regist
The majority of the clocks in the system are gates paired with a reset
controller that holds the IP in reset.
This borrows from clk_hw_register_gate, but registers two 'gates', one
to control the clock enable register and the other to control the reset
IP. This allows us to enforce the ordering:
This adds the stub of a driver for the ASPEED SoCs. The clocks are
defined and the static registration is set up.
Signed-off-by: Joel Stanley
---
v3:
- use named initlisers for aspeed_gates table
- fix clocks typo
- Move ASPEED_NUM_CLKS to the bottom of the list
- Put gates at the start of th
This registers the core clocks; those which are required to calculate
the rate of the timer peripheral so the system can load a clocksource
driver.
Signed-off-by: Joel Stanley
---
v4:
- Add defines to document the BIT() macros
v3:
- Fix ast2400 ahb calculation
- Remove incorrect 'this is w
This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from
Aspeed.
This is v4. See patches for detailed changelogs.
v4: Address review from Andrew and Stephen.
v3: Address review from Andrew and has seen more testing on hardware
v2: split the driver out into a series of patches to
On Tue, 3 Oct 2017, Michael Ellerman wrote:
> Hi Thomas,
> Unfortunately this is hitting the WARN_ON in start_wd_cpu() on powerpc
> because we're calling it multiple times for the boot CPU.
>
> The first call is via:
>
> start_wd_on_cpu+0x80/0x2f0
> watchdog_nmi_reconfigure+0x124/0x170
> so
On 10/03/2017 07:15 AM, James Bottomley wrote:
> On Mon, 2017-10-02 at 21:11 -0700, John Johansen wrote:
>> On 10/02/2017 09:02 PM, James Bottomley wrote:
>>>
>>> The specific problem is that dnsmasq refuses to start on openSUSE
>>> Leap 42.2. The specific cause is that and attempt to open a
>>> P
On Mon, 2017-10-02 at 22:25 -0500, Eric W. Biederman wrote:
> The code where it calls group_send_sig_info is buggy for pdeath_signal.
> And it no less buggy for this new case. There is no point to check
> permissions when sending a signal to yourself. Especially this signal
> gets cleared during
> On 2 Oct 2017, at 19.18, Rakesh Pandit wrote:
>
> On Mon, Oct 02, 2017 at 03:25:10PM +0300, Rakesh Pandit wrote:
>> On Mon, Oct 02, 2017 at 02:09:35PM +0200, Javier González wrote:
On 1 Oct 2017, at 15.25, Rakesh Pandit wrote:
While separating read and erase mempools in 22da65a
On 02/10/17 17:09, Linus Walleij wrote:
> On Sun, Oct 1, 2017 at 12:57 PM, Tetsuo Handa
> wrote:
>
I inserted u-SD card, only to realize that it is not detected as it
should be. And dmesg indeed reveals:
>>>
>>> Tetsuo asked me to report this to linux-mm.
>>>
>>> But 2^4 is 16 pages, II
On 09/29/2017 04:56 AM, Will Deacon wrote:
> The full fix isn't just cosmetic; it's also addressing the wider problem
> of unannotated racing page table accesses outside of the specific failure
> case we've run into.
Let us know if there are additional tests we should be running on the
Red Hat en
On 02/10/17 16:03, Pavel Machek wrote:
> On Mon 2017-10-02 14:06:03, Linus Walleij wrote:
>> On Mon, Oct 2, 2017 at 10:41 AM, Pavel Machek wrote:
>>
Bounce buffers are being removed from v4.15
>>
>> As Adrian states, this would make any last bugs go away. I would
>> even consider putting this
On 10/02/2017 10:15 PM, James Bottomley wrote:
> On Mon, 2017-10-02 at 21:11 -0700, John Johansen wrote:
>> On 10/02/2017 09:02 PM, James Bottomley wrote:
>>>
>>> The specific problem is that dnsmasq refuses to start on openSUSE
>>> Leap 42.2. The specific cause is that and attempt to open a
>>> P
In perf record, it's walked on all samples yet. So it's very easy to get
the first/last samples and save the time to perf file header via the
function write_sample_time().
In later, perf report/script will fetch the time from perf file header.
Change log:
---
v3: Remove the definitions of
perf report/script/... have a --time option to limit the time range
of output. That's very useful to slice large traces, e.g. when processing
the output of perf script for some analysis.
But right now --time only supports absolute time. Also there is no fast
way to get the start/end times of a giv
Previous patch supports the multiple time range.
For example, select the first and second 10% time slices.
perf report --time 10%/1,10%/2
We need a function to check if a timestamp is in the ranges of
[0, 10%) and [10%, 20%].
Note that it includes the last element in [10%, 20%] but it
doesn't in
perf script has a --time option to limit the time range of output.
It only supports absolute time.
Now this option is extended to support multiple time ranges and
support the percent of time.
For example:
1. Select the first and second 10% time slices
perf script --time 10%/1,10%/2
2. Select
perf report has a --time option to limit the time range of output.
It only supports absolute time.
Now this option is extended to support multiple time ranges and
support the percent of time.
For example:
1. Select the first and second 10% time slices
perf report --time 10%/1,10%/2
2. Select fr
Current perf report/script/... have a --time option to limit the time
range of output. But right now it only supports absolute time.
For easy using, now it can support a percent of time usage.
For example:
1. Select the second 10% time slice
perf report --time 10%/2
2. Select from 0% to 10%
v4:
---
1. Use perf script time style for timestamp printing. Also add with
the printing of sample duration. For example:
perf report --header
time of first sample : 5276531.323099
time of last sample : 5276555.345625
sample duration : 24022.526 ms
2. Fix an invalid time string i
On 09/22/2017 05:37 AM, Lorenzo Pieralisi wrote:
> On Thu, Sep 21, 2017 at 03:45:28PM +0800, Hanjun Guo wrote:
>> On 2017/9/21 15:12, Mayuresh Chitale wrote:
>>> This patch modifies the optee driver to add support for parsing
>>> the conduit method from an ACPI node.
>>
>> Sorry I didn't involve th
Tegra power management firmware running on co-processor (BPMP)
implements a simple pseudo file system akin to debugfs. The file
system can be used for debugging purposes to examine and change the
status of selected resources controlled by the firmware (such as
clocks, resets, voltages, powergates,
On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote:
> On 09/21, Joel Stanley wrote:
>> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char
>> *name, u32 val)
>> + /*
>> + * Memory controller (M-PLL) PLL. This clock is configured by the
>> + * bootloader, and is ex
On Tue, Oct 3, 2017 at 7:07 AM, Stephen Boyd wrote:
> On 09/21, Joel Stanley wrote:
>> The majority of the clocks in the system are gates paired with a reset
>> controller that holds the IP in reset.
>>
>> This borrows from clk_hw_register_gate, but registers two 'gates', one
>> to control the clo
On Mon, Oct 02, 2017 at 06:15:00PM +0200, Michal Hocko wrote:
> On Mon 02-10-17 17:06:38, Alexandru Moise wrote:
> > On Mon, Oct 02, 2017 at 04:27:17PM +0200, Michal Hocko wrote:
> > > On Mon 02-10-17 16:06:33, Alexandru Moise wrote:
> > > > On Mon, Oct 02, 2017 at 02:54:32PM +0200, Michal Hocko wr
This patch adds Broadcom FlexRM low-level reset for
VFIO platform.
It will do the following:
1. Disable/Deactivate each FlexRM ring
2. Flush each FlexRM ring
The cleanup sequence for FlexRM rings is adapted from
Broadcom FlexRM mailbox driver.
Signed-off-by: Anup Patel
Reviewed-by: Oza Oza
Rev
This patchset primarily adds Broadcom FlexRM reset module for
VFIO platform driver.
The patches are based on Linux-4.14-rc3 and can also be
found at flexrm-vfio-v10 branch of
https://github.com/Broadcom/arm64-linux.git
Changes since v9:
- Make GPL comment header similar to other Broadcom drivers
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return cloc
> -Original Message-
> From: Andrew Lunn [mailto:and...@lunn.ch]
> Sent: Monday, October 02, 2017 18:37
> To: Razvan Stefanescu
> Cc: gre...@linuxfoundation.org; de...@driverdev.osuosl.org; linux-
> ker...@vger.kernel.org; net...@vger.kernel.org; ag...@suse.de;
> a...@arndb.de; Alexandru
This patchset does few more improvements to Broadcom FlexRM mailbox
driver.
The patches are based on Linux-4.14-rc3 and can also be found at
flexrm-imp2-v1 branch of:
https://github.com/Broadcom/arm64-linux.git
Anup Patel (4):
mailbox: bcm-flexrm-mailbox: Fix FlexRM ring flush sequence
mailbo
As-per suggestion from FlexRM HW folks, we have to first set
FlexRM ring flush state and then clear it for FlexRM ring flush
to work properly.
Currently, the FlexRM driver has incomplete FlexRM ring flush
sequence which causes repeated insmod+rmmod of mailbox client
drivers to fail.
This patch fi
As-per documentation in driver/dma/dmaengine.h, the
dma_cookie_complete() API should be called with lock
held.
This patch ensures that Broadcom SBA RAID driver calls
the dma_cookie_complete() API with reqs_lock held.
Signed-off-by: Anup Patel
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
---
This patchset does few more improvements to Broadcom SBA RAID
driver.
The patches are based on Linux-4.14-rc3 and can also be found
at sba-raid-imp2-v1 branch of:
https://github.com/Broadcom/arm64-linux.git
Anup Patel (4):
dmaengine: bcm-sba-raid: serialize dma_cookie_complete() using
reqs_
This patch makes the comment header of Broadcom SBA RAID driver
similar to the GPL comment header used across Broadcom driver
sources.
Signed-off-by: Anup Patel
---
drivers/dma/bcm-sba-raid.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/bcm-sba-raid
Each mailbox channel used by Broadcom SBA RAID driver is
a separate HW ring.
Currently, Broadcom SBA RAID driver creates one DMA channel
using one or more mailbox channels. When we are using more
than one mailbox channels for a DMA channel, the sba_request
are distributed evenly among multiple mai
By default, we build Broadcom SBA RAID driver as loadable module for
iProc SOCs so that kernel image is little smaller and we load SBA RAID
driver only when required.
Signed-off-by: Anup Patel
Reviewed-by: Scott Branden
---
drivers/dma/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
This patch updates all dev_err() and dev_warn() to print
ring number so that we have more info for debugging.
Signed-off-by: Anup Patel
Reviewed-by: Scott Branden
---
drivers/mailbox/bcm-flexrm-mailbox.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --g
Fix the reversed goto labels, so that we disable cqspi controller only
if its enabled previously. This is a minor cleanup.
Signed-off-by: Vignesh R
---
drivers/mtd/spi-nor/cadence-quadspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadsp
From: Scott Branden
The Broadcom FlexRM Mailbox is only present in the Broadcom IPROC SoCs.
Add depends on ARCH_BCM_IPROC to BCM_FLEXRX_MBOX.
Signed-off-by: Scott Branden
Reviewed-by: Ray Jui
---
drivers/mailbox/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/Kconf
By default, we build Broadcom FlexRM driver as loadable module for
iProc SOCs so that kernel image is little smaller and we load FlexRM
driver only when required.
Signed-off-by: Anup Patel
Reviewed-by: Scott Branden
---
drivers/mailbox/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
This patch makes the comment header of Broadcom FlexRM driver
similar to the GPL comment header used across Broadcom driver
sources.
Signed-off-by: Anup Patel
---
drivers/mailbox/bcm-flexrm-mailbox.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/
Add pm_runtime* calls to cadence-quadspi driver. This is required to
switch on QSPI power domain on TI 66AK2G SoC during probe.
Signed-off-by: Vignesh R
---
v4: Disable pm in error path.
drivers/mtd/spi-nor/cadence-quadspi.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this an
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return cloc
Update binding documentation to add a new compatible for TI 66AK2G SoC,
to handle TI SoC specific quirks in the driver.
Signed-off-by: Vignesh R
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --g
This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
The patches enhance the existing cadence-quadspi driver to support
loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.
Change log:
v4:
* New patch to fix error handling sequence in probe.
v3:
* Fix build
On Mon, 2017-10-02 at 21:11 -0700, John Johansen wrote:
> On 10/02/2017 09:02 PM, James Bottomley wrote:
> >
> > The specific problem is that dnsmasq refuses to start on openSUSE
> > Leap 42.2. The specific cause is that and attempt to open a
> > PF_LOCAL socket gets EACCES. This means that netw
Hi Rohit,
On Thu, Sep 28, 2017 at 8:09 AM, Rohit Jain wrote:
[..]
>>>
>>> With this case, because we know from the past avg, one of the strands is
>>> running low on capacity, I am trying to return a better strand for the
>>> thread to start on.
>>>
>> I know what you're trying to do but they way
On 10/02/2017 09:02 PM, James Bottomley wrote:
> The specific problem is that dnsmasq refuses to start on openSUSE Leap
> 42.2. The specific cause is that and attempt to open a PF_LOCAL socket
> gets EACCES. This means that networking doesn't function on a system
> with a 4.14-rc2 system.
>
> Re
The specific problem is that dnsmasq refuses to start on openSUSE Leap
42.2. The specific cause is that and attempt to open a PF_LOCAL socket
gets EACCES. This means that networking doesn't function on a system
with a 4.14-rc2 system.
Reverting commit 651e28c5537abb39076d3949fb7618536f1d242e (ap
From: Frank Rowand
Follows recommendations in Documentation/process/coding-style.rst,
section 8, Commenting.
Some in function comments are promoted to function header comments.
Signed-off-by: Frank Rowand
---
drivers/of/overlay.c | 53
1 fi
From: Frank Rowand
This patch is aimed primarily at drivers/of/overlay.c, but those
changes also have a small impact in a few other files.
overlay.c is difficult to read and maintain. Improve readability:
- Rename functions, types and variables to better reflect what
they do and to be con
From: Frank Rowand
I have found the device tree overlay code to be difficult to read and
maintain. This patch series attempts to improve that situation.
The cleanup includes some changes visible to users of overlays. The
only in kernel user of overlays is fixed up for those changes. The
in ke
From: Frank Rowand
More renaming of identifiers to better reflect what they do.
Signed-off-by: Frank Rowand
---
drivers/of/overlay.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
index 397ef10d1f26..c35
From: Frank Rowand
The test of whether it is safe to remove an overlay changeset
looked at whether any node in the overlay changeset was in a
subtree rooted at any more recently applied overlay changeset
node.
The test failed to determine whether any node in the overlay
changeset was the root of
From: Frank Rowand
When an attempt to apply an overlay changeset fails, an effort
is made to revert any partial application of the changeset.
When an attempt to remove an overlay changeset fails, an effort
is made to re-apply any partial reversion of the changeset.
The existing code does not che
From: Frank Rowand
When an overlay contains a node that already exists in
the live device tree, the overlay node is not allowed
to change the phandle of the existing node.
The existing check refused to allow an overlay node to
set the node phandle even when the existing node did
not have a phand
From: Frank Rowand
Use normal shorthand for comparing a variable to zero.
For variable "XXX":
convert (XXX == 0) to (!XXX)
convert (XXX != 0) to (XXX)
Signed-off-by: Frank Rowand
---
drivers/of/overlay.c | 36 ++--
1 file changed, 18 insertions(+), 18 dele
From: Frank Rowand
The "%pOF" printf format was recently added to print the
full name of a device tree node, with the intent of changing
the node full_name field to contain only the node name instead
of the full path of the node.
dup_and_fixup_symbol_prop() duplicates a property from the
"/__sym
From: Frank Rowand
The code to apply symbols from an overlay to the live device tree
was implemented with the intent to be minimally intrusive on the
existing code. After recent restructuring of the overlay apply
code, it is easier to disintangle the code that applies the
symbols, and to make th
From: Frank Rowand
Continue improving the readability of overlay.c. The previous patches
renamed identifiers. This patch is split out from the previous patches
to make the previous patches easier to review.
Changes are:
- minor code restructuring
- some initialization of an overlay changes
From: Frank Rowand
The process of applying an overlay consists of:
- unflatten an overlay FDT (flattened device tree) into an
EDT (expanded device tree)
- fixup the phandle values in the overlay EDT to fit in a
range above the phandle values in the live device tree
- create the over
From: Frank Rowand
kbasename() will not return NULL if passed a valid string. If
the parameter passed to kbasename() in this case is already NULL
then the devicetree has been corrupted.
Signed-off-by: Frank Rowand
---
drivers/of/overlay.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/d
Hi Josh,
On Mon, Oct 02, 2017 at 04:31:09PM -0500, Josh Poimboeuf wrote:
On Mon, Oct 02, 2017 at 04:26:54PM -0500, Josh Poimboeuf wrote:
Fengguang, assuming it's reliably recreatable, any chance you could
recreate with the following patch?
Sure, I'll try your patch on v4.14-rc3 since it looks
Andrew Morton writes:
> On Fri, 29 Sep 2017 14:30:58 +0200 Jürg Billeter wrote:
>
>> PR_SET_PDEATHSIG sets a parent death signal that the calling process
>> will get when its parent thread dies, even when the result of getppid()
>> doesn't change because the calling process is reparented to a di
On Fri, Sep 08, 2017 at 01:59:00PM -0700, h...@zytor.com wrote:
> On September 8, 2017 2:45:10 AM PDT, Gary Lin wrote:
> >On Thu, Sep 07, 2017 at 02:16:21PM -0700, h...@zytor.com wrote:
> >> On September 7, 2017 2:44:51 AM PDT, Gary Lin wrote:
> >> >On Thu, Jun 01, 2017 at 08:46:26AM +, Ard B
On Tue, Oct 03, 2017 at 03:07:24AM +0100, Al Viro wrote:
> On Tue, Oct 03, 2017 at 02:50:42AM +0200, Adam Borowski wrote:
> > Anything with bytes 1-31,127 will get -EACCES.
> >
> > Especially \n is bad: instead of natural file-per-line, you need an
> > user-unfriendly feature of -print0 added to e
On Tue, Oct 03, 2017 at 10:38:25AM +0800, Jia-Ju Bai wrote:
> According to fs/dcache.c, might_sleep is called under a spinlock,
> and the function call path is:
> d_prune_aliases (acquire the spinlock)
> dput
> might_sleep
>
> This bug is found by my static analysis tool and my code review.
From: Christoffer Dall
Now that the vttbr value will be different depending on the VM's
exception level, we set it on each VM entry.
We only have one mmu instance at this point, but there will be
multiple of them if we come to run nested VMs.
Signed-off-by: Christoffer Dall
Signed-off-by: Jint
From: Christoffer Dall
Make mmu functions non-static so that we can reuse those functions
to support mmu for the nested VMs.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_mmu.h | 9
virt/kvm/arm/mmu.c | 94 +++
From: Christoffer Dall
Abstract stage-2 MMU state into a separate structure and change all
callers referring to page tables, VMIDs, and the VTTBR to use this new
indirection.
This is about to become very handy when using shadow stage-2 page
tables.
Signed-off-by: Christoffer Dall
Signed-off-by
From: Christoffer Dall
Sometimes when we are invalidating the TLB for a certain S2 MMU
context, this context can also have EL2 context associated with it and
we have to invalidate this too.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
virt/kvm/arm/arm.c | 5 +
virt/kvm/
From: Christoffer Dall
If we are faulting on a shadow stage 2 translation, we first walk the
guest hypervisor's stage 2 page table to see if it has a mapping. If
not, we inject a stage 2 page fault to the virtual EL2. Otherwise, we
create a mapping in the shadow stage 2 page table.
Note that we
From: Christoffer Dall
Move this little function to the header files for arm/arm64 so other
code can make use of it directly.
Signed-off-by: Christoffer Dall
---
arch/arm/include/asm/kvm_emulate.h | 8
arch/arm64/include/asm/kvm_emulate.h | 8
virt/kvm/arm/mmu.c
From: Christoffer Dall
Based on the pseudo-code in the ARM ARM, implement a stage 2 software
page table walker.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
Notes:
v1-->v2:
- Handled different endianness between the host and the guest hypervisor
- Decoupled the s
From: Christoffer Dall
We can have discrepancies between the nested stage 2 page table and the
shadow one in a couple of cases. For example, the guest hypervisor can
mark a page writable but the host hypervisor maps the page read-only in
the shadow page table, if using something like KSM on the
From: Christoffer Dall
Unmap/flush shadow stage 2 page tables for the nested VMs as well as the
stage 2 page table for the guest hypervisor.
Note: A bunch of the code in mmu.c relating to MMU notifiers is
currently dealt with in an extremely abrupt way, for example by clearing
out an entire shad
From: Jintack Lim
We are about to add a framework to handle system instruction traps. To
reuse existing helper functions, let's move them around.
No functional change.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 89 ---
1 file changed
This introduces a function prototype to determine if we need to forward
system instruction traps to the virtual EL2. The implementation of
forward_trap functions for each system instruction will be added in
later patches.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 8
arc
Emulate AT S1E[01] instructions by issuing the same instructions in EL2. We
set the physical EL1 registers, NV and NV1 bits as described in the AT
instruction emulation overview.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/kvm_emulate.h | 11 +++
arch/arm64/kvm/sys_regs.c
TLBI ALLE1(IS) instruction invalidates all EL1&0 regime stage 1 and 2
TLB entries (on all PEs in the same Inner Shareable domain). To emulate
these instructions, we first need to clear all the mappings in the
shadow page tables since executing those instructions implies the change
of mappings in th
Implement AT instruction handling logic in EL2. This will be used to
emulate AT instructions executed in the virtual EL2.
AT instruction emulation works by loading the proper processor context,
which depends on the trapped instruction and the virtual HCR_EL2, to the
EL1 virtual memory control regi
Emulate TLBI VAE2* instruction executed in the virtual EL2. Based on the
same principle as TLBI ALLE2 instruction, we can simply emulate those
instructions by executing corresponding VAE1* instructions with the
virtual EL2's VMID assigned by the host hypervisor.
Signed-off-by: Jintack Lim
---
ar
Emulate TLBI ALLE2(IS) instruction executed in the virtual EL2. Since we
emulate the virtual EL2 in the EL1, we invalidate EL1&0 regime stage 1
TLB entries with setting vttbr_el2 having the VMID of the virtual EL2.
Note that we are able to emulate TLBI ALLE2IS precisely by only
invalidating stage
Based on the same principle as TLBI ALLE1(IS) and TLBI VMALLS12E1(IS)
emulation, we clear the mappings in the shadow stage-2 page tables and
invalidate TLB entries. We do it only for one mapping for the current
VMID from the guest hypervisor's view.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/
Emulate AT S1E2 instructions by issuing the corresponding S1E1
instructions in EL2. We set the physical EL1 registers and the HCR_EL2
register as described in the AT instruction emulation overview.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 19 +--
1 file changed,
Emulating AT A12E[01] instructions involves two steps. First, do the
stage-1 translation by reusing the existing AT emulation functions. Then
do the stage-2 translation by walking the guest hypervisor's stage-2
page table in software. Record the translation result to PAR_EL1.
Signed-off-by: Jintac
Forward system instruction traps to the virtual EL2 if a corresponding
bit in the virtual HCR_EL2 is set.
Signed-off-by: Jintack Lim
---
Notes:
v1-->v2:
This is a new commit. We can rework existing forward_nv_traps() and
forward_nv1_traps() defined in rfc-v2 cpu patches to reuse for
Based on the same principle as TLBI ALLE1(IS) emulation, we clear the
mappings in the shadow stage-2 page tables and invalidate TLB entries.
But this time we do it only for the current VMID from the guest
hypervisor's perspective, not for all VMIDs.
Signed-off-by: Jintack Lim
---
arch/arm64/incl
This design overview will help to digest the subsequent patches that
implement AT instruction emulation.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c | 66 +++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/
Even though a guest hypervisor can execute TLBI instructions that are
accesible at EL1 without trap, it's wrong; All those TLBI instructions
work based on current VMID, and when running a guest hypervisor current
VMID is the one for itself, not the one from the virtual vttbr_el2. So
letting a guest
List all system instructions to emulate. This patch only introduces the
definitions, emulation handlers will be added in subsequent patches.
Signed-off-by: Jintack Lim
---
arch/arm64/include/asm/sysreg.h | 38 ++
arch/arm64/kvm/sys_regs.c | 26 ++
Rework the system instruction emulation framework to handle potentially
all system instruction traps other than MSR/MRS instructions. Those
system instructions would be AT and TLBI instructions controlled by
HCR_EL2.NV, AT, and TTLB bits.
Signed-off-by: Jintack Lim
---
arch/arm64/kvm/sys_regs.c
From: Christoffer Dall
So far we were flushing almost the entire universe whenever a VM would
load/unload the SCTLR_EL1 and the two versions of that register had
different MMU enabled settings. This turned out to be so slow that it
prevented forward progress for a nested VM, because a scheduler
Now that a hypervisor can run in the virtual EL2, the guest hypervisor
can assign any VMID to its own VMs. To avoid conflicts between VMIDs
among a host and guest(s), the host hypervisor maps each VMID from a
guest hypervisor's view (i.e. virtual VMID) to an unique shadow VMID.
It also manages a se
From: Christoffer Dall
When running a guest hypervisor in virtual EL2, the translation context
has to be separate from the rest of the system, including the guest
EL1/0 translation regime, so we allocate a separate VMID for this mode.
Considering that we have two different vttbr values due to se
From: Christoffer Dall
stage2_flush_xxx functions take a pointer to the kvm struct as the first
parameter but they are never used. Clean this up before modifying mmu
code for nested virtualization support.
Signed-off-by: Christoffer Dall
Signed-off-by: Jintack Lim
---
virt/kvm/arm/mmu.c | 15
The Fintek F81866/F81216H support high baud rate and it's up to 1.5Mbps
with 24MHz clock source. It's also support 500Kbps via 24MHz clock too.
We'll implements clock source checking in function fintek_8250_set_termios().
Ji-Ze Hong (Peter Hong) (3):
serial: 8250_fintek: UART dynamic clocksourc
The F81866 had 4 clocksource 1.8432/18.432/14.769/24MHz and baud rates can
be up to 1.5Mbits with 24MHz. We'll implements the dynamic clocksource in
fintek_8250_set_termios().
Signed-off-by: Ji-Ze Hong (Peter Hong)
---
drivers/tty/serial/8250/8250_fintek.c | 54 ++
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