Adding check on failed attempt to parse the address
and skip the line parsing early in that case.
Link: http://lkml.kernel.org/n/tip-djqwni3p6lgctf6o7xhhw...@git.kernel.org
Signed-off-by: Jiri Olsa
---
tools/lib/symbol/kallsyms.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/lib/
On 02/02/2018 10:22 AM, Laurent Dufour wrote:
On 01/02/2018 00:04, daniel.m.jor...@oracle.com wrote:
...snip...
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 99a54df760e3..6911626f29b2 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -2077,6 +2077,7 @@ static void lock_page_lru(stru
On 02/06/2018 07:51 AM, Sekhar Nori wrote:
On Tuesday 06 February 2018 06:38 PM, Bartosz Golaszewski wrote:
2018-02-06 12:07 GMT+01:00 Sekhar Nori :
On Monday 05 February 2018 09:22 PM, Bartosz Golaszewski wrote:
From: Bartosz Golaszewski
Make nand work with the common clock framework by spe
Hi Patrick,
Il 06/02/2018 16:43, Patrick Bellasi ha scritto:
Hi Claudio,
On 06-Feb 11:55, Claudio Scordino wrote:
Hi Peter,
Il 20/12/2017 16:30, Peter Zijlstra ha scritto:
So I ended up with the below (on top of Juri's cpufreq-dl patches).
It compiles, but that's about all the testing it h
Christoffer Dall writes:
> On Wed, Jan 10, 2018 at 07:07:27PM +, Punit Agrawal wrote:
>> In preparation for creating PUD hugepages at stage 2, add support for
>> write protecting PUD hugepages when they are encountered. Write
>> protecting guest tables is used to track dirty pages when migrat
> -Original Message-
> From: Tobin C. Harding [mailto:m...@tobin.cc]
> Sent: Monday, February 5, 2018 2:23 PM
> To: Adam Borowski
> Cc: Kees Cook ; Petr Mladek ;
> Sergey Senozhatsky ; Steven Rostedt
> ; LKML ; Andrew Morton
> ; Joe Perches ; Roberts,
> William C ; Linus Torvalds founda
Christoffer Dall writes:
> On Wed, Jan 10, 2018 at 07:07:29PM +, Punit Agrawal wrote:
>> KVM only supports PMD hugepages at stage 2. Extend the stage 2 fault
>> handling to add support for PUD hugepages.
>>
>> Addition of PUD hugpage support enables additional hugepage sizes (1G
>
>
Andrew and Florian, thanks for your input.
On Tue, Feb 6, 2018 at 12:05 PM, Andrew Lunn wrote:
> I would NACK sysfs bin file. Do it right, or don't do it at all.
On Tue, Feb 6, 2018 at 12:47 PM, Florian Fainelli wrote:
> Sven, there is a standard ethtool register dump interface that can be
> us
On 02/04/2018 05:58 PM, Ulf Magnusson wrote:
> On Mon, Feb 5, 2018 at 2:21 AM, Ulf Magnusson wrote:
>> The MIPS_SEAD3 symbol was removed in commit 64601cb1343f ("leds: Remove
>> SEAD-3
>> driver").
>>
>> Remove the MIPS_SEAD3 dependency from IMG_ASCII_LCD.
>>
>> Discovered with the
>> https://git
>From : Archana Sathyakumar
The Power Domain Controller (PDC) on QTI SoCs like SDM845 houses an
interrupt controller along with other domain control functions to handle
interrupt related functions like handle falling edge or active low which
are not detected at the GIC and handle wakeup interrupt
From: Archana Sathyakumar
Add device binding documentation for the PDC Interrupt controller on
QCOM SoC's like the SDM845. The interrupt-controller can be used to
sense edge low interrupts and wakeup interrupts when the GIC is
non-operational.
Cc: devicet...@vger.kernel.org
Signed-off-by: Archan
Changes since RFC v2:
- Fixed up DT probe based on suggestions from Thomas and Marc
- Code clean up as suggested by Thomas
- Switch to SPDX license marker
- Dropped the FTRACE patch for now, will need more thought and discussions
On newer Qualcomm Techonologies Inc's SoCs like the SDM845, the GIC
From: Rafael J. Wysocki
Update the APM driver overlooked by commit 1b39e3f813b4 (cpuidle: Make
drivers initialize polling state) to initialize the polling state like
the other cpuidle drivers modified by that commit to prevent cpuidle
from crashing.
Fixes: 1b39e3f813b4 (cpuidle: Make drivers ini
2018-02-06 13:25 GMT+01:00 Alexey Brodkin :
> Hi Bartosz,
>
> On Tue, 2018-02-06 at 12:08 +0100, Bartosz Golaszewski wrote:
>> Using compatible strings without the part for at24 is
>> deprecated since commit 6da28acf745f ("dt-bindings: at24: consistently
>> document the compatible property"). Use
On Tue, Feb 6, 2018 at 6:58 PM, syzbot
wrote:
> Hello,
>
> syzbot hit the following crash on net-next commit
> 617aebe6a97efa539cc4b8a52adccd89596e6be0 (Sun Feb 4 00:25:42 2018 +)
> Merge tag 'usercopy-v4.16-rc1' of
> git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux
>
> So far this cra
On Tuesday, February 6, 2018 5:31:34 PM CET Ville Syrjälä wrote:
> On Mon, Feb 05, 2018 at 06:56:31PM +0100, Rafael J. Wysocki wrote:
> > On Monday, February 5, 2018 3:04:45 PM CET Ville Syrjälä wrote:
> > > On Sun, Feb 04, 2018 at 10:18:07AM +0100, Rafael J. Wysocki wrote:
> > > > On Sun, Feb 4, 2
As we're about to trigger a PSCI version explosion, it doesn't
hurt to introduce a PSCI_VERSION helper that is going to be
used everywhere.
Reviewed-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
---
include/kvm/arm_psci.h| 6 --
include/uapi/linux/psci.h |
On 06/02/2018 18:29, David Woodhouse wrote:
> I've put together a linux-4.9.y branch at
> http://git.infradead.org/retpoline-stable.git/shortlog/refs/heads/linux-4.9.y
>
> Most of it is fairly straightforward, apart from the IBPB on context
> switch for which Tim has already posted a candidate.
Instead of open coding the accesses to the various registers,
let's add explicit SMCCC accessors.
Reviewed-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
---
virt/kvm/arm/psci.c | 52 ++--
1 file changed, 42 insertions
The new SMC Calling Convention (v1.1) allows for a reduced overhead
when calling into the firmware, and provides a new feature discovery
mechanism.
Make it visible to KVM guests.
Tested-by: Ard Biesheuvel
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
arch/arm/kvm/handle_exit.c
One of the major improvement of SMCCC v1.1 is that it only clobbers
the first 4 registers, both on 32 and 64bit. This means that it
becomes very easy to provide an inline version of the SMC call
primitive, and avoid performing a function call to stash the
registers that would otherwise be clobbered
Add the detection and runtime code for ARM_SMCCC_ARCH_WORKAROUND_1.
It is lovely. Really.
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/bpi.S| 20 +
arch/arm64/kernel/cpu_errata.c | 68 +-
2 files changed,
Now that we've standardised on SMCCC v1.1 to perform the branch
prediction invalidation, let's drop the previous band-aid.
If vendors haven't updated their firmware to do SMCCC 1.1, they
haven't updated PSCI either, so we don't loose anything.
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
With the exception of handling 'empty' buffers, I ended up with the
below. Please try again.
There are two small errors. After fixing them, the patch works well.
---
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1156,16 +1156,13 @@ int x86_perf_event_set_period(struct per
We want SMCCC_ARCH_WORKAROUND_1 to be fast. As fast as possible.
So let's intercept it as early as we can by testing for the
function call number as soon as we've identified a HVC call
coming from the guest.
Tested-by: Ard Biesheuvel
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
A new feature of SMCCC 1.1 is that it offers firmware-based CPU
workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides
BP hardening for CVE-2017-5715.
If the host has some mitigation for this issue, report that
we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the
host workaround on
Function identifiers are a 32bit, unsigned quantity. But we never
tell so to the compiler, resulting in the following:
4ac: b26187e0mov x0, #0x8001
We thus rely on the firmware narrowing it for us, which is not
always a reasonable expectation.
Cc: sta...@vger.kernel.or
PSCI 1.0 can be trivially implemented by providing the FEATURES
call on top of PSCI 0.2 and returning 1.0 as the PSCI version.
We happily ignore everything else, as they are either optional or
are clarifications that do not require any additional change.
PSCI 1.0 is now the default until we decid
In order to call into the firmware to apply workarounds, it is
useful to find out whether we're using HVC or SMC. Let's expose
this through the psci_ops.
Acked-by: Lorenzo Pieralisi
Reviewed-by: Robin Murphy
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
---
drivers/firmware/psci.c | 2
We're about to need kvm_psci_version in HYP too. So let's turn it
into a static inline, and pass the kvm structure as a second
parameter (so that HYP can do a kern_hyp_va on it).
Tested-by: Ard Biesheuvel
Reviewed-by: Christoffer Dall
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/switch.c
Since PSCI 1.0 allows the SMCCC version to be (indirectly) probed,
let's do that at boot time, and expose the version of the calling
convention as part of the psci_ops structure.
Acked-by: Lorenzo Pieralisi
Reviewed-by: Robin Murphy
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
---
dr
As we're about to update the PSCI support, and because I'm lazy,
let's move the PSCI include file to include/kvm so that both
ARM architectures can find it.
Acked-by: Christoffer Dall
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
---
arch/arm/include/asm/kvm_psci.h|
KVM doesn't follow the SMCCC when it comes to unimplemented calls,
and inject an UNDEF instead of returning an error. Since firmware
calls are now used for security mitigation, they are becoming more
common, and the undef is counter productive.
Instead, let's follow the SMCCC which states that -1
KVM doesn't follow the SMCCC when it comes to unimplemented calls,
and inject an UNDEF instead of returning an error. Since firmware
calls are now used for security mitigation, they are becoming more
common, and the undef is counter productive.
Instead, let's follow the SMCCC which states that -1
When handling an SMC trap, the "preferred return address" is set
to that of the SMC, and not the next PC (which is a departure from
the behaviour of an SMC that isn't trapped).
Increment PC in the handler, as the guest is otherwise forever
stuck...
Cc: sta...@vger.kernel.org
Fixes: acfb3b883f6d (
ARM has recently published a SMC Calling Convention (SMCCC)
specification update[1] that provides an optimised calling convention
and optional, discoverable support for mitigating CVE-2017-5715. ARM
Trusted Firmware (ATF) has already gained such an implementation[2].
This series addresses a few th
On Tue, Feb 6, 2018 at 7:45 PM, David Woodhouse wrote:
> The documentation for ignore_rlimit_data says that it will print a warning
> at first misuse. Yet it doesn't seem to do that. Fix the code to print
> the warning even when we allow the process to continue.
Ack. But I think this was a mispri
On 02/02/2018 12:00 PM, Laurent Dufour wrote:
On 02/02/2018 15:40, Laurent Dufour wrote:
On 01/02/2018 00:04, daniel.m.jor...@oracle.com wrote:
A common case in release_pages is for the 'pages' list to be in roughly
the same order as they are in their LRU. With LRU batch locking, when a
sent
On 02/06/2018 09:05 AM, Andrew Lunn wrote:
> On Tue, Feb 06, 2018 at 11:58:17AM -0500, Sven Van Asbroeck wrote:
>> On Tue, Feb 6, 2018 at 11:50 AM, Andrew Lunn wrote:
>>> And a DSA driver does not need to be complex. You can start simple,
>>> and add more features later.
>>
>> I see. Would it be p
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
Signed-off-by: Stefan Agner
---
.../devicetree/bindings/mtd/gpmi-nand.txt | 5
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 29 ++
2 files cha
The dt property fsl,use-minimum-ecc requires a NAND chip to
provide a ECC strength/step size, otherwise the driver fails
to probe. This is by design to avoid that the driver uses a
fallback and later changes ECC parameters due to additionion
of a NAND chip driver. Document the current behavior.
Si
On 02/02/2018 12:21 AM, Aaron Lu wrote:
On Wed, Jan 31, 2018 at 06:04:13PM -0500, daniel.m.jor...@oracle.com wrote:
Now that release_pages is scaling better with concurrent removals from
the LRU, the performance results (included below) showed increased
contention on lru_lock in the add-to-LRU p
On 02/05/2018 10:50 PM, Joel Fernandes wrote:
On Wed, Jan 31, 2018 at 9:50 AM, Rohit Jain wrote:
kernel/sched/fair.c | 38 --
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index 26a71eb..ce5
On Tue, Feb 6, 2018 at 6:31 PM, syzbot
wrote:
> Hello,
>
> syzbot hit the following crash on upstream commit
> e237f98a9c134c3d600353f21e07db915516875b (Mon Feb 5 21:35:56 2018 +)
> Merge tag 'xfs-4.16-merge-5' of
> git://git.kernel.org/pub/scm/fs/xfs/xfs-linux
>
> So far this crash happened 8
From: David Matlack
The host physical addresses of L1's Virtual APIC Page and Posted
Interrupt descriptor are loaded into the VMCS02. The CPU may write
to these pages via their host physical address while L2 is running,
bypassing address-translation-based dirty tracking (e.g. EPT write
protection
From: Ashok Raj
The Indirect Branch Predictor Barrier (IBPB) is an indirect branch
control mechanism. It keeps earlier branches from influencing
later ones.
Unlike IBRS and STIBP, IBPB does not define a new mode of operation.
It's a command that ensures predicted branch targets aren't used after
From: Paolo Bonzini
Group together the calls to alloc_vmcs and loaded_vmcs_init. Soon we'll also
allocate an MSR bitmap there.
Cc: sta...@vger.kernel.org # prereq for Spectre mitigation
Signed-off-by: Paolo Bonzini
(cherry picked from commit f21f165ef922c2146cc5bdc620f542953c41714b)
Sign
On 02/05/2018 10:42 PM, Joel Fernandes wrote:
On Tue, Jan 30, 2018 at 11:47 AM, Rohit Jain wrote:
[...]
@@ -6102,7 +6107,8 @@ static int select_idle_core(struct task_struct *p,
struct sched_domain *sd, int
*/
static int select_idle_smt(struct task_struct *p, struct sched_domain
*sd, in
From: Markus Elfring
Date: Tue, 6 Feb 2018 18:18:50 +0100
Return an error code without storing it in an intermediate variable.
Signed-off-by: Markus Elfring
---
drivers/hid/hid-asus.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/hid/hid-asus.c b/drivers/hid
From: David Hildenbrand
vmx_complete_nested_posted_interrupt() can't fail, let's turn it into
a void function.
Signed-off-by: David Hildenbrand
Signed-off-by: Paolo Bonzini
(cherry picked from commit 6342c50ad12e8ce0736e722184a7dbdea4a3477f)
Signed-off-by: David Woodhouse
---
arch/x86/kvm/v
From: KarimAllah Ahmed
Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO
(bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the
contents will come directly from the hardware, but user-space can still
override it.
[dwmw2: The bit in kvm_cpuid_7_0_edx_x86_featu
From: Paolo Bonzini
Place the MSR bitmap in struct loaded_vmcs, and update it in place
every time the x2apic or APICv state can change. This is rare and
the loop can handle 64 MSRs per iteration, in a similar fashion as
nested_vmx_prepare_msr_bitmap.
This prepares for choosing, on a per-VM basi
From: KarimAllah Ahmed
[ Based on a patch from Paolo Bonzini ]
... basically doing exactly what we do for VMX:
- Passthrough SPEC_CTRL to guests (if enabled in guest CPUID)
- Save and restore SPEC_CTRL around VMExit and VMEntry only if the guest
actually used it.
Signed-off-by: KarimAllah A
On Tue, 2018-02-06 at 20:27 +0300, Cyrill Gorcunov wrote:
> On Tue, Feb 06, 2018 at 04:45:05PM +, David Woodhouse wrote:
> >
> > The documentation for ignore_rlimit_data says that it will print a warning
> > at first misuse. Yet it doesn't seem to do that. Fix the code to print
> > the warni
From: Markus Elfring
Date: Tue, 6 Feb 2018 18:03:19 +0100
Omit an extra message for a memory allocation failure in these functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
drivers/hid/hid-asus.c | 5 +
1 file changed, 1 insertion(+), 4 d
From: KarimAllah Ahmed
[ Based on a patch from Ashok Raj ]
Add direct access to MSR_IA32_SPEC_CTRL for guests. This is needed for
guests that will only mitigate Spectre V2 through IBRS+IBPB and will not
be using a retpoline+IBPB based approach.
To avoid the overhead of saving and restoring the
From: Jim Mattson
The potential performance advantages of a vmcs02 pool have never been
realized. To simplify the code, eliminate the pool. Instead, a single
vmcs02 is allocated per VCPU when the VCPU enters VMX operation.
Cc: sta...@vger.kernel.org # prereq for Spectre mitigation
Signed-o
I've put together a linux-4.9.y branch at
http://git.infradead.org/retpoline-stable.git/shortlog/refs/heads/linux-4.9.y
Most of it is fairly straightforward, apart from the IBPB on context
switch for which Tim has already posted a candidate. I wanted some more
review on my backports of the KVM b
From: Markus Elfring
Date: Tue, 6 Feb 2018 18:24:56 +0100
Two update suggestions were taken into account
from static source code analysis.
Markus Elfring (2):
Delete an error message for a failed memory allocation in two functions
Return an error code only as a constant in asus_start_multito
On Tue, Feb 06, 2018 at 04:45:05PM +, David Woodhouse wrote:
> The documentation for ignore_rlimit_data says that it will print a warning
> at first misuse. Yet it doesn't seem to do that. Fix the code to print
> the warning even when we allow the process to continue.
>
> Signed-off-by: David
On Tue, Feb 06, 2018 at 05:05:52PM +, Mathieu Desnoyers wrote:
> - On Feb 6, 2018, at 9:11 AM, Will Deacon will.dea...@arm.com wrote:
>
> > On Tue, Feb 06, 2018 at 02:06:50PM +, Mathieu Desnoyers wrote:
> >> - On Feb 6, 2018, at 8:55 AM, Will Deacon will.dea...@arm.com wrote:
> >>
On 05/02/18 07:25 PM, Srivatsa S. Bhat wrote:
From: Srivatsa S. Bhat
register_blkdev() and __register_chrdev_region() treat the major
number as an unsigned int. So print it the same way to avoid
absurd error statements such as:
"... major requested (-1) is greater than the maximum (511) ..."
Thanks!
On 05/02/18 07:25 PM, Srivatsa S. Bhat wrote:
From: Srivatsa S. Bhat
CHRDEV_MAJOR_DYN_END and CHRDEV_MAJOR_DYN_EXT_END are valid major
numbers. So fix the loop iteration to include them in the search for
free major numbers.
While at it, also remove a redundant if condition ("cd->major
On 06.02.2018 17:48, Anand Moon wrote:
> Hi Kamil,
>
> Thanks for providing the fix to this issue.
>
> On 5 February 2018 at 23:10, Kamil Konieczny
> wrote:
>>
>> In AES-ECB mode crypt is done with key only, so any use of IV
>> can cause kernel Oops, as reported by Anand Moon.
>
> If possible
On Tue, Feb 06, 2018 at 11:34:24AM +0100, Petr Mladek wrote:
> User documentation for the atomic replace feature. It makes it easier
> to maintain livepatches using so-called cumulative patches.
Thanks for adding this doc. A few minor wording suggestions and typos
below...
>
> Signed-off-by: Pe
On Tue, Feb 6, 2018 at 12:26 PM, Sebastian Reichel
wrote:
> From: Peter Senna Tschudin
Looking at
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/277931.html
this patch seems to be originally from Martin Fuzzey.
In this case I would expect to see his name in the From field.
The VMA sequence count has been introduced to allow fast detection of
VMA modification when running a page fault handler without holding
the mmap_sem.
This patch provides protection against the VMA modification done in :
- madvise()
- mpol_rebind_policy()
- vma_replace_poli
> That's true, and who knows if python3 is running on ia64 :)
$ python3
-bash: python3: command not found
So I don't have it installed on my ia64 test/build machine.
-Tony
From: Kangmin Park
Signed-off-by: Kangmin Park
Sorry for sending duplicate.
A trivial path to fix a typo in kernel/cpu.c
Fix 'synchronsization' to 'synchronization'
---
kernel/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 53f7dc6.
If a thread is remapping an area while another one is faulting on the
destination area, the SPF handler may fetch the vma from the RB tree before
the pte has been moved by the other thread. This means that the moved ptes
will overwrite those create by the page fault handler leading to page
leaked.
The speculative page fault handler which is run without holding the
mmap_sem is calling lru_cache_add_active_or_unevictable() but the vm_flags
is not guaranteed to remain constant.
Introducing __lru_cache_add_active_or_unevictable() which has the vma flags
value parameter instead of the vma pointer
Ok, I submit it again.
In drivers/net/wan/hdlc_ppp.c, some noise on physical line can cause the
carrier detect still ok, but the protocol will fail. So if carrier detect ok,
don't turn off protocol negotiation
This patch is against the kernel version Linux 4.15-rc8
On Tuesday, February
From: Kan Liang
Improve the readability by using meaningful enum (-EAGAIN, -EINVAL and
0) to replace the three returning states (0, -1 and 1).
Suggested-by: Wang Nan
Signed-off-by: Kan Liang
Acked-by: Jiri Olsa
Cc: Andi Kleen
Cc: Jin Yao
Cc: Namhyung Kim
Cc: Peter Zijlstra
Cc: Wang Nan
L
From: William Cohen
Add JSON metrics for ARM Cortex-A53 Processor.
Unlike the Intel processors there isn't a script that automatically
generated these files. The patch was manually generated from the
documentation and the previous oprofile ARM Cortex ac53 event file patch
I made.
The relevant d
- On Feb 6, 2018, at 9:11 AM, Will Deacon will.dea...@arm.com wrote:
> On Tue, Feb 06, 2018 at 02:06:50PM +, Mathieu Desnoyers wrote:
>> - On Feb 6, 2018, at 8:55 AM, Will Deacon will.dea...@arm.com wrote:
>> > On Tue, Feb 06, 2018 at 12:52:34PM +, Mathieu Desnoyers wrote:
>> >> On
ository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
tags/perf-core-for-mingo-4.17-20180206
for you to fetch changes up to 52a37001d51a320c1019269fb3ba473a1363650d:
perf test: Fix test trace+probe_libc_inet_pton.sh for s390x (2018-02-06
10:4
From: Kan Liang
perf_evlist__mmap_read_catchup() and perf_evlist__mmap_read_backward()
are only for overwrite mode.
But they read the evlist->mmap buffer which is for non-overwrite mode.
It did not bring any serious problem yet, because there is no one use
it.
Remove the unused interfaces.
Si
From: Kan Liang
The 'start' and 'prev' variables are duplicates in perf_mmap__read().
Use 'map->prev' to replace 'start' in perf_mmap__read_*().
Suggested-by: Wang Nan
Signed-off-by: Kan Liang
Acked-by: Jiri Olsa
Cc: Andi Kleen
Cc: Jin Yao
Cc: Namhyung Kim
Cc: Peter Zijlstra
Cc: Wang Nan
From: Kan Liang
Use the new perf_mmap__read_* interfaces for overwrite ringbuffer test.
Commiter notes:
Testing:
[root@seventh ~]# perf test -v backward
48: Read backward ring buffer :
--- start ---
test child forked, pid 8309
Using CPUID GenuineIntel-6-9E
From: Kan Liang
Switch to non-overwrite mode if kernel doesnot support overwrite
ringbuffer.
It's only effect when overwrite mode is supported. No change to current
behavior.
Signed-off-by: Kan Liang
Acked-by: Jiri Olsa
Cc: Andi Kleen
Cc: Jin Yao
Cc: Namhyung Kim
Cc: Peter Zijlstra
Cc: W
From: Kan Liang
For overwrite mode, the ringbuffer will be paused. The event lost is
expected. It needs a way to notify the browser not print the warning.
It will be used later for perf top to disable lost event warning in
overwrite mode. There is no behavior change for now.
Signed-off-by: Kan
From: Kan Liang
There would be some records lost in overwrite mode because of pausing
the ringbuffer. It has little impact for the accuracy of the snapshot
and could be tolerated by 'perf top'.
Remove the lost events checking.
Signed-off-by: Kan Liang
Acked-by: Jiri Olsa
Cc: Andi Kleen
Cc: J
From: Kan Liang
The latency of perf_top__mmap_read() should be lower than refresh time.
If not, give some hints to reduce the latency.
Signed-off-by: Kan Liang
Acked-by: Jiri Olsa
Cc: Andi Kleen
Cc: Jin Yao
Cc: Namhyung Kim
Cc: Peter Zijlstra
Cc: Wang Nan
Link:
http://lkml.kernel.org/r/1
From: Sangwon Hong
Add the --force option to the man page.
Signed-off-by: Sangwon Hong
Cc: Jiri Olsa
Cc: Namhyung Kim
Cc: Taeung Song
Link:
http://lkml.kernel.org/r/1517831315-31490-1-git-send-email-qpa...@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo
---
tools/perf/Documentation/perf
Cast p to dma_addr_t in order to avoid a potential integer overflow.
This variable is being used in a context that expects an expression
of type dma_addr_t (u64).
The expression p << PAGE_SHIFT is currently being evaluated
using 32-bit arithmetic.
Addresses-Coverity-ID: 1458347 ("Unintentional in
From: Thomas Richter
On Intel test case trace+probe_libc_inet_pton.sh succeeds and the
output is:
[root@f27 perf]# ./perf trace --no-syscalls
-e probe_libc:inet_pton/max-stack=3/ ping -6 -c 1 ::1
PING ::1(::1) 56 data bytes
64 bytes from ::1: icmp_seq=1 ttl=64 time=0.037 ms
-
Quoting Hans Verkuil :
On 02/05/18 22:54, Gustavo A. R. Silva wrote:
Hi Hans,
Quoting Hans Verkuil :
On 02/05/2018 09:36 PM, Gustavo A. R. Silva wrote:
Add suffix ULL to constant 10 in order to give the compiler complete
information about the proper arithmetic to use. Notice that this
cons
On Tue, Feb 06, 2018 at 06:32:43AM -0800, Guenter Roeck wrote:
> On 02/05/2018 10:22 AM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.15.2 release.
> > There are 60 patches in this series, all will be posted as a response
> > to this one. If anyone has any i
On Tue, Feb 06, 2018 at 06:29:16AM -0800, Guenter Roeck wrote:
> On 02/05/2018 10:23 AM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 3.18.94 release.
> > There are 36 patches in this series, all will be posted as a response
> > to this one. If anyone has any
Ensure we gather architecture requirements about each architecture supporting
the "sync_core" membarrier command in a single file under
Documentation/features.
[ This patch applies on top of tip sched/core. ]
Signed-off-by: Mathieu Desnoyers
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: Peter Zijls
For some architectures (like arm), there are architecture-
defined events. Sometimes these events may be "recommended"
according to the architecture standard, in that the
implementer is free ignore the "recommendation" and create
its custom event.
This patch adds support for parsing standard event
The arm64 pmu-events folder structure has become
disorganised, since now we have core and also vendor
folders at the same level folder.
Since jevents now supports vendor subdirectory, relocate
the Cortex-A53 JSONs to arm vendor subdirectory.
Signed-off-by: John Garry
---
.../arch/arm64/arm/cort
This patchset adds support for some perf events features,
targeted at ARM64, implemented in a generic fashion.
The two main features are as follows:
- support for arch/vendor/platform pmu events directory structure
- support for parsing standard architecture pmu events
On the back of these, the C
This patch fixes the Cavium ThunderX2 JSON to use event definitions
from the ARMv8 recommended events.
The brief description is kept for readability for arch standard events,
but is not strictly required.
Signed-off-by: John Garry
---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 60
Since jevents now supports vendor subdirectory, relocate
the ThunderX2 JSON to Cavium subdirectory.
Signed-off-by: John Garry
---
.../arch/arm64/cavium/thunderx2-imp-def.json | 62 --
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 62 ++
tools/
This patch adds the HiSilicon hip08 JSON file. This platform
follows the ARMv8 recommended IMPLEMENTATION DEFINED events,
where applicable.
The brief description is kept for readability for arch defined
events, but is not strictly required.
Signed-off-by: John Garry
---
.../arch/arm64/hisilicon
On 2018-01-17 17:24:47 [-0500], David Miller wrote:
> From: Eric Dumazet
> Date: Wed, 17 Jan 2018 14:02:43 -0800
> > There is also the netif_rx_ni() stuff.
> >
> > Can't remember right now why it is not using
> > local_bh_{diable,enable}() pair instead
> > of preempt_disable() ... if (local_softi
On Mon, Feb 5, 2018 at 4:57 PM, Wanpeng Li wrote:
> This is effective one, what I restore in this patch is
> achitectural/guest visible.
This patch doesn't "restore" the guest visible CR4 to its value at the
time of VMLAUNCH/VMRESUME. It loads a new CR4 value from the vmcs12.
That behavior is in
- On Feb 6, 2018, at 11:51 AM, efficios effic...@ubuntu.efficios.com wrote:
> Ensure we gather architecture requirements about each architecture supporting
> the "sync_core" membarrier command in a single file under
> Documentation/features.
>
> [ This patch applies on top of tip sched/core.
On Tue, Feb 6, 2018 at 11:50 AM, Andrew Lunn wrote:
> And a DSA driver does not need to be complex. You can start simple,
> and add more features later.
I see. Would it be possible/practical to start with just phy_read/write,
port_enable/disable in dsa_switch_ops ? And just add a sysfs bin file
f
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