From: Suzuki K Poulose
Prepare the etb10 driver to return errors in enabling
the device.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-etb10.c | 18 +-
1 file changed, 13 insertions(+), 5
From: Suzuki K Poulose
Prepare to handle errors in enabling the hardware and
report it back to the core driver.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etf.c | 73 +++--
1 file
From: zhong jiang
of_node_put and put_device has taken the null pointer check into account.
So it is safe to remove the duplicated check.
Signed-off-by: zhong jiang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 9 +++--
1 file changed, 3 insertions(+), 6
From: zhong jiang
of_node_put and put_device has taken the null pointer check into account.
So it is safe to remove the duplicated check.
Signed-off-by: zhong jiang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 9 +++--
1 file changed, 3 insertions(+), 6
From: Suzuki K Poulose
Use CLAIM protocol to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
.../coresight/coresight-dynamic-replicator.c | 23 +-
1 file changed, 18 insertions(+), 5
From: Suzuki K Poulose
Use the CLAIM protocol to grab the ownership of the component when
in use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-catu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Suzuki K Poulose
We hold the read lock on CPU hotplug to simply copy the
online mask, which is not really needed. And this can
cause a lockdep warning, like :
[ 54.632093] ==
[ 54.638207] WARNING: possible circular locking dependency
From: Suzuki K Poulose
Coresight architecture defines CLAIM tags for a device to negotiate
control of the components (external agent vs self-hosted). Each device
has a pair of registers (CLAIMSET & CLAIMCLR) for managing the CLAIM
tags. However, the protocol for the CLAIM tags is IMPLEMENTATION
From: Suzuki K Poulose
Use CLAIM protocol to make sure the device is available for use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
.../coresight/coresight-dynamic-replicator.c | 23 +-
1 file changed, 18 insertions(+), 5
From: Suzuki K Poulose
Use the CLAIM protocol to grab the ownership of the component when
in use.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-catu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Suzuki K Poulose
We hold the read lock on CPU hotplug to simply copy the
online mask, which is not really needed. And this can
cause a lockdep warning, like :
[ 54.632093] ==
[ 54.638207] WARNING: possible circular locking dependency
From: Suzuki K Poulose
Coresight architecture defines CLAIM tags for a device to negotiate
control of the components (external agent vs self-hosted). Each device
has a pair of registers (CLAIMSET & CLAIMCLR) for managing the CLAIM
tags. However, the protocol for the CLAIM tags is IMPLEMENTATION
From: Suzuki K Poulose
Add a helper to check if the given endpoint is input.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
From: Suzuki K Poulose
If the ETB is already enabled in sysfs mode, the ETB reports
success even if a perf mode is requested. Fix this by checking
the requested mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
From: Suzuki K Poulose
When parsing the remote endpoint of an output port, we do :
rport = of_graph_get_remote_port(ep);
rparent = of_graph_get_remote_port_parent(ep);
and then parse the "remote_port" as if it was the remote endpoint,
which is wrong. The code worked fine because we
From: Suzuki K Poulose
If the ETB is already enabled in sysfs mode, the ETB reports
success even if a perf mode is requested. Fix this by checking
the requested mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
From: Suzuki K Poulose
When parsing the remote endpoint of an output port, we do :
rport = of_graph_get_remote_port(ep);
rparent = of_graph_get_remote_port_parent(ep);
and then parse the "remote_port" as if it was the remote endpoint,
which is wrong. The code worked fine because we
From: Suzuki K Poulose
Add a helper to check if the given endpoint is input.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
From: Suzuki K Poulose
Refactor the tmc-etr enable operation to make it easier to
handle errors in enabling the hardware. We need to make
sure that the buffer is compatible with the ETR. This
patch re-arranges to make the error handling easier, by
deferring the hardware enablement until all the
From: Suzuki K Poulose
Refactor the tmc-etr enable operation to make it easier to
handle errors in enabling the hardware. We need to make
sure that the buffer is compatible with the ETR. This
patch re-arranges to make the error handling easier, by
deferring the hardware enablement until all the
From: Suzuki K Poulose
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the
From: Leo Yan
In ETB dump function tmc_etb_dump_hw() it has nested loops. The second
level loop is to iterate index in the range [0 .. drvdata->memwidth);
but the index isn't really used in the code, thus the second level
loop is useless.
This patch is to remove the second level loop; the
From: Tomasz Nowicki
For non-VHE systems host kernel runs at EL1 and jumps to EL2 whenever
hypervisor code should be executed. In this case ETM4x driver must
restrict configuration to EL1 when it setups kernel tracing.
However, there is no separate hypervisor privilege level when VHE
is enabled,
From: Suzuki K Poulose
coresight_enable_path() enables the components in a trace
path from a given source to a sink, excluding the source.
The operation is performed in the reverse order; the sink
first and then backwards in the list. However, if we encounter
an error in enabling any of the
From: Leo Yan
In ETB dump function tmc_etb_dump_hw() it has nested loops. The second
level loop is to iterate index in the range [0 .. drvdata->memwidth);
but the index isn't really used in the code, thus the second level
loop is useless.
This patch is to remove the second level loop; the
From: Tomasz Nowicki
For non-VHE systems host kernel runs at EL1 and jumps to EL2 whenever
hypervisor code should be executed. In this case ETM4x driver must
restrict configuration to EL1 when it setups kernel tracing.
However, there is no separate hypervisor privilege level when VHE
is enabled,
From: Suzuki K Poulose
Add support for using TMC-ETR as backend for ETM perf tracing.
We use software double buffering at the moment. i.e, the TMC-ETR
uses a separate buffer than the perf ring buffer. The data is
copied to the perf ring buffer once a session completes.
The TMC-ETR would try to
From: Suzuki K Poulose
Since the ETR now uses mode specific buffers, we can reliably
provide the trace data captured in sysfs mode, even when the ETR
is operating in PERF mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
From: Suzuki K Poulose
We enable the trace path, before activating the source.
If we fail to enable the source, we must disable the path
to make sure it is available for another session.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
From: Suzuki K Poulose
Right now we issue an update_buffer() and reset_buffer() call backs
in succession when we stop tracing an event. The update_buffer is
supposed to check the status of the buffer and make sure the ring buffer
is updated with the trace data. And we store information about the
From: Suzuki K Poulose
We can always find the sink configuration for a given perf_output_handle.
Add a helper to retrieve the sink configuration for a given
perf_output_handle. This will be used to get rid of the set_buffer()
call back.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
From: Suzuki K Poulose
Add support for using TMC-ETR as backend for ETM perf tracing.
We use software double buffering at the moment. i.e, the TMC-ETR
uses a separate buffer than the perf ring buffer. The data is
copied to the perf ring buffer once a session completes.
The TMC-ETR would try to
From: Suzuki K Poulose
Since the ETR now uses mode specific buffers, we can reliably
provide the trace data captured in sysfs mode, even when the ETR
is operating in PERF mode.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
From: Suzuki K Poulose
We enable the trace path, before activating the source.
If we fail to enable the source, we must disable the path
to make sure it is available for another session.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
From: Suzuki K Poulose
Right now we issue an update_buffer() and reset_buffer() call backs
in succession when we stop tracing an event. The update_buffer is
supposed to check the status of the buffer and make sure the ring buffer
is updated with the trace data. And we store information about the
From: Suzuki K Poulose
We can always find the sink configuration for a given perf_output_handle.
Add a helper to retrieve the sink configuration for a given
perf_output_handle. This will be used to get rid of the set_buffer()
call back.
Cc: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
From: Suzuki K Poulose
commit 6403587a930c ("coresight: use put_device() instead of kfree()")
fixes the double freeing of resources and ensures that the device
refcount is dropped properly. Add a comment to explain this to
help the readers and prevent people trying to "unfix" it again.
While at
From: Suzuki K Poulose
commit 6403587a930c ("coresight: use put_device() instead of kfree()")
fixes the double freeing of resources and ensures that the device
refcount is dropped properly. Add a comment to explain this to
help the readers and prevent people trying to "unfix" it again.
While at
The BCM63138 SATA PHY requires a special initialization sequence in
order to operate correctly, mostly tuning incorrect default values.
Implement that sequence and match the documented compatible string as an
entry point into that sequence.
Signed-off-by: Florian Fainelli
---
Good day Greg,
To start with here is the tally I gathered for inclusion in the 4.20
cycle - please consider at your convenience. As usual everything applies
cleanly on your char-misc-next branch (f685fc6ab051).
Second, given the increasing number of patches coming into the coresight
subsystem
From: Suzuki K Poulose
The coresight driver doesn't drop the references on the
remote endpoint/port nodes. Add the missing of_node_put()
calls.
Reported-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 5
From: zhong jiang
Use ERR_CAT inlined function to replace the ERR_PTR(PTR_ERR). It
make the code more concise.
Signed-off-by: zhong jiang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The BCM63138 SATA PHY requires a special initialization sequence in
order to operate correctly, mostly tuning incorrect default values.
Implement that sequence and match the documented compatible string as an
entry point into that sequence.
Signed-off-by: Florian Fainelli
---
Good day Greg,
To start with here is the tally I gathered for inclusion in the 4.20
cycle - please consider at your convenience. As usual everything applies
cleanly on your char-misc-next branch (f685fc6ab051).
Second, given the increasing number of patches coming into the coresight
subsystem
From: Suzuki K Poulose
The coresight driver doesn't drop the references on the
remote endpoint/port nodes. Add the missing of_node_put()
calls.
Reported-by: Mathieu Poirier
Signed-off-by: Suzuki K Poulose
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/of_coresight.c | 5
From: zhong jiang
Use ERR_CAT inlined function to replace the ERR_PTR(PTR_ERR). It
make the code more concise.
Signed-off-by: zhong jiang
Signed-off-by: Mathieu Poirier
---
drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c
Add Device Tree entries for the Broadcom AHCI and SATA PHY controller
found on BCM63138 SoCs
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm63138.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi
The Broadcom BCM963138DVT board has an eSATA port which is fully
functional, turn on the AHCI controller and the companion SATA PHY.
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm963138dvt.dts | 8
1 file changed, 8 insertions(+)
diff --git
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same
Broadcom SATA PHY that other SoCs are using, make it possible to select
that driver on these platforms.
Signed-off-by: Florian Fainelli
---
drivers/phy/broadcom/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c
Add Device Tree entries for the Broadcom AHCI and SATA PHY controller
found on BCM63138 SoCs
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm63138.dtsi | 30 ++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi
The Broadcom BCM963138DVT board has an eSATA port which is fully
functional, turn on the AHCI controller and the companion SATA PHY.
Signed-off-by: Florian Fainelli
---
arch/arm/boot/dts/bcm963138dvt.dts | 8
1 file changed, 8 insertions(+)
diff --git
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same
Broadcom SATA PHY that other SoCs are using, make it possible to select
that driver on these platforms.
Signed-off-by: Florian Fainelli
---
drivers/phy/broadcom/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Hi Kishon, Tejun,
This patch series adds support for the SATA AHCI and PHY found on the
ARM-basd BCM63138 DSL SoCs.
It would probably make sense for patches 1-3 to go through Kishon's
tree, patches 4-7 through Tejun's tree, and I would be merging the last
two patches through the Broadcom ARM-SoC
Document the compatible string "brcm,bcm63138-ahci" as a valid
compatible string for the standard Broadcom AHCI controller.
Signed-off-by: Florian Fainelli
---
Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Hi Kishon, Tejun,
This patch series adds support for the SATA AHCI and PHY found on the
ARM-basd BCM63138 DSL SoCs.
It would probably make sense for patches 1-3 to go through Kishon's
tree, patches 4-7 through Tejun's tree, and I would be merging the last
two patches through the Broadcom ARM-SoC
Document the compatible string "brcm,bcm63138-ahci" as a valid
compatible string for the standard Broadcom AHCI controller.
Signed-off-by: Florian Fainelli
---
Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
The Broadcom STB AHCI controller is the same as the one found on DSL
SoCs, so we will utilize the same driver on these systems as well.
Signed-off-by: Florian Fainelli
---
drivers/ata/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ata/Kconfig
Match the "brcm,bcm63138-ahci" compatible string in order to allow this
driver to probe on such platforms.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct
The Broadcom STB AHCI controller is the same as the one found on DSL
SoCs, so we will utilize the same driver on these systems as well.
Signed-off-by: Florian Fainelli
---
drivers/ata/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ata/Kconfig
Match the "brcm,bcm63138-ahci" compatible string in order to allow this
driver to probe on such platforms.
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index
Signed-off-by: Florian Fainelli
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same
Broadcom SATA PHY that other SoCs are using, make it possible to select
that driver on these platforms.
Signed-off-by: Florian Fainelli
---
drivers/phy/broadcom/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Document the compatible string "brcm,bcm63138-sata-phy" as a valid
compatible string describing the standard Broadcom SATA PHY block.
Signed-off-by: Florian Fainelli
---
Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same
Broadcom SATA PHY that other SoCs are using, make it possible to select
that driver on these platforms.
Signed-off-by: Florian Fainelli
---
drivers/phy/broadcom/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Document the compatible string "brcm,bcm63138-sata-phy" as a valid
compatible string describing the standard Broadcom SATA PHY block.
Signed-off-by: Florian Fainelli
---
Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
On 20 September 2018 17:58:47 BST, Sebastian Reichel
wrote:
>[Dropped a couple of people from CC, added Baolin]
>
>Hi Craig, Baolin and Rob,
>
>On Thu, Sep 20, 2018 at 03:32:29PM +0100, Craig wrote:
>> On 16 September 2018 13:10:45 BST, Sebastian Reichel
> wrote:
>> >Sorry for my long delay
On 20 September 2018 17:58:47 BST, Sebastian Reichel
wrote:
>[Dropped a couple of people from CC, added Baolin]
>
>Hi Craig, Baolin and Rob,
>
>On Thu, Sep 20, 2018 at 03:32:29PM +0100, Craig wrote:
>> On 16 September 2018 13:10:45 BST, Sebastian Reichel
> wrote:
>> >Sorry for my long delay
The mm-of-the-moment snapshot 2018-09-20-12-10 has been uploaded to
http://www.ozlabs.org/~akpm/mmotm/
mmotm-readme.txt says
README for mm-of-the-moment:
http://www.ozlabs.org/~akpm/mmotm/
This is a snapshot of my -mm patch queue. Uploaded at random hopefully
more than once a week.
You
The mm-of-the-moment snapshot 2018-09-20-12-10 has been uploaded to
http://www.ozlabs.org/~akpm/mmotm/
mmotm-readme.txt says
README for mm-of-the-moment:
http://www.ozlabs.org/~akpm/mmotm/
This is a snapshot of my -mm patch queue. Uploaded at random hopefully
more than once a week.
You
There is a plan to replace vm_insert_page with new API
vmf_insert_page. As part of it, converting vm_insert_page
to use vmf_insert_page.
Signed-off-by: Souptick Joarder
---
kernel/kcov.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/kernel/kcov.c b/kernel/kcov.c
index
There is a plan to replace vm_insert_page with new API
vmf_insert_page. As part of it, converting vm_insert_page
to use vmf_insert_page.
Signed-off-by: Souptick Joarder
---
kernel/kcov.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/kernel/kcov.c b/kernel/kcov.c
index
From: Tianyu Lan Sent: Thursday, September 20, 2018 7:30 AM
> On 9/20/2018 12:08 AM, Michael Kelley (EOSG) wrote:
> > From: Tianyu Lan Sent: Monday, September 17, 2018 8:19 PM
> >> +
> >> + if (ret && kvm_available_flush_tlb_with_range()) {
> >> +
From: Tianyu Lan Sent: Thursday, September 20, 2018 7:30 AM
> On 9/20/2018 12:08 AM, Michael Kelley (EOSG) wrote:
> > From: Tianyu Lan Sent: Monday, September 17, 2018 8:19 PM
> >> +
> >> + if (ret && kvm_available_flush_tlb_with_range()) {
> >> +
Am Donnerstag, 20. September 2018, 08:26:38 CEST schrieb Ritesh Raj Sarraf:
> The current code fails to run on amd64 because of hardcoded reference to
> i386
>
> Signed-off-by: Ritesh Raj Sarraf
Thanks for spotting this!
> ---
> arch/um/drivers/port_user.c | 2 +-
> 1 file changed, 1
Am Donnerstag, 20. September 2018, 08:26:38 CEST schrieb Ritesh Raj Sarraf:
> The current code fails to run on amd64 because of hardcoded reference to
> i386
>
> Signed-off-by: Ritesh Raj Sarraf
Thanks for spotting this!
> ---
> arch/um/drivers/port_user.c | 2 +-
> 1 file changed, 1
On Wed, Sep 12, 2018 at 03:22:45PM +0530, Amit Kucheria wrote:
> This is another series of tsens cleanups before we add interrupt support.
> This applies on top of 4.19-rc2.
>
> Patches [1-6] can directly be applied by Eduardo.
> Patches [9-16] can directly be applied by Andy.
Eduardo,
I ACKed
On Wed, Sep 12, 2018 at 03:22:45PM +0530, Amit Kucheria wrote:
> This is another series of tsens cleanups before we add interrupt support.
> This applies on top of 4.19-rc2.
>
> Patches [1-6] can directly be applied by Eduardo.
> Patches [9-16] can directly be applied by Andy.
Eduardo,
I ACKed
The success of a cache pseudo-locked region is measured using
performance monitoring events that are programmed directly at the time
the user requests a measurement.
Modifying the performance event registers directly is not appropriate
since it circumvents the in-kernel perf infrastructure that
The success of a cache pseudo-locked region is measured using
performance monitoring events that are programmed directly at the time
the user requests a measurement.
Modifying the performance event registers directly is not appropriate
since it circumvents the in-kernel perf infrastructure that
On Wed, Sep 12, 2018 at 03:23:01PM +0530, Amit Kucheria wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Matthias Kaehlcke
> Tested-by: Matthias Kaehlcke
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++
> 1 file
On Wed, Sep 12, 2018 at 03:23:01PM +0530, Amit Kucheria wrote:
> One thermal zone per cpu is defined
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Matthias Kaehlcke
> Tested-by: Matthias Kaehlcke
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 170 +++
> 1 file
On Wed, Sep 12, 2018 at 03:23:00PM +0530, Amit Kucheria wrote:
> Initialise the camera thermal zone to export temperature to userspace.
>
> Signed-off-by: Amit Kucheria
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git
On Wed, Sep 12, 2018 at 03:23:00PM +0530, Amit Kucheria wrote:
> Initialise the camera thermal zone to export temperature to userspace.
>
> Signed-off-by: Amit Kucheria
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git
On Wed, Sep 12, 2018 at 03:22:59PM +0530, Amit Kucheria wrote:
> Initialise the gpu thermal zone to export temperature to userspace.
>
> Signed-off-by: Amit Kucheria
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 20
> 1 file changed, 20 insertions(+)
>
> diff --git
On Wed, Sep 12, 2018 at 03:22:59PM +0530, Amit Kucheria wrote:
> Initialise the gpu thermal zone to export temperature to userspace.
>
> Signed-off-by: Amit Kucheria
> ---
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 20
> 1 file changed, 20 insertions(+)
>
> diff --git
On Wed, Sep 12, 2018 at 03:22:57PM +0530, Amit Kucheria wrote:
> This new property allows the number of sensors to be configured from DT
> instead of being hardcoded in platform data. Use it.
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Bjorn Andersson
> ---
>
On Wed, Sep 12, 2018 at 03:22:57PM +0530, Amit Kucheria wrote:
> This new property allows the number of sensors to be configured from DT
> instead of being hardcoded in platform data. Use it.
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Bjorn Andersson
> ---
>
On Wed, Sep 12, 2018 at 03:22:56PM +0530, Amit Kucheria wrote:
> This new property allows the number of sensors to be configured from DT
> instead of being hardcoded in platform data. Use it.
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Matthias Kaehlcke
> Reviewed-by: Bjorn Andersson
> ---
On Wed, Sep 12, 2018 at 03:22:56PM +0530, Amit Kucheria wrote:
> This new property allows the number of sensors to be configured from DT
> instead of being hardcoded in platform data. Use it.
>
> Signed-off-by: Amit Kucheria
> Reviewed-by: Matthias Kaehlcke
> Reviewed-by: Bjorn Andersson
> ---
On Wed, Sep 12, 2018 at 03:22:55PM +0530, Amit Kucheria wrote:
> We've earlier added support to split the register address space into TM
> and SROT regions. Split up the regmap address space into two for msm8916
> that has a similar register layout.
>
> Since tsens-common.c/init_common()
On Wed, Sep 12, 2018 at 03:22:55PM +0530, Amit Kucheria wrote:
> We've earlier added support to split the register address space into TM
> and SROT regions. Split up the regmap address space into two for msm8916
> that has a similar register layout.
>
> Since tsens-common.c/init_common()
On Wed, Sep 12, 2018 at 03:22:54PM +0530, Amit Kucheria wrote:
> We've earlier added support to split the register address space into TM
> and SROT regions. Split up the regmap address space into two for msm8974
> that has a similar register layout.
>
> Since tsens-common.c/init_common()
On Wed, Sep 12, 2018 at 03:22:54PM +0530, Amit Kucheria wrote:
> We've earlier added support to split the register address space into TM
> and SROT regions. Split up the regmap address space into two for msm8974
> that has a similar register layout.
>
> Since tsens-common.c/init_common()
On Thu, Sep 20, 2018 at 12:19:23PM -0600, Jason Gunthorpe wrote:
> This is just a friendly reminder that registration deadlines are
> approaching for this conference. Please see
>
> https://www.linuxplumbersconf.org/event/2/page/7-attend
>
> For details.
>
> This year we expect to have close to a
On Thu, Sep 20, 2018 at 12:19:23PM -0600, Jason Gunthorpe wrote:
> This is just a friendly reminder that registration deadlines are
> approaching for this conference. Please see
>
> https://www.linuxplumbersconf.org/event/2/page/7-attend
>
> For details.
>
> This year we expect to have close to a
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