One group can manage 64 interrupts by using two registers (e.g. STATUS/SET).
However, the integrated irqsteer may support only 32 interrupts which
needs only one register in a group. But the current driver assume there's
a mininum of two registers in a group which result in a wrong register map
for
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Lucas Stach
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3:
* add error check for imx_irqsteer_get_hwirq_base
* use DIV_ROUND_UP
* merge 'hwirq +=32' into for loop
* common error path in probe
From: Honghui Zhang
scripts/coccinelle/api/resource_size.cocci complain about the
following warning:
pcie-mediatek.c:720:13-16: WARNING: Suspicious code. resource_size is maybe
missing with mem
Use resource_size(mem) instead of mem->end - mem->start to eliminate the
complain. Since the MMIO wi
On Wed, Jan 30, 2019 at 01:50:27PM -0500, Jerome Glisse wrote:
> I do not see how VMA changes are any different than using struct page
> in respect to userspace exposure. Those vma callback do not need to be
> set by everyone, in fact expectation is that only handful of driver
> will set those.
>
From: Honghui Zhang
The PCIE_AXI_WINDOW0 defines the translate window size for the request
from EP side. Request outside of this window will be treated as
unsupported request.
Enlarge this window size from fls(0x) to 2^33 to support 8GB
translate address range then EP DMA is capable of f
From: Honghui Zhang
Two patches:
patch 1 fix the complain of scripts/coccinelle/api/resource_size.cocci
patch 2 enlarge the PCIe2AHB window size to support fully access of 4GB DRAM
from EP DMA.
v2:
- Fix the checkpatch complains for patch 1.
- update the commit message and change title of pat
On Thu, Jan 31, 2019 at 09:31:25AM +0200, Heikki Krogerus wrote:
> On Wed, Jan 30, 2019 at 11:13:53AM +0800, Kyle Tso wrote:
> > When Sink negotiates PPS, the voltage range of selected PPS APDO might
> > not cover the previous voltage (out_volt). If the previous out_volt is
> > lower than the new m
On Wed, Jan 30, 2019 at 12:27:40PM +, Jean-Philippe Brucker wrote:
> Hi Peter,
Hi, Jean,
>
> On 30/01/2019 05:57, Peter Xu wrote:
> > AMD IOMMU driver is using the clear_flush_young() to do cache flushing
> > but that's actually already covered by invalidate_range(). Remove the
> > extra no
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