On Thu 24 Jan 08:16 PST 2019, Brian Masney wrote:
> Introduce hammerhead_defconfig for the LG Nexus 5 phone. Includes
> options for USG OTG, WiFi, charger, serial console, gyroscope,
> accelerometer, magnetometer, temperature, and pressure sensors.
>
> The necessary options for the display are al
On 2/1/19 2:21 AM, Hans Verkuil wrote:
On 2/1/19 1:46 AM, shuah wrote:
Hi Hans,
On 1/30/19 12:42 AM, Hans Verkuil wrote:
On 1/30/19 2:50 AM, shuah wrote:
On 1/29/19 2:43 AM, Hans Verkuil wrote:
On 1/29/19 12:48 AM, shuah wrote:
Hi Hans,
On 1/28/19 5:03 AM, Hans Verkuil wrote:
Hi Shuah,
O
On Tue, Feb 5, 2019 at 9:52 AM Marc Gonzalez wrote:
>
> On 05/02/2019 18:24, Marc Gonzalez wrote:
>
> > /*** system hangs here for several seconds, then reboots ***/
>
> Silly me. The system crashes in ufshcd_dump_regs() which is a bug
> I fixed myself. Once I cherry-pick the appropriate fix, the
On Sun, Feb 3, 2019 at 8:34 PM Kai Renzig wrote:
>
> Add touchscreen platform data for the Chuwi Hi8 Air tablet.
>
Pushed to my review and testing queue, thanks!
> Signed-off-by: Kai Renzig
> ---
> Changes in v2:
> - Fix the firmware filename to match the actual touchscreen controller.
>
> dr
On 2019-01-25 16:18:40 [+0100], Borislav Petkov wrote:
> Reviewed-by: Borislav Petkov
thanks.
> Should we do this microoptimization in addition, to save us the
> activation when the kernel thread here:
>
> taskA -> kernel thread -> taskA
>
> doesn't call kernel_fpu_begin() and thus fpu_fp
On Thu 24 Jan 05:00 PST 2019, Niklas Cassel wrote:
> The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level
> triggered interrupt.
>
> The msi_ctrl_int will be high for as long as any MSI status bit is set,
> thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the
> IR
Le 05/02/2019 à 19:03, Laurent Vivier a écrit :
resize_hpt_for_hotplug() reports a warning when it cannot
increase the hash page table ("Unable to resize hash page
table to target order") but this is not blocking and
can make user thinks something has not worked properly.
If the operation can
On Mon, 2019-02-04 at 17:46 -0800, Nadav Amit wrote:
> > On Feb 4, 2019, at 4:16 PM, Alexander Duyck
> > wrote:
> >
> > On Mon, Feb 4, 2019 at 4:03 PM Nadav Amit wrote:
> > > > On Feb 4, 2019, at 3:37 PM, Alexander Duyck
> > > > wrote:
> > > >
> > > > On Mon, 2019-02-04 at 15:00 -0800, Nadav
On Fri, Feb 1, 2019 at 9:32 AM Rajneesh Bhardwaj
wrote:
>
> This patch series provides Icelake support for PMC Core driver and while
> doing so it introduces the Icelake Mobile to intel-family.h as per the
> CPUID from below Coreboot link
> https://github.com/coreboot/coreboot/blob/5ebcea33cd3
The `initialized' member of the fpu struct is always set to one for user
tasks and zero for kernel tasks. This avoids saving/restoring the FPU
registers for kernel threads.
The ->initialized = 0 case for user tasks has been removed in previous changes
for instance by always an explicit init at for
Hi Thierry,
On Fri, 2019-02-01 at 15:00 +0100, Thierry Reding wrote:
[...]
> It sounds pretty good and elegant actually. Let me try to restate to see
> if I understand correctly:
>
> So basically what you're saying is that we would be changing the
> definition of exclusive resets to make them exc
From: Colin Ian King
Shifting a u8 by 24 will cause the value to be promoted to an integer. If
the top bit of the u8 is set then the following conversion to an unsigned
long will sign extend the value causing the upper 32 bits to be set in
the result.
Fix this by casting the u8 value to an unsig
On 2019-01-24 14:34:49 [+0100], Borislav Petkov wrote:
> > set it back to one) or don't return to userland.
> >
> > The context switch code (switch_fpu_prepare() + switch_fpu_finish())
> > can't unconditionally save/restore registers for kernel threads. I have
> > no idea what will happen if we re
resize_hpt_for_hotplug() reports a warning when it cannot
increase the hash page table ("Unable to resize hash page
table to target order") but this is not blocking and
can make user thinks something has not worked properly.
If the operation cannot be done the real error message
will be reported b
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape PCIe
> controller with EP mode.
>
> Signed-off-by: Xiaowei Bao
> Reviewed-by: Minghuan Lian
> Reviewed-by: Zhiqiang Hou
> Reviewed-by: Rob Herring
> ---
> v2:
>
On Tue, Feb 05, 2019 at 06:56:11PM +0100, Thierry Reding wrote:
> Sure, here you go:
>
>
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/host1x/cdma.c#n106
Yes, I think we I can come up with a nicer helper for that.
I had an old invalid address for Jason Gunthorpe in my address book...
Correcting his email in the thread.
On Tue, Feb 05, 2019 at 09:50:59AM -0800, 'Ira Weiny' wrote:
>
> The problem: Once we have pages marked as GUP-pinned how should various
> subsystems work with those markings.
>
> The cu
On Fri, Feb 1, 2019 at 10:43 AM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-23 14:11:37)
> > The phy code was using implicit sequencing between the PHY driver
> > and the UFS driver to implement certain hardware requirements.
> > Specifically, the PHY reset register in the UFS controller n
On Fri, Feb 1, 2019 at 10:00 AM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-23 14:11:35)
> > @@ -1144,6 +1150,8 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> >
> > .is_dual_lane_phy = true,
> > .no_pcs_sw_reset= true,
> > +
> > + .has_ufsphy
On Fri, Feb 1, 2019 at 9:56 AM Stephen Boyd wrote:
>
> Quoting Evan Green (2019-01-23 14:11:34)
> > Expose a reset controller that the phy can use to perform its
> > initialization in a single callback.
> >
> > Also, change the use of the phy functions from ufs-qcom such that
> > phy_poweron actua
On Tue, Feb 05, 2019 at 05:38:37PM +0100, Christoph Hellwig wrote:
> On Tue, Feb 05, 2019 at 05:20:57PM +0100, Thierry Reding wrote:
> > The problem is that if I use dma_alloc_coherent(), then the memory will
> > already be mapped via the SMMU at that point and then the driver, not
> > knowing that
> On Feb 5, 2019, at 4:35 AM, Borislav Petkov wrote:
>
> On Tue, Feb 05, 2019 at 12:31:46PM +0100, Peter Zijlstra wrote:
>> ...
>>
>> So while in general I agree with BUG_ON() being undesirable, I think
>> liberal sprinking in text_poke() is fine; you really _REALLY_ want this
>> to work or fail
Try and register an Energy Model from mediatek-cpufreq to allow
interested subsystems like the task scheduler to use the provided
information.
Signed-off-by: Matthias Kaehlcke
---
drivers/cpufreq/mediatek-cpufreq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/mediatek-cp
Try and register an Energy Model from qcom-cpufreq-hw to allow
interested sub-systems like the task scheduler to use the provided
information.
Signed-off-by: Matthias Kaehlcke
---
drivers/cpufreq/qcom-cpufreq-hw.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cpufreq/qcom-cpufreq
On 05/02/2019 18:24, Marc Gonzalez wrote:
> /*** system hangs here for several seconds, then reboots ***/
Silly me. The system crashes in ufshcd_dump_regs() which is a bug
I fixed myself. Once I cherry-pick the appropriate fix, the board
no longer reboots, but UFS init does fail.
Full boot log h
The problem: Once we have pages marked as GUP-pinned how should various
subsystems work with those markings.
The current work for John Hubbards proposed solutions (part 1 and 2) is
progressing.[1] But the final part (3) of his solution is also going to take
some work.
In Johns presentation he
On Tue, Feb 05, 2019 at 11:09:19AM +0530, Subrahmanya Lingappa wrote:
> Reviewed-by: Subrahmanya Lingappa
I have a feeling you do not read what I write. Please never top-post.
Read this, especially the email etiquette section:
https://kernelnewbies.org/PatchCulture
>
>
>
> On Tue, Jan 29, 2
On Dez 17 2018, Paul Walmsley wrote:
> diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> index 2c290e6aaa6e..e6b962ff39b1 100644
> --- a/arch/riscv/kernel/setup.c
> +++ b/arch/riscv/kernel/setup.c
> @@ -171,7 +171,14 @@ asmlinkage void __init setup_vm(void)
>
> void __init p
Hi, Christophe.
On Wed, Jan 16, 2019 at 04:59:27PM +, Christophe Leroy wrote:
> In powerpc code, there are several places implementing safe
> access to user data. This is sometimes implemented using
> probe_kernel_address() with additional access_ok() verification,
> sometimes with get_user()
On 2/4/19 10:12 PM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20190204:
>
on i386:
../fs/btrfs/zstd.c: In function ‘zstd_reclaim_timer_fn’:
../fs/btrfs/zstd.c:27:35: warning: integer overflow in expression [-Woverflow]
#define ZSTD_BTRFS_RECLAIM_NS (45 * NSEC_PER_SEC)
On Thu, Jan 24, 2019 at 8:27 AM Kai-Heng Feng
wrote:
>
> Hi Darren,
>
> > On Dec 12, 2018, at 22:06, Pali Rohár wrote:
> >
> > On Wednesday 12 December 2018 14:41:25 Kai-Heng Feng wrote:
> >> There's a new wmi event generated by dell-wmi when pressing keyboard
> >> backlight hotkey:
> >> [ 3285.4
From: Tudor Ambarus
Naming clocks is a good practice. Keep supporting unnamed
peripheral clock, to be backward compatible with old DTs.
While here, rename clk to pclk, to indicate that it is a
peripheral clock.
Suggested-by: Boris Brezillon
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezi
From: Tudor Ambarus
Introduced in:
commit b60557876849 ("ARM: dts: at91: sama5d2: switch to new clock binding")
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: no change
v3: new patch
Documentation/devicetree/bindings/spi/atmel-quadspi.txt | 2 +-
From: Tudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: collect R-b
v3: "pclk" was made mandator
From: Tudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory. It uses
different transfer type bits in IFR register. It has dedicated registers
to specify a read or a write instruction: Read Instructi
From: Tudor Ambarus
Split the TFRTYP_TRSFR_ bitfields in 2: one bit encoding the
mem/reg transfer type and one bit encoding the direction of
the transfer (read/write).
Remove NOP when setting read transfer type. Remove useless
setting of write transfer type when
op->data.dir == SPI_MEM_DATA_IN &
From: Tudor Ambarus
The cast is done implicitly.
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: no change
v3: no change
v2: collect R-b
drivers/spi/atmel-quadspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/a
On Tue, Dec 25, 2018 at 9:37 PM Kangjie Lu wrote:
>
> buf->length is first copied in from user space and security-checked. The
> second copy issued by copy_from_user copies it again. The data in user
> space may have been modified by malicious users.
So, we already did a check and copied not more
From: Tudor Ambarus
Naming clocks is a good practice. Make "pclk" madatory even if
we support unnamed clock in the driver, to be backward compatible
with old DTs.
Suggested-by: Boris Brezillon
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: add mi
From: Tudor Ambarus
Let general names to core drivers.
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: collect R-b
v3: no change
v2: update after the removing of iomem access wrappers
drivers/spi/atmel-quadspi.c | 16
1 file chan
From: Tudor Ambarus
Adopt the SPDX license identifiers to ease license compliance
management.
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: no change
v3: no change
v2: collect R-b
drivers/spi/atmel-quadspi.c | 13 +
1 file changed,
From: Tudor Ambarus
Return -ENOTSUPP when atmel_qspi_find_mode() fails. Propagate
the error in atmel_qspi_exec_op().
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: no change
v3: no change
v2: collect R-b
drivers/spi/atmel-quadspi.c | 4 ++--
1 f
From: Tudor Ambarus
The wrappers hid that the accesses are relaxed. Drop them.
Suggested-by: Boris Brezillon
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4:
- drop local variable that kept aq->regs, the compiler should be
smart enough to store i
From: Tudor Ambarus
Set the controller by default in Serial Memory Mode (SMM) at probe.
Cache Mode Register (MR) value to avoid write access when setting
the controller in serial memory mode at exec_op().
Signed-off-by: Tudor Ambarus
---
v6: no change
v5: collect R-b
v4: s/smm/mr, init controll
From: Tudor Ambarus
Patches from 1 to 11 are minor fixes or cosmetics.
Patches 12 and 13 introduce the sam9x60 qspi controller.
sam9x60 qspi controller tested with sst26vf064b jedec,spi-nor flash.
Backward compatibility test done on sama5d2 qspi controller and
mx25l25635e jedec,spi-nor flash.
v
From: Tudor Ambarus
Cosmetic change, no functional change.
Signed-off-by: Tudor Ambarus
Reviewed-by: Boris Brezillon
---
v6: no change
v5: no change
v4: no change
v3: no change
v2: collect R-b
drivers/spi/atmel-quadspi.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --
Hi Rui,
On 23/01/2019 22:08, Rui Zhao wrote:
> On Wednesday, January 23, 2019 10:36 AM, James Morse wrote:
>>> If firmware enables it, they're suppose to handle the interrupt.
>> Ah, so you still have resident firmware!
>> How come your firmware trusts linux not to turn off the memory controller?
Hi Boris,
On 23/01/2019 18:46, Borislav Petkov wrote:
> On Wed, Jan 23, 2019 at 06:36:23PM +, James Morse wrote:
>>> Would like to know what's the impact if this error happens, and how to fit
>>> it
>>> with current reporting in EDAC core.
>>
>> At a guess the interrupt triggers when link_err
On 2/4/19 1:15 PM, Alexander Duyck wrote:
> This patch set provides a mechanism by which guests can notify the host of
> pages that are not currently in use. Using this data a KVM host can more
> easily balance memory workloads between guests and improve overall system
> performance by avoiding un
Hi Yash,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on pwm/for-next]
[also build test ERROR on v5.0-rc4 next-20190205]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux
On 05/02/2019 05:58, Alim Akhtar wrote:
> On 04/02/19 11:12 PM, Marc Gonzalez wrote:
>
>> This reverts commit 60f0187031c05e04cbadffb62f557d0ff3564490.
>>
>> Calling ufshcd_set_vccq_rail_unused hangs my system.
>> It seems vccq is not *not* needed.
>
> AFAIK Samsung and Toshiba UFS devices does n
On Tue, Dec 18, 2018 at 12:02:42PM +, Fabrizio Castro wrote:
> Add PCIe support for the RZ/G2E (a.k.a. R8A774C0).
>
> Signed-off-by: Fabrizio Castro
> Reviewed-by: Geert Uytterhoeven
> ---
> v1->v2:
> * Dropped change to the description of "phys" optional property according
> to Geert's co
Hi,
On Tue, Feb 05, 2019 at 09:27:49AM -0500, Sven Van Asbroeck wrote:
> On Tue, Feb 5, 2019 at 3:27 AM Dmitry Torokhov
> wrote:
> >
> > Are there many more instances of this?
>
> Unfortunately I think so.
> A simple grep brings up a couple of candidates, but I'm sure there are more:
>
> driver
On Fri, Feb 1, 2019 at 10:47 PM Liming Sun wrote:
Thanks for an update, my comments below.
(To Mellanox kernel developer team: guys, perhaps you need to
establish a few rounds of internal review before sending the stuff
outside)
First of all, I didn't find ABI documentation for interface this p
Em Tue, Jan 29, 2019 at 09:23:48AM -0800, Andi Kleen escreveu:
> On Tue, Jan 29, 2019 at 12:05:36PM -0500, William Cohen wrote:
> > Fix incorrect event names for the Load_Miss_Real_Latency metric for
> > Cascadelake server in the same manner as commit 91b2b97025 for SKL/SKX.
>
> Reviewed-by: Andi
On Tue, Feb 5, 2019 at 4:14 AM Wolfram Sang wrote:
>
> On Thu, Jan 03, 2019 at 09:49:27PM -0500, Steven Rostedt wrote:
> > On Thu, 3 Jan 2019 16:42:03 -0800
> > John Sperbeck wrote:
> >
> > > If an smbus transfer fails, there's no guarantee that the output
> > > buffer was written. So, avoid co
On Mon, Feb 04, 2019 at 10:31:39PM +0200, Boaz Harrosh wrote:
> On 01/02/19 09:55, Christoph Hellwig wrote:
> > The only real user of the T10 OSD protocol, the pNFS object layout
> > driver never went to the point of having shipping products, and we
> > removed it 1.5 years ago. Exofs is just a si
Move ad7780 ADC driver out of staging and into the mainline.
The ad7780 is a sigma-delta analog to digital converter. This driver provides
reading voltage values and status bits from both the ad778x and ad717x series.
Its interface also allows writing on the FILTER and GAIN GPIO pins on the
ad778
Add SPDX identifier (GPL-2.0) to the AD7780 driver.
Signed-off-by: Renato Lui Geh
---
drivers/staging/iio/adc/ad7780.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/staging/iio/adc/ad7780.c b/drivers/staging/iio/adc/ad7780.c
index 7804cd2b273e..163e3c983598 100644
To maintain consistency between ad7780_probe and ad7780_remove orders,
regulator initialization has been moved to after GPIO initializations.
Signed-off-by: Renato Lui Geh
---
drivers/staging/iio/adc/ad7780.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff
Previously, the AD7780 driver only supported gpio for the 'powerdown'
pin. This commit adds suppport for the 'gain' and 'filter' pin.
Signed-off-by: Renato Lui Geh
Signed-off-by: Giuliano Belinassi
Co-developed-by: Giuliano Belinassi
---
Changes in v3:
- Renamed ad7780_chip_info's filt
This series of patches adds user input to ad7780 'gain' & 'filter' gpio
pins, moves regulator initialization to after gpio initialization to
maintain consistency between probe and remove, adds SPDX to the driver's
license, and moves the ad7780 to the mainline.
Renato Lui Geh (4):
staging: iio: a
On Tue, Feb 5, 2019 at 8:53 AM Dexuan Cui wrote:
>
> > From: Dan Williams
> > Sent: Sunday, February 3, 2019 11:14 AM
> > > ...
> > > As I understand, the essence of the issue is: Hyper-V emulates the
> > > label mechanism (i.e. it supports _LSI and LSR), but doesn't do it
> > > right (i.e. it do
On Tue, Feb 05, 2019 at 08:46:23AM -0800, Dave Hansen wrote:
> On 2/4/19 10:18 PM, Borislav Petkov wrote:
> > Well, if it breaks old apps, it probably needs to be opt-in anyway.
>
> Yes, this was my assumption.
It _should_ not break portable code (because RISC has much stronger #AC
requirements)
The 01/29/2019 18:21, Boris Brezillon wrote:
+Optional properties:
+Driver calculates controller timings base on NAND flash memory timings and
+the following delays in picoseconds.
+ - cdns,if-skew : Skew value of the output signals of the NAND Flash interface
+ - cdns,nand2-delay : Delay val
On Tue, Feb 05, 2019 at 05:51:13PM +0100, David Sterba wrote:
> On Tue, Feb 05, 2019 at 11:30:12AM -0500, Dennis Zhou wrote:
> > > > > Something is wrong, the patchset on top of 5.0-rc5 hangs in test
> > > > > btrfs/007, without a stacktrace. V1 was fine and I double checked that
> > > > > rc5 itse
On Tue, Feb 05, 2019 at 07:19:16AM -0800, Dave Hansen wrote:
> On 2/5/19 12:48 AM, Peter Zijlstra wrote:
> > On Mon, Feb 04, 2019 at 12:46:30PM -0800, Dave Hansen wrote:
> >> So, the compromise we reached in this case is that Intel will fully
> >> document the future silicon architecture, and then
Hallo ihr Lieben, frohes neues Jahr, ich hoffe, es geht euch gut
und deine Familie? Ich habe einen wichtigen Deal, mit dem ich diskutieren kann
Bitte antworten Sie mir umgehend.
danken
Michelle
On 2/4/19 10:41 AM, Eugeniy Paltsev wrote:
> Fix reversed logic while actionpoints configuration (full/min)
> detection.
>
> Fixies: 7dd380c338f1e ("ARC: boot log: print Action point details")
> Signed-off-by: Eugeniy Paltsev
LGTM.
Thx,
-vineet
> ---
> arch/arc/kernel/setup.c | 2 +-
> 1 file
Please get back to me My name is Sgt.Sherri Gallagher,
05.02.2019 19:41, Sowjanya Komatineni пишет:
>> Please use "./scripts/checkpatch.pl --strict *.patch" and fix all its
>> complains, but only those that really make sense. For example ignore the
>> "CHECK: Lines should not end with a '('" warnings.
>>
>> Here checkpatch recommends to use the BIT(
> From: Dan Williams
> Sent: Sunday, February 3, 2019 11:14 AM
> > ...
> > As I understand, the essence of the issue is: Hyper-V emulates the
> > label mechanism (i.e. it supports _LSI and LSR), but doesn't do it
> > right (i.e. it doesn't support _LSW).
> >
> > To manage the namespaces, Linux can
If I plug in a USB-to-Ethernet gadget, the kernel sees something:
usb 2-1: new SuperSpeed Gen 1 USB device number 2 using xhci-hcd
usb 2-1: New USB device found, idVendor=0b95, idProduct=1790, bcdDevice= 1.00
usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 2-1: Product: AX881
On Tue, Feb 05, 2019 at 11:30:12AM -0500, Dennis Zhou wrote:
> > > > Something is wrong, the patchset on top of 5.0-rc5 hangs in test
> > > > btrfs/007, without a stacktrace. V1 was fine and I double checked that
> > > > rc5 itself is fine.
> > >
> > > Hmmm, well that's awkward. I ran xfstests and
Hi Vineet, Corentin,
> -Original Message-
> From: Vineet Gupta
> Sent: Tuesday, February 5, 2019 7:42 PM
> To: Eugeniy Paltsev ; cla...@baylibre.com
> Cc: linux-kernel@vger.kernel.org; alexey.brod...@synopsys.com;
> khil...@baylibre.com; linux-snps-
> a...@lists.infradead.org
> Subject:
On Tue, Feb 05, 2019 at 05:21:07PM +0100, Daniel Vetter wrote:
> Someone owes me a beer ...
I find that deeply offensive - it is clearly directed at me personally
as author of the component helper.
There are double-standards in the kernel ecosystem with respect to
documentation - there are entire
Hi Seth,
On Tue, 2019-02-05 at 09:18 -0600, Seth Forshee wrote:
> On Thu, Jan 31, 2019 at 02:18:59PM -0500, Mimi Zohar wrote:
> > Require signed kernel modules on systems with secure boot mode enabled.
> >
> > To coordinate between appended kernel module signatures and IMA
> > signatures, only de
On 2/4/19 10:18 PM, Borislav Petkov wrote:
> On Mon, Feb 04, 2019 at 03:24:23PM -0800, Dave Hansen wrote:
>> Actually, there's one part of all this that I forgot. Will split lock
>> detection be enumerated _widely_?
>
> You never know what users will do. The moment it gets out, it better be
> des
On 2/5/19 3:42 AM, Eugeniy Paltsev wrote:
> Hi Corentin,
>
> In case of devboards (like HSDK) we really often disable bootloader and load
> Linux image in memory via JTAG. Enabling CONFIG_ARC_UBOOT_SUPPORT by
> default will break it as we will try to interpret some junk in a registers
> as a pointe
In commit
72a671ced66db ("x86, fpu: Unify signal handling code paths for x86 and x86_64
kernels")
the 32bit and 64bit path of the signal delivery code were merged. The 32bit
version:
|int save_i387_xstate_ia32(void __user *buf)
|…
| if (cpu_has_xsave)
| return save_i387_x
>> Cai, can you please check if you can reproduce this issue in your
>> environment with 5.0-rc5?
>
> Yes, please do - practical confirmation more convincing than my certainty.
Indeed, I am no longer be able to reproduce this anymore.
On Fri, Feb 01, 2019 at 06:38:35AM +0100, Hugo Lefeuvre wrote:
> introduce wait_event_freezable_hrtimeout, an interruptible and freezable
> version of wait_event_hrtimeout.
>
> Among others this helper will allow for simplifications in
> staging/android/vsoc.c.
>
> Signed-off-by: Hugo Lefeuvre
>
* Roger Quadros [190205 09:40]:
> On 04/02/19 18:33, Tony Lindgren wrote:
> >
> > shrdram2: memory@1 {
> > device_type = "memory";
> > reg = <0x1 0x3000>;
> > };
>
> Shared RAM is not so straight forward. Both PRU firmwares and both
> application drivers
> Please use "./scripts/checkpatch.pl --strict *.patch" and fix all its
> complains, but only those that really make sense. For example ignore the
> "CHECK: Lines should not end with a '('" warnings.
>
>Here checkpatch recommends to use the BIT() macro:
>
> CHECK: Prefer using the BIT macro
> #3
Hi John,
On Sun, Feb 03, 2019 at 09:21:35PM -0800, john.hubb...@gmail.com wrote:
> From: John Hubbard
>
> 1. Added Documentation/vm/get_user_pages.rst
>
> 2. Added a GET_USER_PAGES entry in MAINTAINERS
>
> Cc: Dan Williams
> Cc: Jan Kara
> Signed-off-by: Jérôme Glisse
> Signed-off-by: John
On Tue, Feb 05, 2019 at 05:20:57PM +0100, Thierry Reding wrote:
> The problem is that if I use dma_alloc_coherent(), then the memory will
> already be mapped via the SMMU at that point and then the driver, not
> knowing that memory has already been mapped, will attempt to map an IOVA
> which will c
On Fri, Feb 01, 2019 at 06:38:05AM +0100, Hugo Lefeuvre wrote:
> Replace schedule(); try_to_freeze() by freezable_schedule().
>
> Tasks calling freezable_schedule() set the PF_FREEZER_SKIP flag
> before calling schedule(). Unlike tasks calling schedule();
> try_to_freeze() tasks calling freezable_
Commissioner for the Reduction of the National Debt
UK Debt Management Office.
Eastcheap Court EC3M 8UD
London United Kingdom
EC3M 8UD.
Email: ukdebtmanagement...@gmail.com
Attention: Beneficiary
My name is Mrs. Jo Whelan.
As you must be aware, I am the Controller General for the Reduction of
On Sat, 2 Feb 2019 17:53:29 +, Marc Zyngier wrote:
> Creating a macvtap on a DSA-backed interface results in the following
> splat when lockdep is enabled:
>
> [ 19.638080] IPv6: ADDRCONF(NETDEV_CHANGE): lan0: link becomes ready
> [ 23.041198] device lan0 entered promiscuous mode
> [ 2
On 2/5/19 11:27 AM, Michael S. Tsirkin wrote:
> On Tue, Feb 05, 2019 at 08:06:33AM -0500, Nitesh Narayan Lal wrote:
>> On 2/4/19 11:14 PM, Michael S. Tsirkin wrote:
>>> On Mon, Feb 04, 2019 at 03:18:48PM -0500, Nitesh Narayan Lal wrote:
This patch includes the following:
1. Basic skeleton
Ping...any thoughts on these patches? (May have slipped through the
cracks over people's holiday vacations I'd guess.)
Thanks,
Zev
On Thu, Dec 27, 2018 at 05:12:28AM CST, Zev Weiss wrote:
Hello,
After being left with an unusable system after a typo executing
something like 'echo $((1<<24)) >
On Tue, Feb 05, 2019 at 05:27:34PM +0100, David Sterba wrote:
> On Tue, Feb 05, 2019 at 11:03:02AM -0500, Dennis Zhou wrote:
> > On Tue, Feb 05, 2019 at 03:57:53PM +0100, David Sterba wrote:
> > > On Mon, Feb 04, 2019 at 03:19:56PM -0500, Dennis Zhou wrote:
> > > > Hi everyone,
> > > >
> > > > V2
Hi Miquel,
Hi Paul,
Paul Cercueil wrote on Mon, 4 Feb 2019
16:04:25
-0300:
The boot ROM of the JZ4725B SoC expects a specific OOB layout on the
NAND, so we use it unconditionally in the ingenic-nand driver.
Also add the jz4725b-bch driver to support the JZ4725B-specific BCH
hardware.
pon., 4 lut 2019 o 23:42 David Lechner napisał(a):
>
> On 1/31/19 7:39 AM, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski
> >
> > We need to create an irq domain if we want to select SPARSE_IRQ. The
> > cp-intc driver already supports it, but aintc doesn't. Use the helpers
> > provided
Hi Miquel,
On Tue, 5 Feb 2019 12:07:28 +0100, Miquel Raynal
wrote:
> +/* There is no suspend to RAM support at DSA level yet, the switch
> configuration
> + * would be lost after a power cycle so prevent it to be suspended.
> + */
> +static int __maybe_unused mv88e6xxx_suspend(struct device *
> -Original Message-
> From: Martin Kepplinger
> Sent: Tuesday, February 5, 2019 9:53 AM
> To: Han Xu ; bbrezil...@kernel.org;
> miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; linux-
> m...@lists.infradead.org
> Cc: l
On Tue, Feb 05, 2019 at 08:06:33AM -0500, Nitesh Narayan Lal wrote:
> On 2/4/19 11:14 PM, Michael S. Tsirkin wrote:
> > On Mon, Feb 04, 2019 at 03:18:48PM -0500, Nitesh Narayan Lal wrote:
> >> This patch includes the following:
> >> 1. Basic skeleton for the support
> >> 2. Enablement of x86 platfo
On Tue, Feb 05, 2019 at 11:03:02AM -0500, Dennis Zhou wrote:
> On Tue, Feb 05, 2019 at 03:57:53PM +0100, David Sterba wrote:
> > On Mon, Feb 04, 2019 at 03:19:56PM -0500, Dennis Zhou wrote:
> > > Hi everyone,
> > >
> > > V2 had only a handful of changes outside of minor feedback.
> > > 0001:
> > >
On Tue, 5 Feb 2019 15:44:04 +
wrote:
> @@ -450,28 +499,49 @@ static int atmel_qspi_probe(struct
> platform_device *pdev) goto exit;
> }
>
> + aq->caps = of_device_get_match_data(&pdev->dev);
> + if (aq->caps && aq->caps->has_qspick) {
Can we add a caps instance to the sama5d2
Someone owes me a beer ...
While typing these I think doing an s/component_master/aggregate/
would be useful:
- it's shorter :-)
- I think component/aggregate is much more meaningful naming than
component/puppetmaster or something like that. At least to my
English ear "aggregate" emphasizes mu
401 - 500 of 928 matches
Mail list logo
