From: Allen Pais
This issue was detected with the help of Coccinelle.
Signed-off-by: Allen Pais
---
arch/s390/tools/gen_opcode_table.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/s390/tools/gen_opcode_table.c
b/arch/s390/tools/gen_opcode_table.c
index
Hi all,
Today's linux-next merge of the mfd tree got a conflict in:
drivers/mfd/Kconfig
between commit:
9baddb61dfec ("mfd: Fix unmet dependency warning for MFD_TPS68470")
from Linus' tree and commit:
09fdc9857712 ("mfd: Kconfig: Fix I2C_DESIGNWARE_PLATFORM dependencies")
from the mfd
The usb support for asyncio encoded one of it's values in the wrong
field. It should have used si_value but instead used si_addr which is
not present in the _rt union member of struct siginfo.
The result is a POSIX and glibc incompatible encoding of fields in
struct siginfo with si_code of
On Thu, Feb 07, 2019 at 10:50:55AM -0800, Mike Kravetz wrote:
> On 1/30/19 1:14 PM, Mike Kravetz wrote:
> > Files can be created and mapped in an explicitly mounted hugetlbfs
> > filesystem. If pages in such files are migrated, the filesystem
> > usage will not be decremented for the associated
On Fri, Feb 8, 2019 at 11:25 AM Kunihiko Hayashi
wrote:
>
> Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update
> the CPU-gear value.
>
> Fixes: d08f1f0d596c ("clk: uniphier: add CPU-gear change (cpufreq) support")
> Cc: linux-sta...@vger.kernel.org
> Signed-off-by: Kunihiko Hayashi
Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update
the CPU-gear value.
Fixes: d08f1f0d596c ("clk: uniphier: add CPU-gear change (cpufreq) support")
Cc: linux-sta...@vger.kernel.org
Signed-off-by: Kunihiko Hayashi
---
drivers/clk/uniphier/clk-uniphier-cpugear.c | 2 +-
1 file
From: Arun Parameswaran
Date: Thu, 7 Feb 2019 16:01:18 -0800
> Fixes the issues with non BCM58XX chips in the b53 driver
> failing, when the irq is not specified in the device tree.
>
> Removed the check for BCM58XX in b53_srab_prepare_irq(),
> so the 'port->irq' will be set to '-EXIO' if the
Add a new function irq_domain_translate_twocell() that is to be used as
the translate function in struct irq_domain_ops for the v2 IRQ API.
This patch also changes irq_domain_xlate_twocell() from the v1 IRQ API
to call irq_domain_translate_twocell() in the v2 IRQ API. This required
changes to
Hi all,
After merging the sound-asoc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
sound/soc/xilinx/xlnx_formatter_pcm.c: In function 'xlnx_formatter_pcm_new':
sound/soc/xilinx/xlnx_formatter_pcm.c:539:9: error: void value not ignored as
it ought to be
return
From: Linus Walleij
The hierarchical irqchip never before ran into a situation
where the parent is not "simple", i.e. does not implement
.irq_ack() and .irq_mask() like most, but the qcom-pm8xxx.c
happens to implement only .irq_mask_ack().
Since we want to make ssbi-gpio a hierarchical child of
From: Linus Walleij
Before we fixed up the interrupt hierarchy for the SSBI
GPIO controller, we had to use the PM8058 directly to pick
interrupts. After making the interrupt controller work properly,
we can reference the real interrupt parent.
Signed-off-by: Linus Walleij
Signed-off-by: Brian
ssbi-gpio did not have any irqchip support so consumers of this in
device tree would need to call gpio[d]_to_irq() in order to get the
proper IRQ on the underlying PMIC. IRQ chips in device tree should
be usable from the start without the consumer having to make an
additional call to get the
The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.
This change was tested on an APQ8060 DragonBoard.
Signed-off-by: Brian Masney
Tested-by: Linus Walleij
---
Changes since v1:
- None
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.
Note that the IRQs started at 24 instead of 192 like all of the other
PMICs. This is the same IRQs as the MPP for this board. qcom-pm8xxx.c
doesn't
This patch series adds hierarchical IRQ chip support to ssbi-gpio so
that device tree consumers can request an IRQ directly from the GPIO
block rather than having to request an IRQ from the underlying PMIC.
For more background information, see the email thread with Linus
Walleij's excellent
Convert the PM8XXX IRQ code to use the version 2 IRQ interface in order
to support hierarchical IRQ chips. This is necessary so that ssbi-gpio
can be setup as a hierarchical IRQ chip with PM8xxx as the parent. IRQ
chips in device tree should be usable from the start without having to
make an
Now that ssbi-gpio is a proper hierarchical IRQ chip, and all in-tree
users of device tree have been updated, we can now drop the hack that
was introduced to disassociate the old Linux virq if a hwirq mapping
already exists. That patch was introduced to not break git bisect for
any existing
Check to see if the hwirq is already associated with another virq on
this IRQ domain. If so, then disassociate it before associating the
hwirq with the new virq.
This is a temporary hack that is needed in order to not break git
bisect for existing boards. The next patch in this series converts
Add interrupt controller properties now that ssbi-gpio is a proper
hierarchical IRQ chip. The interrupts property is no longer needed so
remove it.
This change was not tested on any hardware but the same change was
tested on an APQ8060 DragonBoard with no issues.
Signed-off-by: Brian Masney
---
On 2/7/19 8:51 PM, Stefan Berger wrote:
On 2/7/19 7:33 PM, Jarkko Sakkinen wrote:
On Thu, Feb 07, 2019 at 06:29:43PM -0500, Stefan Berger wrote:
On 2/7/19 4:29 PM, Jarkko Sakkinen wrote:
diff --git a/drivers/char/tpm/tpm2-cmd.c b/drivers/char/tpm/tpm2-cmd.c
index
From: Moritz Fischer
Date: Thu, 7 Feb 2019 12:14:55 -0800
> Add fixed_phy_register_with_gpiod() API. It lets users create a
> fixed_phy instance that uses a GPIO descriptor which was obtained
> externally e.g. through platform data.
> This enables platform devices (non-DT based) to use GPIOs
Hello,
THP is currently supported for
- PMD level pages (anon and file)
- PUD level pages (file - DAX file system)
THP is a single entry mapping at standard page table levels (either PMD or PUD)
But architectures like ARM64 supports non-standard page table level huge pages
with contiguous
Cc-ing Steven
https://lore.kernel.org/lkml/20190207124635.3885-1-...@ellerman.id.au/T/#u
On (02/07/19 23:46), Michael Ellerman wrote:
> Arch code can set a "dump stack arch description string" which is
> displayed with oops output to describe the hardware platform.
>
> It is useful to
On 2/7/2019 5:16 PM, sathyanarayanan kuppuswamy wrote:
If I remember this right, aligned request is only supported on ATS v1.1
but not supported on v1.0.
Its added in v1.1.
This means that you should probably have some kind of version check
here.
The existing upstream kernel doesn't boot for non-smp
configuration. This patch series address various issues
with non-smp configurations.
The patch series is based on 5.0-rc5. Tested on QEMU and
HiFive Unleashed board using both OpenSBI & BBL.
Changes from v2->v3
1. Fixed spurious white space.
On 2/7/19 7:33 PM, Jarkko Sakkinen wrote:
On Thu, Feb 07, 2019 at 06:29:43PM -0500, Stefan Berger wrote:
On 2/7/19 4:29 PM, Jarkko Sakkinen wrote:
On Thu, Feb 07, 2019 at 07:41:56PM +0100, Alexander Steffen wrote:
On 06.02.2019 13:06, Jarkko Sakkinen wrote:
On Wed, Feb 06, 2019 at 12:47:07AM
Currently, logical CPU id to physical hartid mapping is
defined for both smp and non-smp configurations. This
is not required as we need this only for smp configuration.
The mapping function can define directly boot_cpu_hartid
for non-smp use case.
The reverse mapping function i.e. hartid to
In SMP path, __cpu_up waits for other CPU to come online
indefinitely. This is wrong as other CPU might be disabled
in machine mode and possible CPU is set to the cpus present
in DT.
Introduce a completion variable and waits only for a second.
Signed-off-by: Atish Patra
Reviewed-by: Anup Patel
Currently, clocksource registration happens for an invalid cpu
for non-smp kernels. This lead to kernel panic as cpu hotplug
registration will fail for those cpus. Moreover,
riscv_hartid_to_cpuid can return errors now.
Do not proceed if hartid or cpuid is invalid. Take this opprtunity
to print
In non-smp configuration, hartid can be higher that NR_CPUS.
riscv_of_processor_hartid should not be compared to hartid to
NR_CPUS in that case. Moreover, this function checks all the
DT properties of a hart node. NR_CPUS comparison seems out of
place.
Signed-off-by: Atish Patra
Reviewed-by:
Currently, we set hwcap based on first valid cpu from
DT. This may not be correct always as that CPU might not
be current booting cpu.
Set hwcap based on the boot cpu instead of first
valid CPU from DT. Add a sanity check to identify if any
hwcap do not match.
Signed-off-by: Atish Patra
---
It is perfectly okay to call riscv_hartid_to_cpuid for a
hartid that is not mapped with an CPU id. It can happen
if the calling functions retrieves the hartid from DT.
However, that hartid was never brought online by the
firmware or kernel for any reasons.
No need to BUG() in the above case. A
We should never have a cpuid greater that NR_CPUS. Compare
with NR_CPUS before creating the mapping between logical
and physical CPU ids. This is also mandatory as NR_CPUS
check is removed from riscv_of_processor_hartid.
Signed-off-by: Atish Patra
Reviewed-by: Anup Patel
Reviewed-by: Christoph
riscv_hartid_to_cpuid can return invalid cpuid for a hart
that is present in DT but was never brought up.
Print the appropriate warning message and continue.
Signed-off-by: Atish Patra
Reviewed-by: Anup Patel
Reviewed-by: Christoph Hellwig
---
drivers/irqchip/irq-sifive-plic.c | 5 +
1
Simplify field's initialization by directly assigning its final value
instead of initializing the variable to sero and then bitwise or-ing
it.
Signed-off-by: Andrey Smirnov
Cc: Mathias Nyman
Cc: Greg Kroah-Hartman
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Changes
Xhci_handshake() implements the algorithm already captured by
readl_poll_timeout_atomic(). Convert the former to use the latter to
avoid repetition.
Signed-off-by: Andrey Smirnov
Cc: Mathias Nyman
Cc: Greg Kroah-Hartman
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Get page size order using __ffs() instead of open coding it with a loop.
Signed-off-by: Andrey Smirnov
Cc: Mathias Nyman
Cc: Greg Kroah-Hartman
Cc: linux-...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Changes since [v1]:
- Code changed to use __ffs()
- Added check for
On Thu, Feb 07, 2019 at 03:54:58PM -0800, Dan Williams wrote:
> On Thu, Feb 7, 2019 at 9:17 AM Jason Gunthorpe wrote:
> >
> > Insisting to run RDMA & DAX without ODP and building an elaborate
> > revoke mechanism to support non-ODP HW is inherently baroque.
> >
> > Use the HW that supports ODP.
>
On Fri, Feb 08, 2019 at 12:44:14AM +, Derrick, Jonathan wrote:
> On Thu, 2019-02-07 at 23:56 +0100, David Kozub wrote:
> > On Mon, 4 Feb 2019, Christoph Hellwig wrote:
> >
> > > On Fri, Feb 01, 2019 at 09:50:17PM +0100, David Kozub wrote:
> > > > From: Jonas Rabenstein
> > > >
> > > >
'devm_iounmap'; did you mean 'pci_iounmap'?
[-Werror=implicit-function-declaration]
devm_iounmap(dev, mdev->reg_base);
^~~~
pci_iounmap
and lots more ...
Probably caused by commit
e3b01f0d576a ("drm: remove drmP.h from drm_modeset_helper.h")
I have used the
Hi all,
After merging the drm-misc tree, today's linux-next build (arm
multi_v7_defconfig) produced this warning:
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c: In function 'sun6i_dsi_probe':
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c:1053:9: warning: 'ret' may be used
uninitialized in this function
Hi Marek,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pm/linux-next]
[also build test WARNING on next-20190207]
[cannot apply to v5.0-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
On Sat, Feb 02, 2019 at 09:55:29AM +0500, Ivan Mironov wrote:
> On Tue, 2019-01-15 at 19:27 -0700, Jerry Hoemann wrote:
> > On Mon, Jan 14, 2019 at 07:36:14AM +0500, Ivan Mironov wrote:
>
> Somehow I missed the whole pretimout thing when reading about the
> watchdog API. Thanks for clarification,
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/i915/intel_display.c
between commit:
9f58892ea996 ("drm/i915: Pull all the reset functionality together into
i915_reset.c")
from the drm tree and commit:
d0e93599d396 ("drm/i915: prepare for
This EC is an incompatible variant of the typical Chrome OS embedded
controller. It uses the same low-level communication and a similar
protocol with some significant differences. The EC firmware does
not support the same mailbox commands so it is not registered as a
cros_ec device type. This
There is a new chromebook that contains a different Embedded Controller
(codename Wilco) than the rest of the chromebook series. Thus the kernel
requires a different driver than the already existing and generalized
cros_ec_* drivers. The core of the communication with the EC
is implemented in
In order to allow this code to be re-used, remove the dependency
on the rest of the cros_ec code from the cros_ec_lpc_mec functions.
Instead of using a hardcoded register base address of 0x800 have
this be passed in to cros_ec_lpc_mec_init(). The existing cros_ec
use case now passes in the 0x800
Add a debugfs attribute that allows sending raw commands to the EC.
This is useful for development and debug but should not be enabled
in a production environment.
To test:
Get the EC firmware build date
First send the request command
> echo 00 f0 38 00 03 00 > raw
Then read the result.
This Embedded Controller has an internal RTC that is exposed
as a standard RTC class driver with read/write functionality.
The driver is added to the drivers/rtc/ so that the maintainer of that
directory will be able to comment on this change, as that maintainer is
the expert on this system. In
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
struct boo entry[];
};
instance = alloc(sizeof(struct
From: "Enrico Weigelt, metux IT consult"
GPIO platform driver for the AMD G-series PCH (eg. on GX-412TC)
This driver doesn't registers itself automatically, as it needs to
be provided with platform specific configuration, provided by some
board driver setup code.
Didn't implement oftree
From: "Enrico Weigelt, metux IT consult"
Driver for PCengines APUv2 board that supports GPIOs via AMD PCH
and attached LEDs and keys.
Cc: linux-g...@vger.kernel.org
Cc: linus.wall...@linaro.org
Cc: bgolaszew...@baylibre.com
Cc: dvh...@infradead.org
Cc: a...@infradead.org
Cc:
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
struct boo entry[];
};
size = sizeof(struct foo) +
Hi Andreas,
Thank you for the patch.
On Tue, Feb 05, 2019 at 07:38:13AM +0100, Andreas Kemnade wrote:
> This adds an additional backlight property as described
> in panel-common.txt
>
> Signed-off-by: Andreas Kemnade
Reviewed-by: Laurent Pinchart
> ---
>
On Thu, Feb 7, 2019 at 8:59 PM Aaro Koskinen wrote:
>
> From: Aaro Koskinen
>
> Allow specifying reboot_mode for panic only. This is needed on systems
> where ramoops is used to store panic logs, and user wants to use warm
> reset to preserve those, while still having cold reset on normal
Hi Andreas,
Thank you for the patch.
On Tue, Feb 05, 2019 at 07:38:12AM +0100, Andreas Kemnade wrote:
> This panel has a backlight, so fetch it from devicetree using the
> corresponding property as documented in panel-common.txt. It is
> implemented the same way as in panel-dpi.c
> This ensures
Hi Linus,
Missed fixes last week as had nothing until amdgpu showed up on
Saturday. Other stuff has since rolled in along with some more amdgpu
fixes, so we have two weeks of those, and some i915, vmwgfx, sun4i,
rockchip and omap fixes.
Dave.
amdgpu/radeon:
- fix crash on passthrough for SI
-
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
struct boo entry[];
};
size = sizeof(struct foo) +
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
struct boo entry[];
};
size = sizeof(struct foo) +
- ndesaulni...@google.com wrote:
> Similar to how we differentiate between CONFIG_CC_IS_GCC and
> CONFIG_CC_IS_CLANG, add CONFIG_LD_IS_BFD, CONFIG_LD_IS_GOLD, and
> CONFIG_LD_IS_LLD.
>
> This simiplifies patches to Makefiles that need to do different things
> for different linkers.
What
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
void *entry[];
};
size = sizeof(struct foo) + count *
Jerome Brunet writes:
> As pointed out in review, a few clock are not properly defined.
>
> Reported-by: Martin Blumenstingl
> Fixes: 2a4c63e080cd ("soc: amlogic: clk-measure: add axg and g12a support")
> Signed-off-by: Jerome Brunet
I squashed this with the original too.
In doing so, I
Hi Jonathan,
On Thu, Feb 7, 2019 at 8:52 PM Jonathan Neuschäfer
wrote:
>
> Hi,
>
> I'm currently porting mainline Linux to an i.MX507-based board
> (preliminary DT here[1]). Recently I've enabled esdhc1 in the
> devicetree.
>
> However, as soon as the mmc driver (sdhci-esdhc-imx.c) disables
Jerome Brunet writes:
> The clk-msr node should be in cbus.
>
> Fixes: eeca2cf15e05 ("arm64: dts: meson: g12a: add clk measure support")
> Signed-off-by: Jerome Brunet
This one I squashed with the original (in branch v5.1/dt64)
Kevin
On Thu, Feb 7, 2019 at 10:02 PM wrote:
>
> Similar to how we differentiate between CONFIG_CC_IS_GCC and
> CONFIG_CC_IS_CLANG, add CONFIG_LD_IS_BFD, CONFIG_LD_IS_GOLD, and
> CONFIG_LD_IS_LLD.
>
> This simiplifies patches to Makefiles that need to do different things
> for different linkers.
>
>
On Thu, 7 Feb 2019 20:36:32 +
Dexuan Cui wrote:
> When we unload pci-hyperv, the host doesn't send us a PCI_EJECT message.
> In this case we also need to make sure the sysfs pci slot directory
> is removed, otherwise "cat /sys/bus/pci/slots/2/address" will trigger
> "BUG: unable to handle
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
struct boo entry[];
};
size = sizeof(struct foo) +
On Thu, 2019-02-07 at 23:56 +0100, David Kozub wrote:
> On Mon, 4 Feb 2019, Christoph Hellwig wrote:
>
> > On Fri, Feb 01, 2019 at 09:50:17PM +0100, David Kozub wrote:
> > > From: Jonas Rabenstein
> > >
> > > Enable users to mark the shadow mbr as done without completely
> > > deactivating the
On Wed, 6 Feb 2019 15:52:43 -0500
Steven Rostedt wrote:
> On Fri, 18 Jan 2019 13:44:25 +0900
> Masami Hiramatsu wrote:
>
> > @@ -180,7 +183,12 @@ fetch_store_strlen(unsigned long addr)
> > int len;
> > void __user *vaddr = (void __force __user *) addr;
> >
> > - len =
On Thu, 2019-02-07 at 15:57 -0800, Dan Williams wrote:
> Commit 11189c1089da "acpi/nfit: Fix command-supported detection" broke
> ND_CMD_CALL for bus-level commands. The "func = cmd" assumption is only
> valid for:
>
> ND_CMD_ARS_CAP
> ND_CMD_ARS_START
> ND_CMD_ARS_STATUS
>
Make use of the struct_size() helper instead of an open-coded version
in order to avoid any potential type mistakes, in particular in the
context in which this code is being used.
So, change the following form:
sizeof(*ev) + ev->num_hndl * sizeof(struct hci_comp_pkts_info)
to :
On Thu, Feb 07, 2019 at 06:29:43PM -0500, Stefan Berger wrote:
> On 2/7/19 4:29 PM, Jarkko Sakkinen wrote:
> > On Thu, Feb 07, 2019 at 07:41:56PM +0100, Alexander Steffen wrote:
> > > On 06.02.2019 13:06, Jarkko Sakkinen wrote:
> > > > On Wed, Feb 06, 2019 at 12:47:07AM +0200, Jarkko Sakkinen
According to NXP's FAE feedback and a comment in ATF firmware, PCIE1
and PCIE2 power domains can't really be used independently. Due to
shared reset line both power domains have to be turned on at the same
time. Account for that quirk by combining PCIE power domains into a
single 'pgc_pcie' power
Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.
Signed-off-by: Andrey Smirnov
Cc: Shawn Guo
Cc: Fabio Estevam
Cc: Chris Healy
Cc: Lucas Stach
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc:
Add a node for reset controller IP block found on i.MX8MQ.
Signed-off-by: Andrey Smirnov
Cc: Shawn Guo
Cc: Fabio Estevam
Cc: Chris Healy
Cc: Lucas Stach
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc:
Maxime Jourdan writes:
> On Mon, Feb 4, 2019 at 10:49 AM Neil Armstrong
> wrote:
>>
>> When probe fails, a platforn_device is still associated to the node,
>> but dev_get_drvdata() returns NULL.
>>
>> Handle this case by returning a consistent error.
>>
>> Fixes: d4983983d987 ("soc: amlogic:
Everyone:
This series contains all of the i.MX Device Tree changes I made to
enable support of PCIe on i.MX8MQ EVK. Marked as RFC since "arm64:
dts: imx8mq-evk: Enable PCIE0 interface" contains proposed AUX clock
binding that is not part of the PCI tree yet (to be submitted once we
agree on this
Add nodes for two PCIe controllers found on i.MX8MQ.
Signed-off-by: Andrey Smirnov
Cc: Shawn Guo
Cc: Fabio Estevam
Cc: Chris Healy
Cc: Lucas Stach
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc: linux-arm-ker...@lists.infradead.org
Cc:
Mark iomuxc_gpr as compatible with "fsl,imx6q-iomuxc-gpr" in order for
to allow i.MX6 PCIe driver to use it.
Signed-off-by: Andrey Smirnov
Cc: Shawn Guo
Cc: Fabio Estevam
Cc: Chris Healy
Cc: Lucas Stach
Cc: Leonard Crestez
Cc: "A.s. Dong"
Cc: Richard Zhu
Cc: linux-...@nxp.com
Cc:
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
struct boo entry[];
};
size = sizeof(struct foo) +
Hi all,
Today's linux-next merge of the net-next tree got a conflict in:
drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
between commit:
218d05ce326f ("net/mlx5e: Don't overwrite pedit action when multiple pedit
used")
from the net tree and commit:
c500c86b0c75 ("net/mlx5e: support
--
Ich beabsichtige, Ihnen einen Teil meines Vermögens als freiwillige
finanzielle Spende an Sie zu geben. Reagieren Sie auf die Teilnahme.
Wang Jianlin
Wanda-Gruppe
On Mon, 4 Feb 2019 20:58:58 +0100
Daniel Bristot de Oliveira wrote:
>
> +static void text_poke_bp_set_handler(void *addr, void *handler,
> + unsigned char int3)
> +{
> + bp_int3_handler = handler;
> + bp_int3_addr = (u8 *)addr + sizeof(int3);
> +
On Thu, Feb 07, 2019 at 09:03:52PM +0100, Hugo Lefeuvre wrote:
> Replace schedule(); try_to_freeze() by freezable_schedule().
>
> Tasks calling freezable_schedule() set the PF_FREEZER_SKIP flag
> before calling schedule(). Unlike tasks calling schedule();
> try_to_freeze() tasks calling
On Mon, 4 Feb 2019 20:58:58 +0100
Daniel Bristot de Oliveira wrote:
> diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
> index d458c7973c56..202af29c43c0 100644
> --- a/arch/x86/kernel/alternative.c
> +++ b/arch/x86/kernel/alternative.c
> @@ -767,6 +767,29 @@ int
On Thu, Feb 07, 2019 at 06:50:42PM -0500, Steven Rostedt wrote:
> On Thu, 7 Feb 2019 18:39:02 -0500
> Joel Fernandes wrote:
> > > > +
> > > > +spath="$(dirname "$(readlink -f "$0")")"
> > > > +
> > > > +rm -rf $1.tmp
> > > > +mkdir $1.tmp
> > > > +
> > > > +for f in "${@:2}";
> > > > + do
From: Babu Moger
RESCTRL feature is supported both on Intel and AMD now. Some features
are implemented differently. Add vendor detection mechanism. Use the vendor
check where there are differences.
Signed-off-by: Babu Moger
Signed-off-by: Fenghua Yu
---
From: Babu Moger
For now, disable MBA and MBM tests for AMD. Deciding test pass/fail
is not clear right now. We can enable when we have some clarity.
Signed-off-by: Babu Moger
Signed-off-by: Fenghua Yu
---
tools/testing/selftests/resctrl/resctrl_tests.c | 4 ++--
1 file changed, 2
Commit 11189c1089da "acpi/nfit: Fix command-supported detection" broke
ND_CMD_CALL for bus-level commands. The "func = cmd" assumption is only
valid for:
ND_CMD_ARS_CAP
ND_CMD_ARS_START
ND_CMD_ARS_STATUS
ND_CMD_CLEAR_ERROR
The function number otherwise needs to be pulled from the
From: Sai Praneeth Prakhya
Total memory bandwidth can be monitored from perf IMC counter and from
resctrl file system. Later the two will be compared to verify the total
memory bandwidth read from resctrl is correct.
Signed-off-by: Sai Praneeth Prakhya
Signed-off-by: Arshiya Hayatkhan Pathan
From: Arshiya Hayatkhan Pathan
MBA (Memory Bandwidth Allocation) test starts a stressful memory
bandwidth benchmark and allocates memory bandwidth from 100% down
to 10% for the benchmark process. For each allocation, compare
perf IMC counter and mbm total bytes from resctrl. The difference
resctrl tests will be implemented. README is added for the tool first.
Signed-off-by: Fenghua Yu
Signed-off-by: Babu Moger
---
tools/testing/selftests/resctrl/README | 54 ++
1 file changed, 54 insertions(+)
create mode 100644
From: Sai Praneeth Prakhya
The basic resctrl file system operations and data are added for future
usage by resctrl selftest tool.
Signed-off-by: Sai Praneeth Prakhya
Signed-off-by: Arshiya Hayatkhan Pathan
Signed-off-by: Fenghua Yu
Signed-off-by: Babu Moger
---
From: Arshiya Hayatkhan Pathan
MBM (Memory Bandwidth Monitoring) test is the first implemented selftest.
It starts a stressful memory bandwidth benchmark and assigns the
bandwidth pid in a resctrl monitoring group. Read and compare perf IMC
counter and MBM total bytes for the benchmark. The
From: Babu Moger
AMD uses the cache l3 boundary for schemata masks. Update it accordigly.
Signed-off-by: Babu Moger
Signed-off-by: Fenghua Yu
---
tools/testing/selftests/resctrl/resctrlfs.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git
The resctrl selftest will be maintained by RDT maintainers.
Signed-off-by: Fenghua Yu
Signed-off-by: Babu Moger
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8c68de3cfd80..fa3805b5ed56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12819,6
From: Arshiya Hayatkhan Pathan
Cache QoS Monitoring (CQM) selftest starts stressful cache benchmark
with specified size of memory to access the cache. Last Level cache
occupancy reported by CQM should be close to the size of the memory.
Signed-off-by: Arshiya Hayatkhan Pathan
Signed-off-by:
With more and more resctrl features are being added by Intel, AMD
and ARM, a test tool is becoming more and more useful to validate
that both hardware and software functionalities work as expected.
We introduce resctrl selftest to cover resctrl features on both
X86 and ARM architectures. It first
From: Sai Praneeth Prakhya
The callback starts a child process and puts the child pid in created
resctrl group with specified memory bandwidth in schemata. The child
starts running benchmark.
Signed-off-by: Sai Praneeth Prakhya
Signed-off-by: Arshiya Hayatkhan Pathan
Signed-off-by: Fenghua Yu
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