Hi Andrey,
Thank you for the patch.
On Tue, Feb 26, 2019 at 11:36:01AM -0800, Andrey Smirnov wrote:
> Implementation of tc_poll_timeout() is almost a 100% copy-and-paste of
> the code for regmap_read_poll_timeout(). Replace copied code with a
> call to the original. No functional change intended.
Hi,
On 02/03/2019 09:04, Yu Chen wrote:
> The patchset adds support for usb functionality of Hikey960, includes:
> - dwc3 driver for Hisilicon Kirin Soc hi3660
> - usb driver for HiKey960 board
> - some adjustment in dwc3, usb gadget and typec driver
> - dts for support usb of HiKey960
>
> This p
On (03/04/19 20:40), Tetsuo Handa wrote:
> On 2019/03/04 12:22, Sergey Senozhatsky wrote:
> > On (02/23/19 13:42), Tetsuo Handa wrote:
> > [..]
> >> This patch tries to address "don't lockup the system" with minimal risk of
> >> failing to "print out printk() messages", by allowing printk() callers
On Fri, Mar 1, 2019 at 4:15 PM Marek Behun wrote:
> On Fri, 1 Mar 2019 15:34:26 +0100
> Linus Walleij wrote:
>
> > > +What: /sys/bus/moxtet/devices/moxtet-./output_value
> > > +Date: March 2019
> > > +KernelVersion: 5.2
> > > +Contact: Marek Behún
> > > +Description: (
On Sat, Mar 2, 2019 at 3:50 AM Qian Cai wrote:
>
> The commit a00cc7d9dd93 ("mm, x86: add support for PUD-sized transparent
> hugepages") introduced pudp_huge_get_and_clear_full() but no one uses
> its return code. In order to not diverge from
> pmdp_huge_get_and_clear_full(), just change zap_huge
On 01/03/2019 21:48, Kirill A. Shutemov wrote:
> On Wed, Feb 27, 2019 at 05:05:39PM +, Steven Price wrote:
>> walk_page_range() is going to be allowed to walk page tables other than
>> those of user space. For this it needs to know when it has reached a
>> 'leaf' entry in the page tables. This
We have a helper function ds2482_calculate_config() which is calculating
the config value, so just use it instead of passing the same variable
in all calls to this function.
Also fixes the placement of module parameters to match with:
50fa2951bd74 (w1: Organize driver source to natural/common orde
Gabriel C writes:
> Am Mo., 4. März 2019 um 12:28 Uhr schrieb Paul Menzel :
>
>> Resuming from ACPI S3 on the Dell XPS 13 9370 with Debian Sid/unstable,
>> Linux 4.19.20 showed the warning below. It’s not reproducible.
[...]
>> [ 3018.992916] Call Trace:
>> [ 3018.992921] ? ath10k_conf_tx+0x7a
On Sat, Mar 02, 2019 at 08:33:57PM -0300, Paul Cercueil wrote:
> This is cleaner, more future-proof, and incidentally it also fixes the
> PWM resetting its config when stopped/started several times.
>
> Signed-off-by: Paul Cercueil
> Tested-by: Mathieu Malaterre
> Tested-by: Artur Rojek
> ---
>
On 01/03/2019 21:47, Kirill A. Shutemov wrote:
> On Wed, Feb 27, 2019 at 05:05:37PM +, Steven Price wrote:
>> walk_page_range() is going to be allowed to walk page tables other than
>> those of user space. For this it needs to know when it has reached a
>> 'leaf' entry in the page tables. This
Hi Miquel,
> -Original Message-
> From: Miquel Raynal
> Sent: Monday, March 4, 2019 3:13 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com;
> linux-...@lists.infradead.org; linux-
> ker.
Am Mo., 4. März 2019 um 12:28 Uhr schrieb Paul Menzel :
>
> Dear Linux folks,
>
>
> Resuming from ACPI S3 on the Dell XPS 13 9370 with Debian Sid/unstable,
> Linux 4.19.20 showed the warning below. It’s not reproducible.
>
> ```
> [0.00] Linux version 4.19.0-3-amd64 (debian-ker...@lists.deb
te to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Jani-Nikula/log2-make-is_power_of_2-integer-constant-expression-when-possible/20190304-153529
> config: microblaze-mmu_defconfig (attached as .config)
> compiler: microblaze-linux-gcc
On 27/02/2019 17.17, Philipp Puschmann wrote:
> This patch fixes a bug that prevents freeing the reset gpio on unloading
> the module.
>
> aic3x_i2c_probe is called when loading the module and it calls list_add
> with a probably uninitialized list entry aic3x->list (next = prev = NULL)).
> So e
On 2019/03/04 12:22, Sergey Senozhatsky wrote:
> On (02/23/19 13:42), Tetsuo Handa wrote:
> [..]
>> This patch tries to address "don't lockup the system" with minimal risk of
>> failing to "print out printk() messages", by allowing printk() callers to
>> tell printk() "store $body_text_lines lines
Hi Rob,
Thanks for providing the review comments..
Please find my response inline.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Saturday, February 23, 2019 2:01 AM
> To: Nava kishore Manne
> Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; linux-arm-k
Dear Linux folks,
Resuming from ACPI S3 on the Dell XPS 13 9370 with Debian Sid/unstable,
Linux 4.19.20 showed the warning below. It’s not reproducible.
```
[0.00] Linux version 4.19.0-3-amd64 (debian-ker...@lists.debian.org)
(gcc version 8.2.0 (Debian 8.2.0-20)) #1 SMP Debian 4.19.20-1
On Thu, Jan 17, 2019 at 01:11:22AM +0530, Sheetal Tigadoli wrote:
> update macros to remove braces around numbers
>
> Signed-off-by: Sheetal Tigadoli
> ---
> drivers/pwm/pwm-bcm-kona.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
Applied, thanks.
I dropped the "driv
On 3/4/2019 4:04 PM, Nicolas Boichat wrote:
On Wed, Feb 13, 2019 at 4:56 PM Nicolas Boichat wrote:
On Tue, Jan 22, 2019 at 4:46 PM Prateek Patel wrote:
On 11/10/2018 2:58 AM, Rob Herring wrote:
On Fri, Nov 9, 2018 at 1:09 AM Prateek Patel wrote:
From: Sri Krishna chowdary
Memory reser
On Mon, 2019-03-04 at 12:14 +0100, Paolo Bonzini wrote:
> On 04/03/19 12:10, Xiaoyao Li wrote:
> > Like you said before, I think we don't need the condition judgment
> > "if(boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))", but to set
> > F(CORE_CAPABILITY)
> > always for guest since MSR_IA32_CORE_CAP
Hi Schrempf,
Schrempf Frieder wrote on Mon, 18 Feb
2019 10:42:45 +:
> From: Frieder Schrempf
>
> Currently supported bad block marker positions within the block are:
> * in first page only
> * in last page only
> * in first or second page
>
> Some ESMT NANDs are known to have been shipped
On 04/03/19 12:10, Xiaoyao Li wrote:
> Like you said before, I think we don't need the condition judgment
> "if(boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))", but to set
> F(CORE_CAPABILITY)
> always for guest since MSR_IA32_CORE_CAPABILITY is emulated.
>
> And we should set the right emulated va
These patches adds SAR ADC support for the G12A SoCs, using
the same setup/configuration as AXG and GXL.
The only change is the clocks, they are now handled by the AO
Clock Controller, but it doesn't change the bindings or the driver.
Neil Armstrong (2):
dt-bindings: iio: adc: document the Meso
Add the SAR ADC driver for the Amlogic Meson-G12A SoC.
Signed-off-by: Neil Armstrong
---
drivers/iio/adc/meson_saradc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 729becb2d3d9..69aeb5c58a9f 100644
--- a/driver
Update the documentation to expicitly support the Meson-G12A SoC.
Signed-off-by: Neil Armstrong
---
.../devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt
b/Documenta
On Mär 01 2019, Yash Shah wrote:
> This patch series adds a PWM driver and DT documentation
> for HiFive Unleashed board. The patches are mostly based on
> Wesley's patch.
That doesn't appear to work with the heartbeat trigger, the led doesn't
flash.
Andreas.
--
Andreas Schwab, SUSE Labs, sch
On Mon, 2019-03-04 at 11:49 +0100, Paolo Bonzini wrote:
> On 04/03/19 11:47, Xiaoyao Li wrote:
> > On Mon, 2019-03-04 at 09:38 +0100, Paolo Bonzini wrote:
> > > On 02/03/19 03:45, Fenghua Yu wrote:
> > > > From: Xiaoyao Li
> > > >
> > > > In the latest Intel SDM, CPUID.(EAX=7H,ECX=0):EDX[30] will
Hi Dave,
On 3/1/19 4:54 PM, Dave P Martin wrote:
On Fri, Mar 01, 2019 at 10:37:54AM +, Amit Daniel Kachhap wrote:
Hi,
On 2/21/19 9:24 PM, Dave Martin wrote:
On Tue, Feb 19, 2019 at 02:54:31PM +0530, Amit Daniel Kachhap wrote:
[...]
diff --git a/arm/aarch64/include/kvm/kvm-config-arc
On (03/04/19 19:00), Sergey Senozhatsky wrote:
>
> But in general, channels which depend on preemptible printk will become
> totally useless in some cases.
>
Which brings me to a question - what are those messages/channels?
Not important enough to be printed on consoles immediately, yet importan
On Wed, Feb 27, 2019 at 04:24:35PM +, claudiu.bez...@microchip.com wrote:
> From: Claudiu Beznea
>
> Add compatible string for SAM9X60 HLCDC's PWM.
>
> Signed-off-by: Claudiu Beznea
> ---
> drivers/pwm/pwm-atmel-hlcdc.c | 3 +++
> 1 file changed, 3 insertions(+)
I guess it makes more sens
Hi,
>
>hi,
>On Thu, 2019-02-14 at 19:45 +, Pawel Laszczak wrote:
>> This patch introduce new Cadence USBSS DRD driver to linux kernel.
>>
>> The Cadence USBSS DRD Driver is a highly configurable IP Core whichi
>> can be instantiated as Dual-Role Device (DRD), Peripheral Only and
>> Host Only (
Hi Frieder,
Schrempf Frieder wrote on Mon, 18 Feb
2019 10:42:41 +:
> From: Frieder Schrempf
>
> The information about where the manufacturer puts the bad block
> markers inside the bad block and in the OOB data is stored in
> different places. Let's move this information to the chip struct
On Mon, Feb 25, 2019 at 04:44:30PM +, claudiu.bez...@microchip.com wrote:
> From: Claudiu Beznea
>
> This series adds support for PWM controller of the new SAM9X60. The difference
> b/w this one and the provious AT91SAM9X5 is the counter size (32 bits compared
> with 16 bits on the previous v
Add the bindings for the Bifrost family of ARM Mali GPUs.
The Bifrost GPU architecture is similar to the Midgard family,
but with a different Shader Core & Execution Engine structures.
Bindings are based on the Midgard family bindings, but the inner
architectural changes makes it a separate famil
Hi James,
On 2/27/19 12:03 AM, James Morse wrote:
Hi Amit,
On 19/02/2019 09:24, Amit Daniel Kachhap wrote:
This feature will allow the KVM guest to allow the handling of
pointer authentication instructions or to treat them as undefined
if not set. It uses the existing vcpu API KVM_ARM_VCPU_INI
When submitted v2 of the G12A AO-CLK IDs, the SAR_ADC_SEL ID was moved
to the internal non-exported bindings, but this clock is necessary and
mandatory for the SAR ADC bindings.
Export it back to the public bindings.
Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings")
S
Hi James,
On 2/27/19 12:01 AM, James Morse wrote:
Hi Amit,
On 19/02/2019 09:24, Amit Daniel Kachhap wrote:
From: Mark Rutland
When pointer authentication is supported, a guest may wish to use it.
This patch adds the necessary KVM infrastructure for this to work, with
a semi-lazy context swit
On Tue, Feb 26, 2019 at 10:59 AM Souptick Joarder wrote:
>
> On Tue, Feb 26, 2019 at 7:18 AM Michael Ellerman wrote:
> >
> > Souptick Joarder writes:
> > > Remove duplicate headers which are included twice.
> > >
> > > Signed-off-by: Sabyasachi Gupta
> > > Signed-off-by: Souptick Joarder
> > >
The G12A Documentation lacked these 2 reset lines, but they are present and
used for each USB 2 PHYs.
Add them to the dt-bindings for the upcoming USB support.
Fixes: dbfc54534dfc ("dt-bindings: reset: meson: add g12a bindings")
Signed-off-by: Neil Armstrong
---
include/dt-bindings/reset/amlogi
On 04/03/19 11:47, Xiaoyao Li wrote:
> On Mon, 2019-03-04 at 09:38 +0100, Paolo Bonzini wrote:
>> On 02/03/19 03:45, Fenghua Yu wrote:
>>> From: Xiaoyao Li
>>>
>>> In the latest Intel SDM, CPUID.(EAX=7H,ECX=0):EDX[30] will enumerate
>>> the presence of the IA32_CORE_CAPABILITY MSR.
>>>
>>> Update
On 04/03/19 11:17, Peter Zijlstra wrote:
> On Mon, Mar 04, 2019 at 09:33:16AM +0100, Paolo Bonzini wrote:
>> Why not instead change set_bit/clear_bit to use btsl/btrl instead of
>> btsq/btrq?
>
> At least one of the faulty users (wireless) is in generic code and needs
> fixing regardless.
>
> For
Hi Florian,
On Fri, Mar 01, 2019 at 07:08:56PM -0800, Florian Fainelli wrote:
> On 3/1/2019 7:07 AM, Antoine Tenart wrote:
> > On Fri, Mar 01, 2019 at 03:19:53PM +0100, Andrew Lunn wrote:
> >> On Fri, Mar 01, 2019 at 12:00:47PM +0100, Antoine Tenart wrote:
> >>> When the Marvell 10G PHYs are set o
On Mon, Mar 04, 2019 at 08:03:47AM +, Haibo Xu (Arm Technology China) wrote:
> On 2019/3/1 2:32, Sudeep Holla wrote:
> > Currently each architecture handles PTRACE_SYSEMU in very similar way.
> > It's completely arch independent and can be handled in the code helping
> > to consolidate PTRACE_S
On 04/03/19 11:11, Peter Zijlstra wrote:
> On Fri, Mar 01, 2019 at 06:44:57PM -0800, Fenghua Yu wrote:
>> A bit in reg_ch_conf_pending in wl271 and tmp_ch_bitmap is set
>> atomically by set_bit(). set_bit() sets the bit in a single
>> unsigned long location. If the variables are not aligned to
>
On Mon, 2019-03-04 at 09:38 +0100, Paolo Bonzini wrote:
> On 02/03/19 03:45, Fenghua Yu wrote:
> > From: Xiaoyao Li
> >
> > In the latest Intel SDM, CPUID.(EAX=7H,ECX=0):EDX[30] will enumerate
> > the presence of the IA32_CORE_CAPABILITY MSR.
> >
> > Update GET_SUPPORTED_CPUID to expose this fea
On Tue, Feb 19, 2019 at 10:58:06AM +0100, Mathieu Othacehe wrote:
> Split pwm-soc array in one struct per soc and point to the
> corresponding on in of-data.
>
> Signed-off-by: Mathieu Othacehe
> ---
> drivers/pwm/pwm-hibvt.c | 17 -
> 1 file changed, 12 insertions(+), 5 deletion
On Mon, Mar 04, 2019 at 09:36:27AM +, Haibo Xu (Arm Technology China) wrote:
> On 2019/3/1 2:32, Sudeep Holla wrote:
> > Now that we have a new hook ptrace_syscall_enter that can be called from
> > syscall entry code and it handles PTRACE_SYSEMU in generic code, we
> > can do some cleanup using
Add the Amlogic G12A Family USB3 + PCIE Combo PHY Bindings.
This PHY can provide exclusively USB3 or PCIE support on shared I/Os.
Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
---
.../bindings/phy/meson-g12a-usb3-pcie-phy.txt | 22 +++
1 file changed, 22 insert
Adds the specific compatible string for the DWC2 IP found in the
Amlogic G12A SoC Family.
Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
Adds the bindings for the Amlogic G12A USB Glue HW.
The Amlogic G12A SoC Family embeds 2 USB Controllers :
- a DWC3 IP configured as Host for USB2 and USB3
- a DWC2 IP configured as Peripheral USB2 Only
A glue connects these both controllers to 2 USB2 PHYs,
and optionnally to an USB3+PCIE Combo P
This patchs sets the params for the DWC2 Controller found in the
Amlogic G12A SoC family.
It mainly sets the settings reported incorrect by the driver,
leaving the remaining detected automatically by the driver and
provided by the DT node.
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc2/para
This adds support for the shared USB3 + PCIE PHY found in the
Amlogic G12A SoC Family.
It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of
the board.
Selection is done by the #phy-cells, making the mode static and exclusive.
Signed-off-by: Neil Armstrong
---
drivers/phy/aml
This adds support for the USB2 PHY found in the Amlogic G12A SoC Family.
It supports Host and/or Peripheral mode, depending on it's position.
The first PHY is only used as Host, but the second supports Dual modes
defined by the USB Control Glue HW in front of the USB Controllers.
Signed-off-by: N
Add the Amlogic G12A Family USB2 OTG PHY Bindings
The PHY can work in host or peripheral modes depending on it's position.
Configuration of the mode is part of the USBCTRL registers which are
outside of the PHY registers.
Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
Reviewed-b
Adds support for Amlogic G12A USB Control Glue HW.
The Amlogic G12A SoC Family embeds 2 USB Controllers :
- a DWC3 IP configured as Host for USB2 and USB3
- a DWC2 IP configured as Peripheral USB2 Only
A glue connects these both controllers to 2 USB2 PHYs, and optionnally
to an USB3+PCIE Combo PH
This patchset adds support for USB on Amlogic G12A SoCs.
This patchset is composed with :
- bindings of the PHYs
- bindings of the USB Control Glue
- PHY Drivers
- USB Control Glue driver
Device Tree nodes will be added in a separate patchset.
The Amlogic G12A USB Complex is composed of :
- 2 US
This patch implements Audio Mixer machine driver for NXP iMX8 SOCs.
It connects together Audio Mixer and related SAI instances.
Signed-off-by: Viorel Suman
Acked-by: Nicolin Chen
---
sound/soc/fsl/Kconfig | 9 ++
sound/soc/fsl/Makefile | 2 +
sound/soc/fsl/imx-audmix.c | 327 ++
Add the DT binding documentation for NXP Audio Mixer
CPU DAI driver.
Signed-off-by: Viorel Suman
Acked-by: Nicolin Chen
Acked-by: Rob Herring
---
.../devicetree/bindings/sound/fsl,audmix.txt | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/d
This patch implements Audio Mixer CPU DAI driver for NXP iMX8 SOCs.
The Audio Mixer is a on-chip functional module that allows mixing of
two audio streams into a single audio stream.
Audio Mixer datasheet is available here:
https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf
Signed-off-by
The patchset adds NXP Audio Mixer (AUDMIX) device and machine
drivers and related DT bindings documentation.
Changes since V4:
1. Removed "model" attribute from device driver DT bindings documentation
as suggested by Nicolin.
Changes since V3:
1. Removed machine driver DT bindings documentatio
Hi Paul,
Paul Cercueil wrote on Sat, 9 Feb 2019 16:23:04
-0300:
> The boot ROM of the JZ4725B SoC expects a specific OOB layout on the
> NAND, so we use it unconditionally in the ingenic-nand driver.
>
> Also add the jz4725b-bch driver to support the JZ4725B-specific BCH
> hardware.
>
> Signe
On Wed, Feb 13, 2019 at 4:56 PM Nicolas Boichat wrote:
>
> On Tue, Jan 22, 2019 at 4:46 PM Prateek Patel wrote:
> >
> >
> > On 11/10/2018 2:58 AM, Rob Herring wrote:
> > > On Fri, Nov 9, 2018 at 1:09 AM Prateek Patel wrote:
> > >> From: Sri Krishna chowdary
> > >>
> > >> Memory reserved with "n
If the block [contig_hint_start, contig_hint_start + contig_hint)
matches block->right_free area, need use "<=", not "<".
Signed-off-by: Peng Fan
---
V1:
Based on https://patchwork.kernel.org/cover/10832459/ applied linux-next
boot test on qemu aarch64
mm/percpu.c | 3 ++-
1 file changed,
pcpu_find_block_fit is not find block index, it is to find
the bitmap off in a chunk.
Signed-off-by: Peng Fan
---
V1:
Based on https://patchwork.kernel.org/cover/10832459/ applied linux-next
mm/percpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/percpu.c b/mm/perc
Hi Paul,
Paul Cercueil wrote on Sat, 9 Feb 2019 16:23:03
-0300:
> Add support for probing the ingenic-nand driver on the JZ4740 SoC from
> Ingenic, and the jz4740-ecc driver to support the JZ4740-specific
> ECC hardware.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Changes:
>
> v2: New patch
On Fri, 1 Mar 2019 at 18:28, Stephen Boyd wrote:
>
> Quoting Ulf Hansson (2019-02-28 05:59:19)
> > PSCI firmware v1.0+, supports two different modes for CPU_SUSPEND. The
> > Platform Coordinated mode, which is the default and mandatory mode, while
> > support for the OS initiated (OSI) mode is opt
Hi,
On 21/02/2019 09:14, Felipe Balbi wrote:
>
> Hi,
>
> (please break your emails at 80-columns)
>
> Pawel Laszczak writes:
One more thing. Workaround has implemented algorithm that decide for which
endpoint it should be enabled. e.g for composite device MSC+NCM+ACM it
should
On Fri, Mar 01, 2019 at 10:51:27AM +0100, Geert Uytterhoeven wrote:
> On Fri, Mar 1, 2019 at 9:57 AM Wen Yang wrote:
> > The call to of_get_next_child returns a node pointer with refcount
> > incremented thus it must be explicitly decremented after the last
> > usage.
> >
> > Detected by coccinell
Nicholas Piggin writes:
> Will Deacon's on March 2, 2019 12:03 am:
>> In preparation for removing all explicit mmiowb() calls from driver
>> code, implement a tracking system in asm-generic based loosely on the
>> PowerPC implementation. This allows architectures with a non-empty
>> mmiowb() defin
Hi Paul,
Paul Cercueil wrote on Sat, 9 Feb 2019 16:23:02
-0300:
> The ingenic-nand driver uses an API provided by the jz4780-bch driver.
> This makes it difficult to support other SoCs in the jz4780-bch driver.
> To work around this, we separate the API functions from the SoC-specific
> code, s
On 04/03/2019 03:09, Halil Pasic wrote:
On Fri, 22 Feb 2019 16:29:56 +0100
Pierre Morel wrote:
We need to associate the ap_vfio_queue, which will hold the
per queue information for interrupt with a matrix mediated device
which hold the configuration and the way to the CRYCB.
[..]
+static int
From: Ludovic Barre
This patch adds get_datactrl_cfg callback in mmci_host_ops
to allow to get datactrl configuration specific at variant.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmc
On Mon, Mar 04, 2019 at 09:33:16AM +0100, Paolo Bonzini wrote:
> Why not instead change set_bit/clear_bit to use btsl/btrl instead of
> btsq/btrq?
At least one of the faulty users (wireless) is in generic code and needs
fixing regardless.
For better or worse; the bitmap stuff is defined to work o
From: Ludovic Barre
This patch series adds get_datactrl_cfg callback in mmci_host_ops
to allow to get datactrl configuration specific at variant.
Ludovic Barre (5):
mmc: mmci: add get_datactrl_cfg callback
mmc: mmci: define get_dctrl_cfg for legacy variant
mmc: mmci: qcom: define get_dctrl
Add Thomas and Ingo to CC, and x86 ML.
On 03/04/19 at 01:55pm, Baoquan He wrote:
> The declarations related to immovable memory handling are put out of
> the BOOT_COMPRESSED_MISC_H #ifdef scope, wrap them inside.
>
> Signed-off-by: Baoquan He
> ---
> v2->v3:
> Add code comment to clearly note
From: Ludovic Barre
This patch defines get_dctrl_cfg callback for qcom variant.
qcom variant has a specific block size definition.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci_qcom_dml.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/host/mmci_qcom_dml.c b/dr
From: Ludovic Barre
This patch defines get_dctrl_cfg callback for legacy variants
whatever DMA_ENGINE configuration.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 38 --
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/
From: Ludovic Barre
This patch allows to get datactrl configuration specific
at variant. This introduce more flexibility on datactlr
value.
Signed-off-by: Ludovic Barre
---
drivers/mmc/host/mmci.c | 13 +
drivers/mmc/host/mmci.h | 5 -
2 files changed, 1 insertion(+), 17 delet
From: Ludovic Barre
This patch defines get_dctrl_cfg callback for sdmmc variant.
sdmmc variant has specific stm32 transfer modes.
sdmmc data transfer mode selection could be:
-Block data transfer ending on block count.
-SDIO multibyte data transfer.
-MMC Stream data transfer (not used).
-Block da
As I'll no longer be working with Prevas, add a mailmap entry so
any mail directed towards me reaches the appropriate mailbox.
Signed-off-by: Sean Nyekjaer
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index ea98fcc197e4..4087826d8753 100644
--- a/.mailmap
On Fri, 1 Mar 2019 at 18:28, Mark Rutland wrote:
>
> On Thu, Feb 28, 2019 at 02:59:17PM +0100, Ulf Hansson wrote:
> > Instead of iterating through all the state nodes in DT, to find out how
> > many states that needs to be allocated, let's use the number already known
> > by the cpuidle driver. In
git tree, please drop us a note to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Yifeng-Li/Preliminary-Platform-Driver-Support-for-Lemote-Yeeloong-Laptops/20190304-005203
> config: powerpc-allyesconfig (attached as .config)
> compiler: power
On Fri, 01 Mar 2019, Andrew Morton wrote:
> On Fri, 1 Mar 2019 14:52:07 +0200 Jani Nikula wrote:
>
>> While is_power_of_2() is an inline function and likely gets optimized
>> for compile time constant arguments, it still doesn't produce an integer
>> constant expression that could be used in, sa
On Mon, Mar 04, 2019 at 08:25:28AM +, Haibo Xu (Arm Technology China) wrote:
> On 2019/3/1 2:32, Sudeep Holla wrote:
> > Now that we have a new hook ptrace_syscall_enter that can be called from
> > syscall entry code and it handles PTRACE_SYSEMU in generic code, we
> > can do some cleanup using
On Fri, Mar 01, 2019 at 06:44:57PM -0800, Fenghua Yu wrote:
> A bit in reg_ch_conf_pending in wl271 and tmp_ch_bitmap is set atomically
> by set_bit(). set_bit() sets the bit in a single unsigned long location. If
> the variables are not aligned to unsigned long, set_bit() accesses two
> cache line
On Sat, Mar 02, 2019 at 05:11:40PM -0800, Andy Lutomirski wrote:
> On Thu, Feb 28, 2019 at 10:32 AM Sudeep Holla wrote:
> >
> > Now that we have a new hook ptrace_syscall_enter that can be called from
> > syscall entry code and it handles PTRACE_SYSEMU in generic code, we
> > can do some cleanup u
On 25/02/2019 at 18:27, Alexandre Belloni wrote:
> From: Matthias Wieloch
>
> The prescaler formula of the programmable clock has changed for sama5d2.
> Update
> the driver accordingly. A new compatibility string is needed for this driver,
> now.
Actually, with new clk binding, a new compatibil
On Fri, Mar 01, 2019 at 12:52:21PM -0600, Jeremy Linton wrote:
> ACPI 6.3 bumps the PPTT table revision and adds a LEAF_NODE flag.
> This allows us to avoid a second pass through the table to assure
> that the node in question is a leaf.
>
Reviewed-by:Sudeep Holla
--
Regards,
Sudeep
> Signed-of
Switch to bitmap_zalloc() to show clearly what we are allocating.
Besides that it returns pointer of bitmap type instead of opaque void *.
Signed-off-by: Andy Shevchenko
---
lib/test_printf.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/test_printf.c b/lib/test_pri
On (03/04/19 16:38), Sergey Senozhatsky wrote:
> This, theoretically, creates a whole new world of possibilities for
> console drivers. Now they can do GFP_KERNEL allocations and stall
> printk_kthread during OOM; or they can explicitly reschedule from
> ->write() callback (via console_conditional_
On Fri, Mar 01, 2019 at 06:44:56PM -0800, Fenghua Yu wrote:
> A bit in pwol_mask is set in b44_magic_pattern automatically by set_bit.
> set_bit sets the bit in a single unsigned long location. Since pwol_mask
> may not be aligned to unsigned long, the location may cross two cache
> lines and acces
On Sun, Mar 3, 2019 at 11:42 PM Gabriele Mazzotta
wrote:
>
> Hi,
>
> I applied these patches on top of 4.20. The max frequency of all the
> cores now reflects the actual value and it's updated whenever I
> change the power source.
Thanks for the confirmation!
On Mon, Mar 4, 2019 at 12:17 AM Marek Behun wrote:
> do you know who is responsible for merging into drivers/bus?
Usually the ARM SoC maintainers a...@kernel.org merge drivers
there. You should just send them a pull request and explain the
situation I think. Else they know who should deal with i
Hi Paul,
Paul Cercueil wrote on Sat, 9 Feb 2019 16:22:58
-0300:
> The JZ4740 ECC hardware is not BCH but Reed-Solomon, so it makes more
> sense to use the more generic ECC term.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Changes:
>
> v3: New patch
>
> v4: No change
>
> .../devicetree/bin
On 04/03/2019 02:57, Halil Pasic wrote:
On Fri, 22 Feb 2019 16:29:58 +0100
Pierre Morel wrote:
We register the AP PQAP instruction hook during the open
of the mediated device. And unregister it on release.
In the AP PQAP instruction hook, if we receive a demand to
enable IRQs,
- we retrieve t
Hi Paul,
Paul Cercueil wrote on Sat, 9 Feb 2019 16:22:57
-0300:
> Add compatible strings to probe the jz4780-nand and jz4780-bch drivers
> from devicetree on the JZ4725B and JZ4740 SoCs from Ingenic.
>
> Signed-off-by: Paul Cercueil
> ---
>
> Changes:
>
> v2: - Change 'ingenic,jz4725b-nand'
On Mon, Mar 04, 2019 at 10:03:27AM +0100, Marek Szyprowski wrote:
> Hi Greg,
>
> On 2019-03-04 09:53, Greg Kroah-Hartman wrote:
> > On Mon, Mar 04, 2019 at 08:46:30AM +, He, Bo wrote:
> >> Hi, Greg:
> >>Marek Szyprowski report the patch has issue that calling
> >> synchronize_irq() under
Hi Naga,
Naga Sureshkumar Relli wrote on
Sat, 9 Feb 2019 12:07:27 +0530:
> Add driver for arm pl353 static memory controller nand interface with
> HW ECC support. This controller is used in Xilinx Zynq SoC for
> interfacing the NAND flash memory.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
On 26.02.2019 20:36, Andrey Smirnov wrote:
> Drop the use of tc_write() as well as "magicly" used "ret" and "err:"
> and replace it with a simple call to regmap_write(). No functional
> change intended.
>
> Signed-off-by: Andrey Smirnov
> Cc: Archit Taneja
> Cc: Andrzej Hajda
> Cc: Laurent Pinch
On Mon, Mar 4, 2019 at 5:06 AM Srinivas Pandruvada
wrote:
>
> On Sun, 2019-03-03 at 22:51 +0100, Rafael J. Wysocki wrote:
> > On Sun, Mar 3, 2019 at 10:20 PM Srinivas Pandruvada
> > wrote:
> > >
> > > On Sun, 2019-03-03 at 18:03 +0100, Rafael J. Wysocki wrote:
> > > > On Fri, Mar 1, 2019 at 6:39
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