On Mon, May 20, 2019 at 04:19:35PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier
>
> Change the assembly code to use only relative references of symbols for the
> kernel to be PIE compatible.
>
> Position Independent Executable (PIE) support will allow to extend the
> KASLR randomization
On Wed, May 29, 2019 at 04:31:01PM -0700, Mike Kravetz wrote:
> On 5/28/19 2:49 AM, Wanpeng Li wrote:
> > Cc Paolo,
> > Hi all,
> > On Wed, 14 Feb 2018 at 06:34, Mike Kravetz wrote:
> >>
> >> On 02/12/2018 06:48 PM, Michael Ellerman wrote:
> >>> Andrew Morton writes:
> >>>
> On Thu, 08 Feb
From: Greg Hackmann
By traversing /proc/*/fd and /proc/*/map_files, processes with CAP_ADMIN
can get a lot of fine-grained data about how shmem buffers are shared
among processes. stat(2) on each entry gives the caller a unique
ID (st_ino), the buffer's size (st_size), and even the number of
On Mon, May 20, 2019 at 04:19:33PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier
>
> Change the assembly code to use only relative references of symbols for the
> kernel to be PIE compatible.
>
> Position Independent Executable (PIE) support will allow to extend the
> KASLR randomization
From: Doug Anderson
This enables wake up on Bluetooth activity when the device is
suspended. The BT_HOST_WAKE signal is only connected on devices
with BT module that are connected through UART.
Signed-off-by: Douglas Anderson
Signed-off-by: Matthias Kaehlcke
---
Changes in v2:
- attributed
On Sun, Oct 07, 2018 at 09:39:18PM +0200, Alexandre Belloni wrote:
> Hi,
>
> On 07/10/2018 14:18:31+0200, Dmitry Vyukov wrote:
> > On Sun, Oct 7, 2018 at 2:15 PM, syzbot
> > wrote:
> > > Hello,
> > >
> > > syzbot found the following crash on:
> > >
> > > HEAD commit:c1d84a1b42ef Merge
> > >
Currently, intel_pt_process_auxtrace_info() sets synth_opts.callchain for
use_browser != -1, which is not accurate after we set use_browser to 0 in
cmd_script(). As a result, the following commands sees a lot more errors
like:
perf record -e intel_pt//u -C 10 -- sleep 3
perf script
...
On Sat, May 25, 2019 at 11:17 AM Yangtao Li wrote:
>
> This patch adds the support for allwinner thermal sensor, within
> allwinner SoC. It will register sensors for thermal framework
> and use device tree to bind cooling device.
Hi Yangtao,
Any plans on v4 of this series?
> Signed-off-by:
Quoting Vivek Gautam (2019-06-06 04:17:16)
> Hi Stephen,
>
> On Thu, Jun 6, 2019 at 2:27 AM Stephen Boyd wrote:
> >
> > Quoting Vivek Gautam (2019-06-04 21:55:26)
> >
> > >
> > > Cheza will throw faults for anything that is programmed with TZ on mtp
> > > as all of that should be handled in
This is to officially inform you that ATM card number: 3774 2856 7847
9006 worth fifteen Million US dollars($15. Million US dollars.) has
been credited in your favor in bid to compensate you on your contract
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This is to officially inform you that ATM card number: 3774 2856 7847
9006 worth fifteen Million US dollars($15. Million US dollars.) has
been credited in your favor in bid to compensate you on your contract
payment since you are next on our inheritance file for the second part
of this fiscal
This is to officially inform you that ATM card number: 3774 2856 7847
9006 worth fifteen Million US dollars($15. Million US dollars.) has
been credited in your favor in bid to compensate you on your contract
payment since you are next on our inheritance file for the second part
of this fiscal
This is to officially inform you that ATM card number: 3774 2856 7847
9006 worth fifteen Million US dollars($15. Million US dollars.) has
been credited in your favor in bid to compensate you on your contract
payment since you are next on our inheritance file for the second part
of this fiscal
This is to officially inform you that ATM card number: 3774 2856 7847
9006 worth fifteen Million US dollars($15. Million US dollars.) has
been credited in your favor in bid to compensate you on your contract
payment since you are next on our inheritance file for the second part
of this fiscal
This is just an example code and I'm not actually trying to get this
merged.
Bjorn,
This is what the code would look like. It compiles, but I can't test it.
I'm not sending this as part of the patch series as I'm not sure what
the interconnects property should be set to in DT for qcom-rng device
On Mon, Jun 10, 2019 at 02:20:33PM -0700, Andrew Morton wrote:
> On Mon, 10 Jun 2019 17:18:05 +0900 Naoya Horiguchi
> wrote:
>
> > The pass/fail of soft offline should be judged by checking whether the
> > raw error page was finally contained or not (i.e. the result of
> >
On Mon, 2019-06-10 at 10:49 +0300, Konstantin Khlebnikov wrote:
> On 10.06.2019 0:37, James Bottomley wrote:
> > On Sat, 2019-06-08 at 17:13 +0300, Konstantin Khlebnikov wrote:
> > > > On 08.06.2019 11:25, Christoph Hellwig wrote:> On Fri, Jun 07,
> > > > 2019
> > > > at 10:34:39AM +0300,
--
Dear Friend,
I am Mrs Clara David. am sending you this brief letter to solicit your
partnership to transfer $18.5 million US Dollars.I shall send you more
information and procedures when I receive positive response from you.
please send me a message in my Email box (mrsclarad...@gmail.com)
Recently usfbs gained availability to retrieve device speed, but there
is sill no way to determine the bus number or list of ports the device
is connected to when using usbfs. While this information can be obtained
from sysfs, not all environments allow sysfs access. In a jailed
environment a
Hi Rob,
Commit
4713b5d95035 ("dt-bindings: vendor: Add a bunch of vendors")
is missing a Signed-off-by from its committer.
--
Cheers,
Stephen Rothwell
pgpY5Jndfex4s.pgp
Description: OpenPGP digital signature
On Mon, May 13, 2019 at 02:32:43PM -0700, Kees Cook wrote:
> On Sat, May 11, 2019 at 09:11:42PM -0700, Matthew Wilcox wrote:
> > On Sat, May 11, 2019 at 05:03:08PM -0700, Kees Cook wrote:
> > > On Fri, May 10, 2019 at 08:41:43PM -0400, Laura Abbott wrote:
> > > > On 5/10/19 3:43 PM, Kees Cook
On 6/10/19 3:03 PM, Florian Fainelli wrote:
> On 6/10/19 2:51 PM, Andrew Morton wrote:
>> On Fri, 7 Jun 2019 16:43:31 -0700 Florian Fainelli
>> wrote:
>>
>>> With architectures allowing the kernel to be placed almost arbitrarily
>>> in memory (e.g.: ARM64), it is possible to have the kernel
> From: Andy Lutomirski [mailto:l...@kernel.org]
> Sent: Monday, June 10, 2019 12:15 PM
>
> On Mon, Jun 10, 2019 at 11:29 AM Xing, Cedric
> wrote:
> >
> > > From: Christopherson, Sean J
> > > Sent: Wednesday, June 05, 2019 7:12 PM
> > >
> > > +/**
> > > + * sgx_map_allowed - check vma
On Mon, May 20, 2019 at 04:19:34PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier
>
> Change the assembly code to use only relative references of symbols for the
> kernel to be PIE compatible.
>
> Early at boot, the kernel is mapped at a temporary address while preparing
> the page table.
Quoting Evan Green (2019-05-30 10:12:03)
> On Wed, May 15, 2019 at 1:05 AM Nicolas Boichat wrote:
> >
> > On Wed, May 15, 2019 at 4:14 AM Stephen Boyd wrote:
> >
> > > We could immediately unmask those lines in the hardware when the
> > > set_wake() callback is called. That way the genirq layer
This prepare for adding native non-SBI IPI code.
Signed-off-by: Christoph Hellwig
---
arch/riscv/kernel/smp.c | 55 +++--
1 file changed, 31 insertions(+), 24 deletions(-)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index
From: Damien Le Moal
Do not allow selecting SBI related options with MMU option not set.
Signed-off-by: Damien Le Moal
Signed-off-by: Christoph Hellwig
---
drivers/tty/hvc/Kconfig| 2 +-
drivers/tty/serial/Kconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
The RISC-V ISA only supports flushing the instruction cache for the local
CPU core. For normal S-mode Linux remote flushing is offloaded to
machine mode using ecalls, but for M-mode Linux we'll have to do it
ourselves. Use the same implementation as all the existing open source
SBI
Only call the SBI code if we are not running in M mode, and if we didn't
do the SBI call, or it didn't succeed call wfi in a loop to at least
save some power.
Signed-off-by: Christoph Hellwig
---
arch/riscv/kernel/reset.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
RISC-V has the concept of a cpu level interrupt controller. Part of it
is expose as bits in the status registers, and 2 new CSRs per privilege
level in the instruction set, but the machanisms to trigger IPIs and
timer events, as well as reading the actual timer value are not
specified in the
Hi all,
below is a series to support nommu mode on RISC-V. For now this series
just works under qemu with the qemu-virt platform, but Damien has also
been able to get kernel based on this tree with additional driver hacks
to work on the Kendryte KD210, but that will take a while to cleanup
an
From: Damien Le Moal
When in M-Mode, we can use the mhartid CSR to get the ID of the running
HART. Doing so, direct M-Mode boot without firmware is possible.
Signed-off-by: Damien Le Moal
---
arch/riscv/kernel/head.S | 8
1 file changed, 8 insertions(+)
diff --git
The kernel runs in M-mode without using page tables, and thus doesn't
can run bare metal without help from additional firmware.
Most of the patch is just stubbing out code not needed without page
tables, but there is an interesting detail in the signals implementation:
- The normal RISC-V
This allows just loading the kernel at a pre-set address without
qemu going bonkers trying to map the ELF file.
Signed-off-by: Christoph Hellwig
---
arch/riscv/Makefile| 13 +
arch/riscv/boot/Makefile | 7 ++-
arch/riscv/boot/loader.S | 8
Signed-off-by: Christoph Hellwig
---
include/linux/mm.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index dd0b5f4e1e45..69843ee0c5f8 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -2756,7 +2756,13 @@ extern int
When running in M-mode we still the S-mode plic handlers in the DT.
Ignore them by setting the maximum threshold.
Signed-off-by: Christoph Hellwig
---
drivers/irqchip/irq-sifive-plic.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git
There is no SBI when we run in M-mode, so fail the compile for any code
trying to use SBI calls.
Signed-off-by: Christoph Hellwig
---
arch/riscv/include/asm/sbi.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
We can't expose UAPI symbols differently based on CONFIG_ symbols, as
userspace won't have them available. Instead always define the flag,
but only repsect it based on the config option.
Signed-off-by: Christoph Hellwig
---
arch/xtensa/include/uapi/asm/mman.h| 6 +-
Many of the privileged CSRs exist in a supervisor and machine version
that are used very similarly. Provide a new X-naming layer so that
we don't have to ifdef everywhere for M-mode Linux support.
Contains contributions from Damien Le Moal .
Signed-off-by: Christoph Hellwig
---
The numerical levels for External/Timer/Software interrupts differ
between S-mode and M-mode.
Signed-off-by: Christoph Hellwig
---
arch/riscv/kernel/irq.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index
The whole header file deals with swap entries and PTEs, none of which
can exist for nommu builds.
Signed-off-by: Christoph Hellwig
---
include/linux/swapops.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/linux/swapops.h b/include/linux/swapops.h
index
Switch to our own constant for the satp register instead of using
the old name from a legacy version of the privileged spec.
Signed-off-by: Christoph Hellwig
---
arch/riscv/mm/context.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/riscv/mm/context.c
When we get booted we want a clear slate without any leaks from previous
supervisors or the firmware. Flush the instruction cache and then clear
all registers to known good values. This is really important for the
upcoming nommu support that runs on M-mode, but can't really harm when
running in
On 3/13/2019 9:36 PM, Alexandre Bailon wrote:
>
> This adds support of i.MX SoC to interconnect framework.
> This is based on busfreq, from NXP's tree.
> This is is generic enough to be used to add support of interconnect
> framework to any i.MX SoC, and, even, this could used for some other
>
On Thu, May 30, 2019 at 9:53 PM Alex Elder wrote:
>
> Add the binding definitions for the "qcom,ipa" device tree node.
>
> Signed-off-by: Alex Elder
> ---
> .../devicetree/bindings/net/qcom,ipa.yaml | 180 ++
> 1 file changed, 180 insertions(+)
> create mode 100644
> From: Christopherson, Sean J
> Sent: Monday, June 10, 2019 12:50 PM
>
> On Mon, Jun 10, 2019 at 10:47:52AM -0700, Xing, Cedric wrote:
> > > From: Christopherson, Sean J
> > > Sent: Monday, June 10, 2019 8:56 AM
> > >
> > > > > As a result, LSM policies cannot be meaningfully applied, e.g.
> > >
On 6/10/19 2:51 PM, Andrew Morton wrote:
> On Fri, 7 Jun 2019 16:43:31 -0700 Florian Fainelli
> wrote:
>
>> With architectures allowing the kernel to be placed almost arbitrarily
>> in memory (e.g.: ARM64), it is possible to have the kernel resides at
>> physical addresses above 4GB, resulting
From: Vadim Sukhomlinov
TPM 2.0 Shutdown involve sending TPM2_Shutdown to TPM chip and disabling
future TPM operations. TPM 1.2 behavior was different, future TPM
operations weren't disabled, causing rare issues. This patch ensures
that future TPM operations are disabled.
Signed-off-by: Vadim
On 6/9/19 10:41 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 5.1.9 release.
There are 70 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On Fri, May 31, 2019 at 12:39 AM Manivannan Sadhasivam
wrote:
>
> This commit documents Avenger96 devicetree binding based on
> STM32MP157 SoC.
>
> Signed-off-by: Manivannan Sadhasivam
> ---
> Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 ++
> 1 file changed, 2 insertions(+)
On Fri, May 31, 2019 at 12:39 AM Manivannan Sadhasivam
wrote:
>
> This commit converts STM32 SoC bindings to DT schema using jsonschema.
>
> Signed-off-by: Manivannan Sadhasivam
> ---
> .../devicetree/bindings/arm/stm32/stm32.yaml | 29 +++
> 1 file changed, 29 insertions(+)
>
On 6/9/19 10:41 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.19.50 release.
There are 51 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On 6/9/19 10:42 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.14.125 release.
There are 35 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On 6/10/19 11:57 AM, Asmaa Mnebhi wrote:
> Support receiving IPMB requests on a Satellite MC from the BMC.
> Once a response is ready, this driver will send back a response
> to the BMC via the IPMB channel.
>
> Signed-off-by: Asmaa Mnebhi
> Acked-by: vad...@mellanox.com
> ---
>
On Mon, Jun 10, 2019 at 11:02:27PM +0200, Enric Balletbo i Serra wrote:
> Hi Matthias,
>
> On 10/6/19 22:39, Matthias Kaehlcke wrote:
> > Hi Enric
> >
> > On Mon, Jun 10, 2019 at 12:00:02PM +0200, Enric Balletbo i Serra wrote:
> >> Hi Matthias,
> >>
> >> On 8/6/19 23:02, Pavel Machek wrote:
>
On Fri, 7 Jun 2019 16:43:31 -0700 Florian Fainelli
wrote:
> With architectures allowing the kernel to be placed almost arbitrarily
> in memory (e.g.: ARM64), it is possible to have the kernel resides at
> physical addresses above 4GB, resulting in neither the default CMA area,
> nor the atomic
Hi,
On Sun, May 26, 2019 at 06:19:00AM -0300, Alexandre Oliva wrote:
> On Mar 8, 2019, "Maciej W. Rozycki" wrote:
>
> > Anyway I meant: does `war_io_reorder_wmb' expand to `wmb' on your system?
>
> No, it expands to `barrier' on the yeeloong:
>
> CONFIG_CPU_LOONGSON2F=y
>
On 6/9/19 10:41 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.9.181 release.
There are 83 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be made
On Sun, Jun 2, 2019 at 2:01 AM Paul Walmsley wrote:
>
> At Rob's request, we're starting to migrate our DT binding
> documentation to json-schema YAML format. Start by converting our cpu
> binding documentation. While doing so, document more properties and
> nodes. This includes adding binding
On 6/9/19 10:39 AM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 4.4.181 release.
There are 241 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On Sun, Jun 2, 2019 at 2:05 AM Paul Walmsley wrote:
>
> Add YAML DT binding documentation for the SiFive FU540 SoC. This
> SoC is documented at:
>
> https://static.dev.sifive.com/FU540-C000-v1.0.pdf
>
> Passes dt-doc-validate, as of yaml-bindings commit 4c79d42e9216.
>
> This second version
On Sun, Jun 2, 2019 at 7:26 PM wrote:
>
> From: Anson Huang
>
> This patch adds the soc & board binding for i.MX8MN.
>
> Signed-off-by: Anson Huang
> ---
> No changes.
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++
> 1 file changed, 6 insertions(+)
Reviewed-by: Rob Herring
On Mon, May 20, 2019 at 04:19:31PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier
>
> Change assembly to use the new _ASM_MOVABS macro instead of _ASM_MOV for
> the assembly to be PIE compatible.
>
> Position Independent Executable (PIE) support will allow to extend the
> KASLR
On Mon, May 20, 2019 at 04:19:25PM -0700, Thomas Garnier wrote:
> Splitting the previous serie in two. This part contains assembly code
> changes required for PIE but without any direct dependencies with the
> rest of the patchset.
Thanks for doing this! It should be easier to land the "little"
On Mon, May 20, 2019 at 04:19:30PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier
>
> Change the assembly code to use only relative references of symbols for the
> kernel to be PIE compatible.
>
> Position Independent Executable (PIE) support will allow to extend the
> KASLR randomization
This fixes an issue in which key down events for function keys would be
repeatedly emitted even after the user has raised the physical key. For
example, the driver fails to emit the F5 key up event when going through
the following steps:
- fnmode=1: hold FN, hold F5, release FN, release F5
-
On Mon, May 20, 2019 at 04:19:29PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier
>
> Change the assembly code to use only absolute references of symbols for the
> kernel to be PIE compatible.
>
> Position Independent Executable (PIE) support will allow to extend the
> KASLR randomization
On Tue, 2019-05-28 at 14:44 +0800, Yang Shi wrote:
> The commit 9092c71bb724 ("mm: use sc->priority for slab shrink
> targets")
> has broken up the relationship between sc->nr_scanned and slab
> pressure.
> The sc->nr_scanned can't double slab pressure anymore. So, it sounds
> no
> sense to still
On Mon, 10 Jun 2019 13:45:02 +0100
Jean-Philippe Brucker wrote:
> On 07/06/2019 18:43, Jacob Pan wrote:
> >>> So it seems we agree on the following:
> >>> - iommu_unregister_device_fault_handler() will never fail
> >>> - iommu driver cleans up all pending faults when handler is
> >>>
On Wed, 05 Jun, at 08:00:35PM, Peter Zijlstra wrote:
>
> And then we had two magic values :/
>
> Should we not 'fix' RECLAIM_DISTANCE for EPYC or something? Because
> surely, if we want to load-balance agressively over 30, then so too
> should we do node_reclaim() I'm thikning.
Yeah we can fix
Currently, the /proc/sys/net/bridge folder is only created in the initial
network namespace. This patch ensures that the /proc/sys/net/bridge folder
is available in each network namespace if the module is loaded and
disappears from all network namespaces when the module is unloaded.
In doing so
syzbot writes:
> syzbot has bisected this bug to:
>
> commit e9db4ef6bf4ca9894bb324c76e01b8f1a16b2650
> Author: John Fastabend
> Date: Sat Jun 30 13:17:47 2018 +
>
> bpf: sockhash fix omitted bucket lock in sock_close
>
> bisection log:
Hey everyone,
/* v2 */
Split into two patches (cf. [4]):
1/2: replace #define with static inline helpers
2/2: namespace syscals
/* v1 */
This is a rework of the patch to not touch struct net at all and instead
rely on the pernet infrastructure directly to namespace the sysctls.
/* v0 */
This is
One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct tp_probes {
...
struct tracepoint_func probes[0];
};
instance
On Mon, 10 Jun 2019 17:18:05 +0900 Naoya Horiguchi
wrote:
> The pass/fail of soft offline should be judged by checking whether the
> raw error page was finally contained or not (i.e. the result of
> set_hwpoison_free_buddy_page()), but current code do not work like that.
> So this patch is
The split between the two flat.h files is completely arbitrary, and the
uapi version even contains CONFIG_ ifdefs that can't work in userspace.
The only userspace program known to use the header is elf2flt, and it
ships with its own version of the combined header.
Use the chance to move the
Ever since the initial commit of the binfmt_flat shared library
support back in the bitkeeper days we've offset the actual in-memory
.data start by one field per possible shared library, or 1 in case
shared library support isn't enabled. I can't find anything in the
loader that actually makes use
Oleg Nesterov writes:
> On 06/07, Eric W. Biederman wrote:
>>
>> +static int set_sigmask(sigset_t *kmask)
>> +{
>> +set_restore_sigmask();
>> +current->saved_sigmask = current->blocked;
>> +set_current_blocked(kmask);
>> +
>> +return 0;
>> +}
>
> I was going to do the same change
Use the generic support with arguments are on the stack. Same as arm
and m68k.
Signed-off-by: Christoph Hellwig
---
arch/riscv/Kconfig| 2 ++
arch/riscv/include/asm/Kbuild | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index
MAX_SHARED_LIBS is an implementation detail of the kernel loader,
and should be kept away from the file format definition.
Signed-off-by: Christoph Hellwig
---
fs/binfmt_flat.c | 6 ++
include/linux/flat.h | 6 --
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git
No need to carry the extra code around, given that systems using flat
binaries are generally very resource constrained.
Signed-off-by: Christoph Hellwig
---
fs/Kconfig.binfmt | 7 +++
fs/binfmt_flat.c | 29 +
2 files changed, 28 insertions(+), 8 deletions(-)
Instead add a Kconfig variable that only h8300 selects.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/flat.h| 1 -
arch/c6x/include/asm/flat.h| 1 -
arch/h8300/Kconfig | 1 +
arch/h8300/include/asm/flat.h | 1 -
arch/m68k/include/asm/flat.h
The argument is never used.
Signed-off-by: Christoph Hellwig
---
arch/c6x/include/asm/flat.h| 2 +-
arch/h8300/include/asm/flat.h | 2 +-
arch/microblaze/include/asm/flat.h | 2 +-
arch/sh/include/asm/flat.h | 2 +-
arch/xtensa/include/asm/flat.h | 2 +-
This file implements the flat get/put reloc helpers for architectures
that do not need to overload the relocs by simply using get_user/put_user.
Note that many nommu architectures currently use {get,put}_unaligned, which
looks a little bogus and should probably later be switched over to this
Hi Greg,
below is a larger stash of cleanups for the binfmt_misc code,
preparing for the last patch that now trivially adds RISC-V
support, which will be used for the RISC-V nommu series I am
about to post.
Allow architectures to opt into ARCH_HAS_BINFMT_FLAT support instead of
assuming that all nommu ports support the format.
Signed-off-by: Christoph Hellwig
---
arch/arm/Kconfig| 1 +
arch/c6x/Kconfig| 1 +
arch/h8300/Kconfig | 1 +
arch/m68k/Kconfig | 1 +
This will eventually allow us to kill the need for an for
many cases.
Signed-off-by: Christoph Hellwig
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/flat.h| 2 --
arch/c6x/include/asm/flat.h| 1 -
arch/h8300/Kconfig | 1 +
This way only the two architectures that do masking need to provide
the helper.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/flat.h| 2 --
arch/c6x/include/asm/flat.h| 1 -
arch/m68k/include/asm/flat.h | 1 -
arch/sh/include/asm/flat.h | 1 -
Most binfmt_flat on-disk fields are big endian. Use the proper __be32
type where applicable.
Signed-off-by: Christoph Hellwig
---
fs/binfmt_flat.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/fs/binfmt_flat.c b/fs/binfmt_flat.c
index
So far binfmt_flat has onl been supported on 32-bit platforms, so the
variable size of the fields didn't matter. But the upcoming RISC-V
nommu port supports 64-bit CPUs, and we now have a conflict between
the elf2flt creation tool that always uses 32-bit fields and the kernel
that uses (unsigned)
This helper is a no-op on all architectures, remove it.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/flat.h| 1 -
arch/c6x/include/asm/flat.h| 1 -
arch/h8300/include/asm/flat.h | 1 -
arch/m68k/include/asm/flat.h | 5 -
This helper is the same for all architectures, open code it in the only
caller.
Signed-off-by: Christoph Hellwig
---
arch/arm/include/asm/flat.h| 1 -
arch/c6x/include/asm/flat.h| 1 -
arch/h8300/include/asm/flat.h | 1 -
arch/m68k/include/asm/flat.h | 1 -
On 6/9/19 3:56 PM, Arseny Maslennikov wrote:
> This is similar to SIGWINCH, which is default-ignored as well: if the
> terminal width/height changes (like when a terminal emulator window is
> resized), its foreground pgrp gets a surprise signal as well, and the
> processes that don't care about
On Mon, Jun 10, 2019 at 12:31:49PM -0700, Florian Fainelli wrote:
> We need to specifically deal with phylink_of_phy_connect() returning
> -ENODEV, because this can happen when a CPU/DSA port does connect
> neither to a PHY, nor has a fixed-link property. This is a valid use
> case that is
On Mon 10-06-19 20:21:12, Minchan Kim wrote:
[...]
> >From 5cb8958ea240e2580bd2b331448009e8e1854240 Mon Sep 17 00:00:00 2001
> From: Minchan Kim
> Date: Fri, 24 May 2019 15:54:10 +0900
> Subject: [PATCH] mm: fix trying to reclaim unevicable LRU page
>
> There was below bugreport from Wu Fangsuo.
On Sat, May 25, 2019 at 3:37 PM Steven Rostedt wrote:
> Hi Cong,
>
> Thanks for sending these patches, but I just want to let you know that
> it's currently a US holiday, and then afterward I'll be doing quite a
> bit of traveling for the next two weeks. If you don't hear from me in
> after two
> Hi Florian,
>
> Can you give an example of when this is a valid use case, and why
> fixed-link is not appropriate?
A DSA link is used to connect two switches together. ZII devel b and c
are two boards which does this. Such links have the MACs connected
back to back, no PHYs involved. You can
On Tue, Jun 11, 2019 at 2:47 AM Greg Kroah-Hartman
wrote:
>
> On Wed, Jun 05, 2019 at 02:44:12AM +0900, Masahiro Yamada wrote:
> > This function never attempts to allocate memory, so returning -ENOMEM
> > looks weird to me. The reason of the failure is there is no more space
> > in the given
This function never attempts to allocate memory, so returning -ENOMEM
looks weird to me. The reason of the failure is there is no more space
in the given kobj_uevent_env structure.
Let's change the error code to -ENOSPC.
This patch is safe since this function had never failed in reality.
The
On 6/5/19 3:19 AM, Arseny Maslennikov wrote:
> This complementary patch defines SIGINFO as a synonym for SIGPWR
> on every architecture supported by the kernel.
> The particular signal number chosen does not really matter and is only
> required for the related tty functionality to work properly,
>
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