Hi Eduardo,
thanks for stepping up and pushing this further!
On Wed, Jun 05, 2019 at 09:46:50AM -0700, Eduardo Valentin wrote:
> From: Haiyue Wang
>
> Some protocols over I2C are designed for bi-directional transferring
> messages by using I2C Master Write protocol. Like the MCTP (Management
>
On Mon 27-05-19 13:11:45, David Hildenbrand wrote:
> A proper arch_remove_memory() implementation is on its way, which also
> cleanly removes page tables in arch_add_memory() in case something goes
> wrong.
>
> As we want to use arch_remove_memory() in case something goes wrong
> during memory
On Mon 01-07-19 09:45:03, Michal Hocko wrote:
> On Mon 27-05-19 13:11:44, David Hildenbrand wrote:
> > Will come in handy when wanting to handle errors after
> > arch_add_memory().
>
> I do not understand this. Why do you add a code for something that is
> not possible on this HW (based on the
On Mon 01-07-19 09:43:06, Michal Hocko wrote:
> On Mon 27-05-19 13:11:43, David Hildenbrand wrote:
> > ZONE_DEVICE is not yet supported, fail if an altmap is passed, so we
> > don't forget arch_add_memory()/arch_remove_memory() when unlocking
> > support.
>
> Why do we need this? Sure ZONE_DEVICE
> > +===
> > +Device Tree for I2C slave message queue backend
> > +===
> > +
> > +Some protocols over I2C/SMBus are designed for bi-directional transferring
> > +messages by using I2C Master Write protocol.
Hi Ted,
On Fri, May 17, 2019 at 6:44 PM Geert Uytterhoeven wrote:
> On Wed, May 15, 2019 at 6:57 AM Theodore Ts'o wrote:
> > Ah, I think I see the problem. Sorry, this one was my fault. Does
> > this fix things for you?
>
> Thanks!
> Sorry for missing this patch in the thread before.
>
> >
> Looks like the slave reg missed the key value bit:
>
>
> https://elinux.org/images/f/f6/ELCE15-WolframSang-ShinyNewI2CSlaveFramework.pdf
>
> Example: reg = <(I2C_OWN_SLAVE_ADDRESS | 0x42)>;
Yes.
signature.asc
Description: PGP signature
Hi all,
Changes since 20190628:
The dma-mapping tree gained a conflict against Linus' tree.
The xfs tree gained conflicts against the f2fs tree and a build failure
so I used the version from next-20190628.
The pm tree gained a conflict against the pci tree and a build failure,
so I used the
On 6/27/2019 8:08 PM, Lorenzo Pieralisi wrote:
On Mon, Jun 24, 2019 at 02:44:54PM +0530, Vidya Sagar wrote:
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar
Reviewed-by: Thierry Reding
---
Changes since [v10]:
* None
Changes since
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
For each PCIe lane of a controller, there is a P2U unit instantiated at
hardware level. This driver provides support for the programming required
for each
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
Acked-by: Thierry Reding
---
Changes since [v11]:
* None
Changes since [v10]:
* None
Changes since [v9]:
* Used _relaxed() versions of readl() & writel()
Changes since
Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
module instantiated one for each PCIe lane between Synopsys DesignWare core
based PCIe IP and Universal PHY block.
Signed-off-by: Vidya Sagar
Reviewed-by: Rob Herring
Acked-by: Thierry Reding
Acked-by: Kishon Vijay
Add support for Tegra194 PCIe controllers. These controllers are based
on Synopsys DesignWare core IP.
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
t=1561984897; bh=SatwB927mzd7rncXv8QPKhwoP5yCvHNiedxQcFowAP0=;
Some host controllers need to know the existence of clkreq signal routing to
downstream devices to be able to advertise low power features like ASPM L1
substates. Without clkreq signal routing being present, enabling ASPM L1 sub
states might lead to downstream devices falling off the bus. Hence a
Add support to enable CDM (Configuration Dependent Module) register check
for any data corruption based on the device-tree flag 'snps,enable-cdm-check'.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Reviewed-by: Thierry Reding
---
Changes since [v11]:
* None
Changes since [v10]:
*
Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Reviewed-by: Thierry Reding
---
Changes since [v11]:
* None
Changes since [v10]:
* None
Changes since [v9]:
* None
Tegra PCIe rootports don't generate MSI interrupts for PME and AER events.
Since PCIe spec (Ref: r4.0 sec 7.7.1.2 and 7.7.2.2) doesn't support using
a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports
service drivers registering their respective ISRs with MSI interrupt and
to
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar
Reviewed-by: Thierry Reding
---
Changes since [v11]:
* None
Changes since [v10]:
* None
Changes since [v9]:
* None
Changes since [v8]:
* None
Changes since [v7]:
* None
Changes
Some of DesignWare core's DBI registers (a.k.a configuration space
registers) are write-protected with a lock without enabling which they are
read-only by default. These write-protected registers are implementation
specific. Tegra194's BAR-0 register which is at offset 0x10 in the
configuration
Add extended configuration space capability search API using struct dw_pcie *
pointer
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Acked-by: Thierry Reding
---
Changes since [v11]:
* None
Changes since [v10]:
* None
Changes since [v9]:
* None
Changes since [v8]:
* Added Acked-by
Hello,
syzbot found the following crash on:
HEAD commit:7829a896 usb-fuzzer: main usb gadget fuzzer driver
git tree: https://github.com/google/kasan.git usb-fuzzer
console output: https://syzkaller.appspot.com/x/log.txt?x=1092d175a0
kernel config:
Le lun. 1 juil. 2019 à 14:28, Miquel Raynal
a écrit :
Hi Paul,
One question below.
Paul Cercueil wrote on Sat, 29 Jun 2019
03:22:48
+0200:
If MTD_NAND_JZ4780 is y and MTD_NAND_JZ4780_BCH is m,
which select CONFIG_MTD_NAND_INGENIC_ECC to m, building fails:
Hi Paul,
One question below.
Paul Cercueil wrote on Sat, 29 Jun 2019 03:22:48
+0200:
> If MTD_NAND_JZ4780 is y and MTD_NAND_JZ4780_BCH is m,
> which select CONFIG_MTD_NAND_INGENIC_ECC to m, building fails:
>
> drivers/mtd/nand/raw/ingenic/ingenic_nand.o: In function
> `ingenic_nand_remove':
On Mon, Jun 24, 2019 at 01:17:42PM -0700, Jacob Pan wrote:
> drivers/iommu/intel_irq_remapping.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Applied, thanks.
From: Wanpeng Li
Cache the busy housekeeping target for timer instead of researching each time.
This patch reduces the total time of get_nohz_timer_target() for busy
housekeeping
CPU from 2u~3us to less than 1us which can be observed by ftrace.
Cc: Ingo Molnar
Cc: Peter Zijlstra
Cc:
On 2019-07-01 00:04:15 [-0400], Joel Fernandes (Google) wrote:
> This reverts commit a6fda6dab93c2c06ef4b8cb4b9258df6674d2438 which
> causes kvm.sh to not run on my machines. The qemu-system-x86_64 command
> runs but does nothing.
Nope. I would like to know *why* you need 'noapic' to work. Is it
On Mon, Jul 1, 2019 at 6:15 AM Jose Abreu wrote:
>
> From: Willem de Bruijn
>
> > By the
> >
> > if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
> > stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
> > napi_schedule_irqoff(>rx_napi);
On Mon, Jul 01, 2019 at 12:24:42PM +0200, Sebastian Andrzej Siewior wrote:
> On 2019-07-01 11:42:15 [+0200], Peter Zijlstra wrote:
> > I'm not sure if smp_send_reschedule() can be used as self-IPI, some
> > hardware doesn't particularly like that IIRC. That is, hardware might
> > only have
On Thu, Jun 27, 2019 at 04:43:39PM +0200, Andrew Lunn wrote:
> On Thu, Jun 27, 2019 at 03:21:37PM +0200, Corentin Labbe wrote:
> > Hello
> >
> > I own an USB dongle which is a "Davicom DM96xx USB 10/100 Ethernet".
> > According to the CHIP_ID, it is a DM9620.
> >
> > Since I needed for bringing
On 2019-06-29 17:22:59 [+0200], Vegard Nossum wrote:
> The commit for this patch in mainline
> (ccb18db2ab9d923df07e7495123fe5fb02329713) causes the kernel to hang on
> boot when passing the "nofxsr" option:
as a result of nofxsr we do:
[0] setup_clear_cpu_cap(X86_FEATURE_FXSR);
[1]
syzbot has bisected this bug to:
commit e9db4ef6bf4ca9894bb324c76e01b8f1a16b2650
Author: John Fastabend
Date: Sat Jun 30 13:17:47 2018 +
bpf: sockhash fix omitted bucket lock in sock_close
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=17f7f4d5a0
start commit:
On 01/07/19 09:50, Li Wang wrote:
> Hello there,
>
> LTP/umip_basic_test get failed on KVM UMIP
> system(kernel-v5.2-rc4.x86_64). The test is only trying to do
> asm volatile("smsw %0\n" : "=m" (val));
> and expect to get SIGSEGV in this SMSW operation, but it exits with 0
> unexpectedly.
On Tue, 21 May 2019 17:34:33 +0200
Pierre Morel wrote:
> This patch series implements PQAP/AQIC interception in KVM.
Thanks, applied
Enable the IR receiver controller on the SEI510 board.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
On 01/07/2019 13:55, Neil Armstrong wrote:
> Enable IR receiver controllera on the SEI510 board.
Damn typo s/controllera/controller/
Resending...
>
> Signed-off-by: Neil Armstrong
> ---
> arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 6 ++
> 1 file changed, 6 insertions(+)
>
>
Fix DST_FEATURE_ECN_CA to use "U" cast to avoid shifting signed
32-bit value by 31 bits problem.
Signed-off-by: Vandana BN
---
include/net/dst.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/net/dst.h b/include/net/dst.h
index 12b31c602cb0..095c5daf9403 100644
---
Enable IR receiver controllera on the SEI510 board.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
On Mon, Jul 01, 2019 at 07:24:23AM +, Sa, Nuno wrote:
> The problem is in spi_map_msg() which
> allocates dummy buffers (because of the ctrl flags). As a result, in
> bcm2835_spi_transfer_one() we set "cs |= BCM2835_SPI_CS_REN;" when we
> want to do tx only. I believe this was the actual
Fix an incomplete devm_clk_bulk_get_optional() function documentation
by adding description of the num_clks argument as in other *clk_bulk*
functions.
Fixes: 9bd5ef0bd874 ("clk: Add devm_clk_bulk_get_optional() function")
Reported-by: kbuild test robot
Signed-off-by: Sylwester Nawrocki
---
syzbot wrote:
> syzbot has bisected this bug to:
>
> commit 1548bc4e0512700cf757192c106b3a20ab639223
> Author: Florian Westphal
> Date: Fri Jan 4 13:17:02 2019 +
>
> xfrm: policy: delete inexact policies from inexact list on hash rebuild
I'm looking at this now.
Add basic dts support for a Advantech iMX8QM Qseven Board
Signed-off-by: Oliver Graute
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
.../boot/dts/freescale/imx8qm-rom7720-a1.dts | 221 ++
2 files changed, 222 insertions(+)
create mode 100644
By refactoring the command setup code, we can let the compiler
determine the size of each command.
Signed-off-by: Marc Gonzalez
---
drivers/media/dvb-frontends/si2168.c | 142 ---
1 file changed, 41 insertions(+), 101 deletions(-)
diff --git
On 6/25/19 7:27 PM, Aniket Masule wrote:
> Add vpp cycles for for different types of codec
> It indicates the cycles required by video hardware
> to process each macroblock. Initialize the codec
> data with core resources.
>
> Signed-off-by: Aniket Masule
> ---
>
On 6/27/19 5:32 PM, Doug Berger wrote:
A timing hazard exists when an early fork/exec thread begins
exiting and sets its mm pointer to NULL while a separate core
tries to update the section information.
This commit ensures that the mm pointer is not NULL before
setting its section parameters.
This patchset is ontop of Aisheng Dongs clock driver changes for the imx8qm
https://patchwork.kernel.org/cover/10824537/
This patchset is based on next-20190222
I need information about the status of the integration of the imx8qm clock
driver into mainline. Is this ongoing?
I need some hints
add gpio4 to imx8qm.dtsi
add gpio5 to imx8qm.dtsi
Signed-off-by: Oliver Graute
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index
I'm very skeptical about this approach.
On Sun, 30 Jun 2019 20:23:43 +0300
Ivan Khoronzhuk wrote:
> XDP rxqs can be same for ndevs running under same rx napi softirq.
> But there is no ability to register same allocator for both rxqs,
> by fact it can same rxq but has different ndev as a
syzbot has found a reproducer for the following crash on:
HEAD commit:41550654 [UPSTREAM] KVM: x86: degrade WARN to pr_warn_rate..
git tree: kmsan
console output: https://syzkaller.appspot.com/x/log.txt?x=1577f4d5a0
kernel config:
Below is the list of build error/warning regressions/improvements in
v5.2-rc7[1] compared to v5.1[2].
Summarized:
- build errors: +0/-0
- build warnings: +142/-115
JFYI, when comparing v5.2-rc7[1] to v5.2-rc6[3], the summaries are:
- build errors: +0/-0
- build warnings: +57/-60
Note
On 7/1/19 6:55 AM, Tetsuo Handa wrote:
Andrew, can you pick up this patch? No response from Laura Abbott nor Sumit
Semwal.
On 2019/06/21 18:58, Tetsuo Handa wrote:
From e0758655727044753399fb4f7c5f3eb25ac5cccd Mon Sep 17 00:00:00 2001
From: Tetsuo Handa
Date: Fri, 21 Jun 2019 11:22:51 +0900
The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.
This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.
Hi Rafael,
On 01-07-19 12:42, Rafael J. Wysocki wrote:
Hi All,
This series of patches addresses a few issues related to the handling of
hibernation in the PCI bus type and the ACPI PM domain and ACPI LPSS driver.
The v2 addresses Hans' concerns regarding the LPSS changes.
First of all, all
This patch introduces the min-frequency and max-frequency device
constraints, which will be used by the cpufreq core to begin with.
Reviewed-by: Matthias Kaehlcke
Reviewed-by: Ulf Hansson
Signed-off-by: Viresh Kumar
---
drivers/base/power/qos.c | 111 ++-
In order to allow dev_pm_qos_read_value() to read values for different
QoS requests, pass request type as a parameter to these routines.
For now, it only supports resume-latency request type but will be
extended to frequency limit (min/max) constraints later on.
Reviewed-by: Matthias Kaehlcke
The implementation of intel_pstate_update_max_freq() is quite similar to
refresh_frequency_limits(), lets reuse it.
Finding minimum of policy->user_policy.max and policy->cpuinfo.max_freq
in intel_pstate_update_max_freq() is redundant as cpufreq_set_policy()
will call the ->verify() callback of
This implements QoS requests to manage userspace configuration of min
and max frequency.
Reviewed-by: Matthias Kaehlcke
Reviewed-by: Ulf Hansson
Signed-off-by: Viresh Kumar
---
drivers/cpufreq/cpufreq.c | 87 ---
include/linux/cpufreq.h | 8 +---
2 files
This registers the notifiers for min/max frequency constraints with the
PM QoS framework. The constraints are also taken into consideration in
cpufreq_set_policy().
This also relocates cpufreq_policy_put_kobj() as it is required to be
called from cpufreq_policy_alloc() now.
Hello,
This patchset attempts to manage CPU frequency constraints using the PM
QoS framework. It only does the basic stuff right now and moves the
userspace constraints to use the QoS infrastructure.
Todo:
- Migrate all users to the QoS framework and get rid of cpufreq specific
notifiers.
-
dev_pm_qos_read_value() will soon need to support more constraint types
(min/max frequency) and will have another argument to it, i.e. type of
the constraint. While that is fine for the existing users of
dev_pm_qos_read_value(), but not that optimal for the callers of
__dev_pm_qos_read_value() and
In order to use the same set of routines to register notifiers for
different request types, update the existing
dev_pm_qos_{add|remove}_notifier() routines with an additional
parameter: request-type.
For now, it only supports resume-latency request type but will be
extended to frequency limit
Hi Lukas and Stefan,
On Fri, 2019-06-28 at 21:00 +0200, Lukas Wunner wrote:
>
> On Fri, Jun 28, 2019 at 05:23:54PM +0200, Stefan Wahren wrote:
> > Am 28.06.19 um 14:30 schrieb Nuno Sá:
> > > As stated in
> > > https://www.raspberrypi.org/documentation/hardware/raspberrypi/spi/README.md,
> > >
Hi Christoph,
On Fri, 28 Jun 2019 08:59:46 -0700
Christoph Hellwig wrote:
>I'd much rather bite the bullet and make dev->dma_mask a scalar
>instead of a pointer. The pointer causes way to much boiler plate code,
>and the semantics are way to subtile.
I agree that this the real solution, it
Alexander Shishkin writes:
> So far, we tried to disallow grouping exclusive events for the fear of
> complications they would cause with moving between contexts. Specifically,
> moving a software group to a hardware context would violate the exclusivity
> rules if both groups contain matching
On Mon, Jul 01, 2019 at 08:38:10AM +0100, David Howells wrote:
> Al Viro wrote:
>
> > /* The thing moved must be mounted... */
> > if (!is_mounted(old_path->mnt))
> > goto out;
>
> Um... Doesn't that stuff up fsmount()?
Nope - check is_mounted() definition. Stuff in anon
From: Markus Elfring
Date: Mon, 1 Jul 2019 13:07:55 +0200
A single character (depending on a condition check) should be put
into a sequence. Thus use the corresponding function “seq_putc”.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring
---
Am Mittwoch, den 26.06.2019, 10:38 -0400 schrieb Alan Stern:
> On Wed, 26 Jun 2019, Oliver Neukum wrote:
>
> > Am Montag, den 24.06.2019, 10:22 -0400 schrieb Alan Stern:
> > > But that pattern makes no sense; a driver would never use it. The
> > > driver would just do the reset itself.
> >
> >
Hi all,
After merging the hmm tree, today's linux-next build (x86_64 allmodconfig)
failed like this:
mm/hmm.c: In function 'hmm_get_or_create':
mm/hmm.c:50:2: error: implicit declaration of function
'lockdep_assert_held_exclusive'; did you mean 'lockdep_assert_held_once'?
On Mon, Jul 01, 2019 at 12:53:14PM +0200, Soeren Moch wrote:
> In contrast to the TX path, there is no need to separately read the transfer
> status from the device after receiving RX data. Consequently, there is no
> real STATUS_PENDING RX processing queue entry state.
> Remove the unnecessary
So far, we tried to disallow grouping exclusive events for the fear of
complications they would cause with moving between contexts. Specifically,
moving a software group to a hardware context would violate the exclusivity
rules if both groups contain matching exclusive events.
This attempt was,
On Mon, Jul 01, 2019 at 12:53:13PM +0200, Soeren Moch wrote:
> Since commit ed194d136769 ("usb: core: remove local_irq_save() around
> ->complete() handler") the handler rt2x00usb_interrupt_rxdone() is
> not running with interrupts disabled anymore. So this completion handler
> is not guaranteed
Hi,
Linux kernel recently got a bugfix 1fde6f21d90f ("proc: fix /proc/net/* after
setns(2)"),
but unfortunately it only solves the issue for procfs net file inodes so they
get correct
content after a process change namespace.
Checking on a v5.2-rc6 kernel :
sh-4.4# sh netns_procfs_test.sh
[
On Mon, Jul 01, 2019 at 12:49:50PM +0200, Soeren Moch wrote:
> Hello!
>
> On 29.06.19 10:50, Stanislaw Gruszka wrote:
> > Hello
> >
> > On Wed, Jun 26, 2019 at 03:28:00PM +0200, Soeren Moch wrote:
> >> Hi Stanislaw,
> >>
> >> the good news is: your patch below also solves the issue for me. But
>
So far, we tried to disallow grouping exclusive events for the fear of
complications they would cause with moving between contexts. Specifically,
moving a software group to a hardware context would violate the exclusivity
rules if both groups contain matching exclusive events.
This attempt was,
From: Rafael J. Wysocki
Remove a leftover function header and a static inline stub with no
users from the ACPI header file.
Signed-off-by: Rafael J. Wysocki
---
-> v2: No changes.
---
include/linux/acpi.h |2 --
1 file changed, 2 deletions(-)
Index: linux-pm/include/linux/acpi.h
From: Rafael J. Wysocki
First, after a previous change causing all runtime-suspended devices
in the ACPI PM domain (and ACPI LPSS devices) to be resumed before
creating a snapshot image of memory during hibernation, it is not
necessary to worry about the case in which them might be left in
From: Rafael J. Wysocki
Both the PCI bus type and the ACPI PM domain avoid resuming
runtime-suspended devices with DPM_FLAG_SMART_SUSPEND set during
hibernation (before creating the snapshot image of system memory),
but that turns out to be a mistake. It leads to functional issues
and adds
From: Rafael J. Wysocki
After a previous change causing all runtime-suspended PCI devices
to be resumed before creating a snapshot image of memory during
hibernation, it is not necessary to worry about the case in which
them might be left in runtime-suspend any more, so get rid of the
code
From: Rafael J. Wysocki
In general, it is not correct to call pm_generic_suspend(),
pm_generic_suspend_late() and pm_generic_suspend_noirq() during the
hibernation's "poweroff" transition, because device drivers may
provide special callbacks to be invoked then and the wrappers in
question cause
Andrew, can you pick up this patch? No response from Laura Abbott nor Sumit
Semwal.
On 2019/06/21 18:58, Tetsuo Handa wrote:
> From e0758655727044753399fb4f7c5f3eb25ac5cccd Mon Sep 17 00:00:00 2001
> From: Tetsuo Handa
> Date: Fri, 21 Jun 2019 11:22:51 +0900
> Subject: [PATCH] staging: android:
Since commit ed194d136769 ("usb: core: remove local_irq_save() around
->complete() handler") the handler rt2x00usb_interrupt_rxdone() is
not running with interrupts disabled anymore. So this completion handler
is not guaranteed to run completely before workqueue processing starts
for the same
In contrast to the TX path, there is no need to separately read the transfer
status from the device after receiving RX data. Consequently, there is no
real STATUS_PENDING RX processing queue entry state.
Remove the unnecessary ENTRY_DATA_STATUS_PENDING flag checks from the RX path.
Also remove the
mutexes can sleep and therefore should not be taken while holding a
spinlock. move clk_get_rate (can sleep) outside the spinlock protected
region.
This regression was introduced with commit
Date: Mon Nov 21 12:07:16 2016 +0530
mmc: sdhci-msm: Update DLL reset sequence
SDCC core
Andrew, can you pick up this patch? We might miss next merge window, for
Eric Biederman seems to be offline for two weeks.
On 2019/06/14 19:16, Tetsuo Handa wrote:
> syzbot found that a thread can stall for minutes inside kexec_load() after
> that thread was killed by SIGKILL [1]. It turned out
Hello!
On 29.06.19 10:50, Stanislaw Gruszka wrote:
> Hello
>
> On Wed, Jun 26, 2019 at 03:28:00PM +0200, Soeren Moch wrote:
>> Hi Stanislaw,
>>
>> the good news is: your patch below also solves the issue for me. But
>> removing the ENTRY_DATA_STATUS_PENDING check in
>> rt2x00usb_kick_rx_entry()
The new Amlogic SM1 SoC Family is a derivative of the Amlogic G12A
SoC Family, with the following changes :
- Cortex-A55 cores instead of A53
- more power domains, including USB & PCIe
- a neural network co-processor (NNA)
- a CSI input and image processor
- some changes in the audio complex, thus
Add the clk-measurer clocks IDs for the Amlogic SM1 SoC family.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/meson-clk-measure.c | 134
1 file changed, 134 insertions(+)
diff --git a/drivers/soc/amlogic/meson-clk-measure.c
Add the SoC IDs for the S905X3 Amlogic SM1 SoC.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-socinfo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c
b/drivers/soc/amlogic/meson-gx-socinfo.c
index bca34954518e..eb81d391b620 100644
Add bindings for the Amlogic SM1 Power control:
- the VPU power control compatible
- the general-purpose power controller, controlling the USB, PCIe, NNA and
GE2D power domains.
Signed-off-by: Neil Armstrong
---
.../bindings/power/amlogic,meson-gx-pwrc.txt | 35 +++
On 17/06/19 6:31 PM, Arnd Bergmann wrote:
> The irqchip driver depends on the SoC specific driver, but we want
> to be able to compile-test it elsewhere:
>
> WARNING: unmet direct dependencies detected for TI_SCI_INTA_MSI_DOMAIN
> Depends on [n]: SOC_TI [=n]
> Selected by [y]:
> -
Add support for the Amlogic SM1 SoC Family to the G12A AO-CECB
derivative.
It only adds a single init register.
Signed-off-by: Neil Armstrong
---
drivers/media/platform/meson/ao-cec-g12a.c | 37 +-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git
Add support for the General Purpose Amlogic SM1 Power controller,
dedicated to the PCIe, USB, NNA and GE2D Power Domains.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/Kconfig | 11 ++
drivers/soc/amlogic/Makefile | 1 +
drivers/soc/amlogic/meson-sm1-pwrc.c | 245
Add bindings for the new Amlogic SM1 SoC Family.
It a derivative of the G12A SoC Family with :
- Cortex-A55 core instead of A53
- more power domains
- a neural network co-processor
- a CSI input and image processor
Signed-off-by: Neil Armstrong
---
Add support for the Amlogic SM1 SoCs VPU Power Domain control,
it uses a different register for Isolation and a supplementaty
register for the domain memories power control.
Signed-off-by: Neil Armstrong
---
drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 120
1 file changed,
Add the compatible for the Amlogic SM1 Based SEI610 board.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml
Add AO-CEC compatible string for the Amlogic SM1 SoC family,
a derivate of the G12A AO-CECB controller.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/media/meson-ao-cec.txt | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git
Add support for the Amlogic SM1 Based SEI610 board.
The SM1 SoC is a derivative of the G12A SoC Family with :
- Cortex-A55 core instead of A53
- more power domains, including USB & PCIe
- a neural network co-processor (NNA)
- a CSI input and image processor
- some changes in the audio complex,
Add the Amlogic SM1 Compatible for the clk-measurer IP.
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt
On Fri 28-06-19 10:46:28, Alastair D'Silva wrote:
[...]
> Given that there is already a VM_BUG_ON in the code, how do you feel
> about broadening the scope from 'VM_BUG_ON(!root)' to 'VM_BUG_ON(!root
> || (root_nr == NR_SECTION_ROOTS))'?
As far as I understand the existing VM_BUG_ON will hit when
501 - 600 of 806 matches
Mail list logo
