On Fri, Apr 26, 2019 at 10:11:54AM +0200, CREGUT Pierre IMT/OLN wrote:
> I also initially thought that kobject_uevent generated the netlink event
> but this is not the case. This is generated by the specific driver in use.
> For the Intel i40e driver, this is the call to i40e_do_reset_safe in
> i40
On Tue, Oct 01, 2019 at 04:23:34PM +0200, Arnd Bergmann wrote:
> The new __must_check annotation on __copy_from_user successfully
> identified some code that has lacked the check since at least
> linux-2.1.73:
>
> arch/x86/math-emu/reg_ld_str.c:88:2: error: ignoring return value of function
> dec
Previously, there was an omap panel-dpi driver that would
read generic timings from the device tree and set the display
timing accordingly. This driver was removed so the screen
no longer functions. This patch modifies the panel-simple
file to setup the timings to the same values previously used.
Hi,
On 19. 8. 12. 오전 6:23, Dmitry Osipenko wrote:
> There are cases where unnecessary ACTMON interrupts could be avoided,
> like when one memory client device requests higher clock rate than the
> other or when clock rate is manually limited using sysfs devfreq
> parameters. These cases could be a
On 19. 8. 12. 오전 6:23, Dmitry Osipenko wrote:
> Now that all kHz-conversion related bugs are fixed, we can use the kHz
> uniformly. This makes code cleaner and avoids integer divisions in the
> code, which is useful in a case of Tegra30 that has Cortex A9 CPU that
> doesn't support integer division
Hi Alexandre,
On Tue, Oct 01, 2019 at 09:09:48PM +0200, Alexandre GRIVEAUX wrote:
> The JZ4780 have 2 core, adding to DT.
>
> Signed-off-by: Alexandre GRIVEAUX
> ---
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/mips/b
It may be related to the following sparse make warning:
No rule to make target
'/usr/include/x86_64-linux-gnu/bits/huge_val.h', needed by
'sparse-llvm.o'
I don't see huge_val.h in the Ubuntu 19 version of libc6-dev
Will send you the kernel config - but I am using the default one from
the Ubuntu
On Fri, Sep 20, 2019 at 8:58 AM Eugene Syromiatnikov wrote:
>
> Hello.
>
> This is a small fix of a typo (or, more specifically, some remnant of
> the old patch version spelling) in RWH_WRITE_LIFE_NOT_SET constant,
> which is named as RWF_WRITE_LIFE_NOT_SET currently. Since the name
> with "H" is
On Tue, Oct 01, 2019 at 11:28:16AM -0500, Steve French wrote:
> Updated sparse to get rid of some unneeded kernel sparse check
> warnings but now get many more
>
> I get 100s of warnings similar to
>
> ./include/linux/quota.h:114:17: error: Expected ( after asm
> ./include/linux/quota.h:114:17: e
On Fri, Sep 20, 2019 at 11:00 PM Dan Carpenter wrote:
>
> The first argument to WARN() is supposed to be a condition. The
> original code will just print the mdname() instead of the full warning
> message.
>
> Fixes: c84a1372df92 ("md/raid0: avoid RAID0 data corruption due to layout
> confusion.
Use interpolated brightness tables (added by commit 573fe6d1c25
("backlight: pwm_bl: Linear interpolation between
brightness-levels") for veyron, instead of specifying every single
step.
Another option would be to switch to a perceptual brightness curve
(CIE 1931), with the caveat that it would ch
On Tue, Oct 1, 2019 at 4:36 PM Alex G. wrote:
>
>
>
> On 10/1/19 4:14 PM, Stuart Hayes wrote:
> > Some systems have in-band presence detection disabled for hot-plug PCI
> > slots,
> > but do not report this in the slot capabilities 2 (SLTCAP2) register. On
> > these systems, presence detect can
On Tue, Oct 01, 2019 at 10:37:26AM -0700, Brian Vazquez wrote:
> This patch series fixes some fd leaks in tcp_rtt and
> test_sockopt_inherit bpf prof_tests.
>
> Brian Vazquez (2):
> selftests/bpf: test_progs: don't leak server_fd in tcp_rtt
> selftests/bpf: test_progs: don't leak server_fd in
-Original Message-
From: Sasha Levin
Sent: Tuesday, October 1, 2019 3:49 PM
> On Tue, Oct 01, 2019 at 08:41:43PM +, Pavel Shilovskiy wrote:
> >Hi Greg,
> >
> >Are you going to apply this patch to the 5.3.y stable kernel? The patch is
> >applicable there too.
>
> I will, yes.
Thanks
Kees Cook writes:
> On Tue, Oct 01, 2019 at 01:36:32PM -0500, Eric W. Biederman wrote:
>>
>> This system call has been deprecated almost since it was introduced, and
>> in a survey of the linux distributions I can no longer find any of them
>> that enable CONFIG_SYSCTL_SYSCALL. The only indicat
BCM7211 has a number of similarities with BCM2836, except the register
offsets are different and the bank bits are also different, account for
all of these differences.
Signed-off-by: Florian Fainelli
---
drivers/irqchip/irq-bcm2835.c | 86 +--
1 file changed, 72
With many different kind of interrupt controllers available and used on
7211, add prints to help determine which ones are registered.
Signed-off-by: Florian Fainelli
---
drivers/irqchip/irq-bcm2835.c | 9 +
drivers/irqchip/irq-bcm2836.c | 2 ++
2 files changed, 11 insertions(+)
diff --g
Now that irq-bcm2835.c and irq-bcm2836.c have been updated to support
BCM7211 which is under ARCH_BRCMSTB, build both drivers for
ARCH_BRCMSTB.
Signed-off-by: Florian Fainelli
---
drivers/irqchip/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig
BCM7211 uses a very similar root interrupt controller than what exists on
BCM2836, define a specific compatible string to key off specific
behavior.
Signed-off-by: Florian Fainelli
---
.../bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt| 4 +++-
1 file changed, 3 insertions(+), 1 dele
On Tue, Oct 01, 2019 at 08:41:43PM +, Pavel Shilovskiy wrote:
Hi Greg,
Are you going to apply this patch to the 5.3.y stable kernel? The patch is
applicable there too.
I will, yes.
--
Thanks,
Sasha
The root interrupt controller on 7211 is about identical to the one
existing on BCM2836, except that the SMP cross call are done through the
standard ARM GIC-400 interrupt controller. This interrupt controller is
used for side band wake-up signals though.
Signed-off-by: Florian Fainelli
---
driv
Hi Marc, Jason, Thomas,
This patch series updates the BCM2835 and BCM2836 interrupt controller
drivers to support BCM7211 which can make use of those drivers in some
configurations where the ARM GIC is muxed out and the legacy ARM
interrupt controller is used instead.
Thank you!
Florian Fainelli
Both irq-bcm2835.c and irq-bcm2836.c are currently used with
ARCH_BCM2835 but are soon going to be used with ARCH_BRCMSTB, introduce
a Kconfig symbol to make that those drivers selected/built by other
platforms.
Signed-off-by: Florian Fainelli
---
drivers/irqchip/Kconfig | 5 +
drivers/irqc
BCM7211 features a second level interrupt controller similar in nature
to BCM2836, with a few modifications to the register offsets, document
that specific compatible string.
Signed-off-by: Florian Fainelli
---
.../interrupt-controller/brcm,bcm2835-armctrl-ic.txt| 6 --
1 file change
On Tue, Oct 01, 2019 at 05:01:23PM -0400, Joel Fernandes wrote:
> On Tue, Oct 01, 2019 at 01:39:47PM -0400, Alan Stern wrote:
> > This patch fixes a few minor typos and improves word usage in a few
> > places in the Linux Kernel Memory Model's explanation.txt file.
> >
> > Signed-off-by: Alan Ster
Hi all,
In commit
e66e52c5b742 ("ASoC: SOF: pcm: fix resource leak in hw_free")
Fixes tag
Fixes: c29d96c3b9b4 ("ASoC: SOF: reset DMA state in prepare")
has these problem(s):
- Target SHA1 does not exist
Did you mean
Fixes: 04c8027764bc ("ASoC: SOF: reset DMA state in prepare")
--
Ch
On Fri, 20 Sep 2019 18:21:24 +0200, Krzysztof Kozlowski wrote:
> Include generic watchdog DT schema bindings in Amlogic GXBB Watchdog
> bindings.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> .../devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml | 3 +++
> 1 file changed, 3 insertions(
On Fri, Sep 20, 2019 at 06:21:22PM +0200, Krzysztof Kozlowski wrote:
> Convert Samsung S3C/S5P/Exynos watchdog bindings to DT schema format
> using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes since v1:
> 1. Indent example with four spaces (more readable),
> 2. Remove
On Mon, Sep 30, 2019 at 10:00:35AM -0400, Waiman Long wrote:
On 9/29/19 9:46 PM, Tetsuo Handa wrote:
On 2019/09/30 9:28, Sasha Levin wrote:
On Sun, Sep 29, 2019 at 11:43:38PM +0900, Tetsuo Handa wrote:
On 2019/09/29 22:54, Greg Kroah-Hartman wrote:
From: Waiman Long
[ Upstream commit 513e10
Hi!
> Secondly there are lots of coding style issues, see:
> https://www.kernel.org/doc/html/v4.10/process/coding-style.html
I addressed most of these except one "#if 0" warning from checkpatch.
> I'm afraid there are many problems with this patch. First of all it looks
> like support was added
On Fri, 20 Sep 2019 13:52:26 +0200, Stefan Riedmueller wrote:
> Add devicetree bindings for i.MX6 based phyCORE-i.MX6, phyBOARD-Mira and
> phyFLEX-i.MX6.
>
> Signed-off-by: Stefan Riedmueller
> ---
> Changes in v2:
> - Use seperate description for each board instead of squashing them into
>t
On Fri, 20 Sep 2019 13:52:25 +0200, Stefan Riedmueller wrote:
> Add devicetree bindings for i.MX6 UL/ULL based phyCORE-i.MX6 UL/ULL and
> phyBOARD-Segin.
>
> Signed-off-by: Stefan Riedmueller
> ---
> Changes in v2:
> - Use seperate description for each board instead of squashing them into
>t
The commit 87eaceb3faa59b9b4d940ec9554ce251325d83fe ("mm: thp: make
deferred split shrinker memcg aware") makes deferred split queue per
memcg to resolve memcg pre-mature OOM problem. But, all nodes end up
sharing the same queue instead of one queue per-node before the commit.
It is not a big deal
On Wed, Aug 21, 2019 at 10:26:41AM +0200, Paolo Bonzini wrote:
> Even though it is preferrable to use SPEC_CTRL (represented by
> X86_FEATURE_AMD_SSBD) instead of VIRT_SPEC, VIRT_SPEC is always
> supported anyway because otherwise it would be impossible to
> migrate from old to new CPUs. Make this
On Thu, Sep 19, 2019 at 08:11:02AM -0400, Jianxin Pan wrote:
> Add the bindings for the Amlogic Secure power domains, controlling the
> secure power domains.
>
> The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the
> power domain registers are in secure world.
>
> Signed-off-b
On Wed, Sep 18, 2019 at 10:18:20PM -0400, Thara Gopinath wrote:
> Introduce a new binding parameter to thermal trip point description
> to indicate whether the temperature level specified by the trip point
> is monitored for a rise or fall in temperature.
What if it is both?
When do you need this
On Wed, Sep 18, 2019 at 09:38:53PM +0200, Martin Kaiser wrote:
> According to
> Documentation/devicetree/bindings/display/panel/display-timing.txt,
> native-mode is a property of the display-timings node.
>
> If it's located outside of display-timings, the native-mode setting is
> ignored and the
On Wed, Sep 18, 2019 at 04:06:37PM -0400, vincent.cheng...@renesas.com wrote:
> From: Vincent Cheng
>
> Add device tree binding doc for the IDT ClockMatrix PTP clock driver.
Bindings are for h/w, not drivers...
>
> Signed-off-by: Vincent Cheng
> ---
> Documentation/devicetree/bindings/ptp/pt
On Wed, Sep 18, 2019 at 03:32:14PM -0700, rana...@codeaurora.org wrote:
> On 2019-09-18 13:13, Rob Herring wrote:
> > On Wed, Sep 18, 2019 at 1:47 PM Raghavendra Rao Ananta
> > wrote:
> > >
> > > On some embedded systems, the '/memory' dt-property gets updated
> > > by the bootloader (for example
We have added polled mode to the normal input devices with the intent of
retiring input_polled_dev. This converts psxpad-spi driver to use the
polling mode of standard input devices and removes dependency on
INPUT_POLLDEV.
Signed-off-by: Dmitry Torokhov
---
drivers/input/joystick/Kconfig |
My name is Mrs Munasalem Mustapha from France,
I know that this message might come to you as surprise because we
don't know each other nor have we ever met before but accept it with
an open and positive mind. I have a Very important request that made
me to contact you; I was diagnosed with ovarian
On Tue, Oct 01, 2019 at 02:32:54PM -0700, Nick Desaulniers wrote:
> On Tue, Oct 1, 2019 at 2:26 PM Russell King - ARM Linux admin
> wrote:
> >
> > On Tue, Oct 01, 2019 at 09:59:38PM +0100, Russell King - ARM Linux admin
> > wrote:
> > > On Tue, Oct 01, 2019 at 01:21:44PM -0700, Nick Desaulniers w
On 10/1/19 10:31 PM, David Rientjes wrote:
> On Tue, 1 Oct 2019, Vlastimil Babka wrote:
>
>> diff --git a/mm/mempolicy.c b/mm/mempolicy.c
>> index 4ae967bcf954..2c48146f3ee2 100644
>> --- a/mm/mempolicy.c
>> +++ b/mm/mempolicy.c
>> @@ -2129,18 +2129,20 @@ alloc_pages_vma(gfp_t gfp, int order, stru
Speakup exposes a set of sysfs attributes under
/sys/accessibility/speakup/ for user-space to interact with and
configure speakup's kernel modules. This patch describes those
attributes. Some attributes either lack a description or contain
incomplete description. They are marked wit TODO.
Authored
Introduce an asm/sync.h header which provides infrastructure that can be
used to generate sync instructions of various types, and for various
reasons. For example if we need a sync instruction that provides a full
completion barrier but only on systems which have weak memory ordering,
we can genera
Rather than #ifdef on CONFIG_CPU_* to determine whether the ins
instruction is supported we can simply check MIPS_ISA_REV to discover
whether we're targeting MIPSr2 or higher. Do so in order to clean up the
code.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h
Implement __sync() using the new __SYNC() infrastructure, which will
take care of not emitting an instruction for old R3k CPUs that don't
support it. The only behavioral difference is that __sync() will now
provide a compiler barrier on these old CPUs, but that seems like
reasonable behavior anyway
We define macros in asm/atomic.h which end each line with space
characters before a backslash to continue on the next line. Remove the
space characters leaving tabs as the whitespace used for conformity with
coding convention.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/includ
We #ifdef on Cavium Octeon CPUs, but emit the same sync instruction in
both cases. Remove the #ifdef & simply expand to the __sync() macro.
Whilst here indent the strong ordering case definitions to match the
indentation of the weak ordering ones, helping readability.
Signed-off-by: Paul Burton
When targeting MIPSr6 or higher make use of a compact branch in LL/SC
loops, preventing the insertion of a delay slot nop that only serves to
waste space.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/llsc.h | 4
1 file changed, 4 insertions(+)
diff --git a/arc
Remove the remaining duplication between 32b & 64b in asm/atomic.h by
making use of an ATOMIC_OPS() macro to generate:
- atomic_read()/atomic64_read()
- atomic_set()/atomic64_set()
- atomic_cmpxchg()/atomic64_cmpxchg()
- atomic_xchg()/atomic64_xchg()
This is consistent with the way all ot
Handle the !kernel_uses_llsc path first in our ATOMIC_OP(),
ATOMIC_OP_RETURN() & ATOMIC_FETCH_OP() macros & return from within the
block. This allows us to de-indent the kernel_uses_llsc path by one
level which will be useful when making further changes.
Signed-off-by: Paul Burton
---
Changes in
The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already
return a zero or one, so there's no need to perform another comparison
against zero. Move these comparisons into the LLSC paths to avoid the
redundant work.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/includ
The loongson_llsc_mb() macro is no longer used - instead barriers are
emitted as part of inline asm using the __SYNC() macro. Remove the
now-defunct loongson_llsc_mb() macro.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/barrier.h | 40 ---
Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had
On Tue, Oct 01, 2019 at 04:23:35PM +0200, Arnd Bergmann wrote:
> The fpu emulation code is old and fragile in places, try to limit its
> use to builds for CPUs that actually use it. As far as I can tell,
> this is only true for i486sx compatibles, including the Cyrix 486SLC,
> AMD Am486SX and ÉLAN
When Loongson3 LL/SC errata workarounds are enabled (ie.
CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) run a tool to scan through the
compiled kernel & ensure that the workaround is applied correctly. That
is, ensure that:
- Every LL or LLD instruction is preceded by a sync instruction.
- Any branches
The logical operations or & xor used in the test_and_set_bit_lock(),
test_and_clear_bit() & test_and_change_bit() functions currently force
the value 1<
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/mi
Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had
Reorder conditions in our various bitops functions that check
kernel_uses_llsc such that they handle the !kernel_uses_llsc case first.
This allows us to avoid the need to duplicate the kernel_uses_llsc check
in all the other cases. For functions that don't involve barriers common
to the various imp
Use smp_mb__before_atomic() rather than smp_mb__before_llsc() in
test_and_set_bit(), test_and_clear_bit() & test_and_change_bit(). The
_atomic() versions make semantic sense in these cases, and will allow a
later patch to omit redundant barriers for Loongson3 systems that
already include a barrier
Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already
emit a full completion barrier as part of the inline assembly containing
LL/SC loops for atomic operations. As such the barrier emitted by
__smp_mb__before_atomic() is redundant, and we can remove it.
Signed-off-by: Paul Burto
Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had
set_bit() can set bits 0-15 using an ori instruction, rather than
loading the value -1 into a register & then using an ins instruction.
That is, rather than the following:
li t0, -1
ll t1, 0(t2)
ins t1, t0, 4, 1
sc t1, 0(t2)
We can have the simpler:
ll t1, 0(t2)
ori t1, t1
Rather than using custom SZLONG_LOG & SZLONG_MASK macros to shift & mask
a bit index to form word & bit offsets respectively, make use of the
standard BIT_WORD() & BITS_PER_LONG macros for the same purpose.
volatile is added to the definition of pointers to the long-sized word
we'll operate on, in
In ejtag_debug_handler we use LL & SC instructions to acquire & release
an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
this requires that we insert a sync instruction prior to the LL in order
to ensure correct behavior of the LL/SC loop.
Signed-off-by: Paul Burton
---
Cha
Use the BIT() macro in asm/bitops.h rather than open-coding its
equivalent.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/bitops.h | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/mips/include/asm/bitops.h b/a
Introduce __bit_op() & __test_bit_op() macros which abstract away the
implementation of LL/SC loops. This cuts down on a lot of duplicate
boilerplate code, and also allows R1_LLSC_WAR to be handled outside
of the individual bitop functions.
Signed-off-by: Paul Burton
---
Changes in v2: None
When building a kernel configured to support Loongson3 LL/SC workarounds
(ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) the inline assembly in
__xchg_asm() & __cmpxchg_asm() already emits completion barriers, and as
such we don't need to emit extra barriers from the xchg() or cmpxchg()
macros. Add compil
Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had
The only difference between test_and_set_bit() & test_and_set_bit_lock()
is memory ordering barrier semantics - the former provides a full
barrier whilst the latter only provides acquire semantics.
We can therefore implement test_and_set_bit() in terms of
test_and_set_bit_lock() with the addition
In ejtag_debug_handler() we must reload the address of
ejtag_debug_buffer_spinlock if an sc fails, since the address in k0 will
have been clobbered by the result of the sc instruction. In the case
where we simply load a non-zero value (ie. there's contention for the
lock) the address will not be cl
Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had
Use smp_mb__before_atomic() & smp_mb__after_atomic() in
atomic_sub_if_positive() rather than the equivalent
smp_mb__before_llsc() & smp_llsc_mb(). The former are more standard &
this preps us for avoiding redundant duplicate barriers on Loongson3 in
a later patch.
Signed-off-by: Paul Burton
---
The start position for an ins instruction is always encoded as an
immediate, so allowing registers to be used by the inline asm makes no
sense. It should never happen anyway since a bit index should always be
small enough to be treated as an immediate, but remove the nonsensical
"r" for sanity.
Si
Use the new __SYNC() infrastructure to implement sync_ginv(), for
consistency with much of the rest of the asm/barrier.h.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/barrier.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/include/asm
Unify the definitions of atomic_sub_if_positive() &
atomic64_sub_if_positive() using a macro like we do for most other
atomic functions. This allows us to share the implementation ensuring
consistency between the two. Notably this provides the appropriate
loongson3_war barriers in the atomic64_sub_
Simplify our definitions of rmb() & wmb() using the new __SYNC()
infrastructure.
The fast_rmb() & fast_wmb() macros are removed, since they only provided
a level of indirection that made the code less readable & weren't
directly used anywhere in the kernel tree.
The Octeon #ifdef'ery is removed,
Cut down on duplication by generalizing the ATOMIC_OP(),
ATOMIC_OP_RETURN() & ATOMIC_FETCH_OP() macros to work for both 32b &
64b atomics, and removing the ATOMIC64_ variants. This ensures
consistency between our atomic_* & atomic64_* functions.
Signed-off-by: Paul Burton
---
Changes in v2: None
We currently duplicate the definition of __scbeqz in asm/atomic.h &
asm/cmpxchg.h. Move it to asm/llsc.h & rename it to __SC_BEQZ to fit
better with the existing __SC macro provided there.
We include a tab in the string in order to avoid the need for users to
indent code any further to include whi
This series consists of a bunch of cleanups to the way we handle memory
barriers (though no changes to the sync instructions we use to implement
them) & atomic memory accesses. One major goal was to ensure the
Loongson3 LL/SC errata workarounds are applied in a safe manner from
within inline-asm &
The definition of fast_mb() is the same in both the Octeon & non-Octeon
cases, so remove the duplication & define it only once.
Signed-off-by: Paul Burton
---
Changes in v2: None
arch/mips/include/asm/barrier.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/i
On Tue, Oct 01, 2019 at 04:40:26PM -0500, Dinh Nguyen wrote:
> With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
> amba bus probe", the amba bus driver needs to be deferred probe because the
> reset driver is probed later than the amba bus. However with a deferred
> probe, t
On Tue, Oct 01, 2019 at 11:07:28AM +0100, Andrew Murray wrote:
> Hi Tom,
>
> Thanks for the patch.
>
> I'd suggest that you rename the subject of this series to "PCI: cadence: ..."
> to be consistent with the existing commit history, e.g. git log
> --oneline drivers/pci/controller/pcie-cadence*
With commit "79bdcb202a35 ARM: 8906/1: drivers/amba: add reset control to
amba bus probe", the amba bus driver needs to be deferred probe because the
reset driver is probed later than the amba bus. However with a deferred
probe, the call to request_resource() in the driver returns -EBUSY. The
reaso
On 10/1/19 4:14 PM, Stuart Hayes wrote:
Some systems have in-band presence detection disabled for hot-plug PCI slots,
but do not report this in the slot capabilities 2 (SLTCAP2) register. On
these systems, presence detect can become active well after the link is
reported to be active, which c
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I know that this message might come to you as surprise because we
don't know each other nor have we ever met before but accept it with
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On Tue, Oct 1, 2019 at 2:26 PM Russell King - ARM Linux admin
wrote:
>
> On Tue, Oct 01, 2019 at 09:59:38PM +0100, Russell King - ARM Linux admin
> wrote:
> > On Tue, Oct 01, 2019 at 01:21:44PM -0700, Nick Desaulniers wrote:
> > > On Tue, Oct 1, 2019 at 11:14 AM Russell King - ARM Linux admin
> >
Hi,
On 19. 10. 1. 오후 9:46, Marek Szyprowski wrote:
> The error code is propagated to the caller, so there is no need to keep
> it additionally in the unused variable.
>
> Signed-off-by: Marek Szyprowski
> ---
> drivers/devfreq/event/exynos-ppmu.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff
On Tue, Oct 01, 2019 at 09:59:38PM +0100, Russell King - ARM Linux admin wrote:
> On Tue, Oct 01, 2019 at 01:21:44PM -0700, Nick Desaulniers wrote:
> > On Tue, Oct 1, 2019 at 11:14 AM Russell King - ARM Linux admin
> > wrote:
> > >
> > > On Tue, Oct 01, 2019 at 11:00:11AM -0700, Nick Desaulniers w
Hi,
On Tue, Oct 1, 2019 at 10:44 AM Stephen Boyd wrote:
>
> We don't check for errors from clk_ops::get_phase() before storing away
> the result into the clk_core::phase member. This can lead to some fairly
> confusing debugfs information if these ops do return an error. Let's
> skip the store wh
On Fri, Sep 20, 2019 at 04:18:57PM +0200, Marco Elver wrote:
> Hi all,
>
> We would like to share a new data-race detector for the Linux kernel:
> Kernel Concurrency Sanitizer (KCSAN) --
> https://github.com/google/ktsan/wiki/KCSAN (Details:
> https://github.com/google/ktsan/blob/kcsan/Documentat
Hello Marc,
On 10/1/19 4:32 PM, Marc Kleine-Budde wrote:
> On 9/26/19 10:50 AM, Jeroen Hofstee wrote:
>> When the C_CAN interface is closed it is put in power down mode, but
>> does not reset the error counters / state. So reset the D_CAN on open,
>> so the reported state and the actual state matc
Dan,
On 10/1/19 8:04 PM, Dan Murphy wrote:
> Update the Kconfig to be consistent in the case of using
> "LED" in the Kconfig. LED is an acronym and should be
> capitalized.
>
> Signed-off-by: Dan Murphy
> ---
> drivers/leds/Kconfig | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Some systems have in-band presence detection disabled for hot-plug PCI slots,
but do not report this in the slot capabilities 2 (SLTCAP2) register. On
these systems, presence detect can become active well after the link is
reported to be active, which can cause the slots to be disabled after a
dev
In older PCIe specs, PDS (presence detect) would come up when the
"in-band" presence detect pin connected, and would be up before DLLLA
(link active).
In PCIe 4.0 (as an ECN) and in PCIe 5.0, there is a new bit to show if
in-band presence detection can be disabled for the slot, and another bit
tha
On Tue, Oct 1, 2019 at 2:06 PM Miguel Ojeda
wrote:
>
> On Tue, Oct 1, 2019 at 10:53 PM Arnd Bergmann wrote:
> >
> > 1. is clearly the most common case, but there is also
> >
> > 4. Some compiler version (possibly long gone, possibly still current)
> > makes bad inlining decisions that result in h
When inband presence is disabled, PDS may come up at any time, or not
at all. PDS being low may indicate that the card is still mating, and
we could expect contact bounce to bring down the link as well.
It is reasonable to assume that most cards will mate in a hotplug slot
in about a second. Thus,
The presence detect state (PDS) is normally a logical or of in-band and
out-of-band presence. As of PCIe 4.0, there is the option to disable
in-band presence so that the PDS bit always reflects the state of the
out-of-band presence.
The recommendation of the PCIe spec is to disable in-band presenc
12.08.2019 00:22, Dmitry Osipenko пишет:
> Hello,
>
> This series addresses some additional review comments that were made by
> Thierry Reding to [1], makes several important changes to the driver,
> fixing excessive interrupts activity, and adds new features. In the end
> I'm proposing myself as
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